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Pentacene thin-film transistors on polymeric gate dielectric: device fabrication and electrical characterization
Journal of Non-Crystalline Solids 338–340 (2004) 617–621 www.elsevier.com/locate/jnoncrysol
Pentacene thin-film transistors on polymeric gate dielectric: device fabrication and electrical characterization J. Puigdollers *, C. Voz, I. Martin, A. Orpella, M. Vetter, R. Alcubilla Departament d’Enginyeria Electronica, Universitat Politecnica de Catalunya c/ Jordi Girona 1-3, Modul C4, Barcelona 08034, Spain Available online 9 April 2004
Abstract Pentacene thin-film transistors using polymethyl methacrylate as a gate dielectric have been fabricated. A bottom gate, inverted staggered structure was selected to study the influence of the dielectric on the device performance. Crystalline silicon wafers and polyethylenenaphtalate polymer foils were used as substrates. Pentacene thin-films were deposited by thermal evaporation in a highvacuum system. The maximum process temperature was 170 C, corresponding to the baking of polymethyl methacrylate. These devices showed satisfactory p-type electrical characteristics with on/off ratios exceeding 103 for VGS ranging from )30 to 30 V. The field-effect mobility and threshold voltage were around 0.01 cm2 V1 s1 and )14 V, respectively. The polymethyl methacrylate dielectric also seems to provide some advantages of the so-called self-assembling monolayers. 2004 Elsevier B.V. All rights reserved. PACS: 61.10.H; 73.61.P; 72.80.L; 85.30.T
1. Introduction Organic thin-film transistors (OTFT) have the key advantage of relatively simple and low temperature processing. Therefore, OTFTs could be competitive for applications requiring large area coverage on inexpensive substrates. Such applications include smart cards, radio frequency identification tags and displays. The performance of OTFTs has considerably improved during the last years [1]. Among the variety of organic semiconductors, pentacene has allowed the highest electrical performance. Pentacene TFTs have already reached field-effect mobilities over 1 cm2 V1 s1 [2]. These values are comparable to those obtained with hydrogenated amorphous silicon (a-Si:H) TFTs, which are the devices commonly used in large area active matrix arrays. So far most of the pentacene TFTs have been fabricated using inorganic dielectrics such as thermally
*
Corresponding author. Tel.: +34-93 401 1002; fax: +34-93 401 6756. E-mail address: [email protected] (J. Puigdollers). 0022-3093/$ - see front matter 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.jnoncrysol.2004.03.054
grown silicon dioxide or plasma-enhanced chemical vapor deposited silicon nitride. In addition, OTFTs are usually fabricated on non-flexible substrates, like crystalline silicon or glass. However, the use of plastic substrates to obtain flexible devices is more challenging. Nevertheless, some plastic substrates could not be compatible with the high or moderate temperature processes used to obtain standard inorganic dielectrics. Alternative polymeric dielectrics which can be spin cast or dip coated on inexpensive substrates are more desirable. In this paper we present pentacene TFTs using polymethyl methacrylate (PMMA) as a gate dielectric material. The thermal and mechanical stability of PMMA, together with its high resistivity (>2 · 1015 X cm) and suitable dielectric constant (e ¼ 2:6 @ 1 MHz, e ¼ 3:9 @ 60 Hz), make of PMMA a good candidate as a dielectric layer for OTFTs. In addition, its low baking temperature (<170 C) is compatible with plastic substrates. The first part of the paper deals with the influence of the substrate on the structural properties of thermally evaporated pentacene thin-films. Unlike with other inorganic semiconductors as a-Si:H, the properties of pentacene layers are strongly dependent on the base layer. In particular, we have studied the
618
J. Puigdollers et al. / Journal of Non-Crystalline Solids 338–340 (2004) 617–621
structural properties of pentacene films grown on bare and PMMA-coated glass substrates. The last part of the paper presents the electrical characteristics of the fabricated pentacene TFTs using PMMA as a gate dielectric. The temperature dependence of the field-effect mobility can provide valuable information about the electronic transport in pentacene TFTs.
pentacene layer is about 800 nm. It is worth mentioning that these devices are fabricated without any photolithographic step. Besides, the maximum process temperature is 170 C that corresponds to the baking of PMMA. The electrical characterization of the fabricated devices was done by means of a HP4145B parameter analyzer and a MMR Technologies K-20 temperature controller.
2. Experimental 3. Results
source and drain contacts (Au) pentacene
3.1. Material characterization The microstructure of the pentacene thin-films was studied by X-ray diffraction (XRD). Fig. 2 shows the XRD pattern of pentacene films deposited in the same run on bare and on PMMA-coated glass substrates. The thickness of these layers was around 1 lm. An overall increase of the diffraction pattern is observed for the pentacene film on PMMA. Nevertheless, both samples exhibit high structural order and the coexistence of thinfilm (phase 1) and bulk (phase 2) triclinic phases, labeled (0 0 l) and (0 0 l0 ) respectively [3]. It has been shown that s1 ) or high substrate either low deposition rates (<1 A temperatures (>80 C) enhance the bulk crystalline phase [4]. Although these are not the conditions used to grow our pentacene films, both XRD patterns evidence a high bulk phase fraction. We could attribute this effect to the relatively thick pentacene films used for the XRD measurements. As might be expected, the bulk phase of pentacene is enhanced with the thickness of the film [4]. Considering the pentacene film on bare glass, first order diffraction peaks appear at 5.90 (phase 1) and 6.32 (phase 2). These diffraction angles correspond to vertical respectively. The periodicities of 14.98 and 13.98 A, pentacene film grown on PMMA shows diffraction
(001) 6.18°
Counts(a.u.)
Pentacene thin-films were deposited by thermal evaporation in a high-vacuum system with base pressure 106 mbar. The pentacene source is available from Aldrich Chemical (98%) and further purification processes were not performed. The pentacene thin-films were grown at room temperature and high deposition rates s1 ). Both bare and PMMA spin-coated glass (>20 A substrates (Corning 7059) were used to study the influence of the polymeric dielectric on the properties of pentacene films. The PMMA was spun at 4000 r.p.m. for 40 s to form an uniform dielectric coating around 700 nm thick. X-ray diffraction (XRD) and atomic force microscope (AFM) techniques were used to evaluate the microstructure and surface morphology of the films. All these experiments were done with pentacene layers around 1 lm thick. In addition, pentacene TFTs were fabricated to evaluate the feasibility of PMMA as a gate dielectric material in field-effect devices. An inverted staggered configuration was selected, which schematic structure is shown in Fig. 1. The bottom-gate was a chromium layer thermally evaporated on both crystalline silicon and polyethylenenaphtalate (PEN) substrates. Crystalline silicon was used because of its flatness, whereas PEN substrates were also tested to fabricate flexible devices. In order to define and isolate the devices, pentacene was evaporated through a metallic mask. Finally, gold contacts were thermally evaporated through a shadow mask to form the drain and source electrodes. The pentacene TFTs thereby obtained have a channel length and width of 120 and 600 lm, respectively. The thickness of the
on PMMA (001') 5.78°
on bare glass
PMMA gate dielectric gate electrode(Cr) c-Si substrate
Fig. 1. Schematic cross-section of a pentacene TFT. The width of the channel was 600 lm, its length 120 lm, and the thickness of the PMMA gate dielectric was 700 nm.
(002) 12.34°
(001') 5.90°
5
(001) 6.32°
10
(004) 24.82°
(003) 18.56°
(002') 11.50°
(004') 24.08°
(003') 17.32°
15
20
25
2θ(°) Fig. 2. XRD spectra of pentacene films deposited in the same run on bare and PMMA-coated glass substrates. The first order diffraction peak of the sample on bare glass has been also indexed to evidence the angle shift.
J. Puigdollers et al. / Journal of Non-Crystalline Solids 338–340 (2004) 617–621
619
Fig. 3. AFM topographic images of pentacene films deposited on thermally grown silicon dioxide (a) and PMMA layers spin cast on crystalline silicon (b).
0.0
10 10 10 10 10
-0.1 VGS =-20 V
-1
ID ( µA)
10
ID ( µA)
peaks at 5.78 and 6.18, for layer-by-layer spacings of 15.29 and 14.30 A. In order to investigate the influence of the PMMA surface on the microstructure of pentacene layers, we have compared AFM images of films deposited on PMMA and on silicon dioxide. The topographic image of the pentacene film on silicon dioxide (Fig. 3(a)) shows a uniform and smooth surface. By contrast, when deposited on PMMA (Fig. 3(b)), a granular microstructure with a root mean square roughness around 70 nm is observed. Bigger crystalline domains for the pentacene film on PMMA could explain this morphology, though further research on thinner samples is under way for more confident conclusions.
-2
-0.2 -0.3
VGS =-30 V
-0.4 -0.5
-3
VGS =-40 V -0.6 -40 -30 -20
-4
-10
0
VDS (V)
-5
-6
V DS = -40V
3.2. Device characterization -40
Several pentacene TFTs have been fabricated using either silicon dioxide or PMMA as a gate dielectric. The pentacene active film of the devices was deposited in the same run. All the devices on silicon dioxide showed poor electrical characteristics. However, the use of PMMA as a dielectric layer allowed us the fabrication of devices with good electrical performance. Fig. 4 shows the electrical characteristics of a pentacene TFT fabricated on PMMA-coated crystalline silicon. The main plot is the transfer characteristic measured at room temperature, i.e., the drain current (ID ) as a function of the gate-source voltage (VGS ) at a drain–source voltage (VDS ) of )40 V. The inset shows the output characteristic, i.e., ID as a function of VDS for different VGS values. The device exhibits typical ptype characteristics with on/off ratios over 103 for VGS ranging from )30 to 30 V. It can be observed that these devices are off for zero-applied VGS voltages. This is an important advantage to be considered for low power consumption applications [5].
-30
-20
-10
0
10
20
30
40
VGS (V) Fig. 4. Transfer characteristic of a pentacene TFT fabricated on PMMA-coated crystalline silicon. The inset shows the output characteristic of the same device measured at different VGS voltages.
The field-effect mobility (l) and threshold voltage (VT ) of the TFT can be calculated from a linear fit to the saturation characteristic (Fig. 5), i.e., the square root of ID as a function of VDS in the saturation regime (VGS ¼ VDS ). The values obtained at room temperature are l ¼ 0:01 cm2 V1 s1 and VT ¼ 14 V. The temperature dependence of l can be obtained by fitting the saturation characteristics measured at different temperatures. A simple Arrhenius behavior with an activation energy of 90 meV was observed (inset of Fig. 5). This result will be discussed in Section 4. Devices with the same structure on flexible PEN substrates also showed satisfactory output and transfer characteristics. Nevertheless, in that case l was
620
J. Puigdollers et al. / Journal of Non-Crystalline Solids 338–340 (2004) 617–621 0.5
-1
µ (cm V s )
0.02
ID ( µA
1/2
)
2
-1
0.4
0.3
0.01 2.8
0.1
3.0
3.2
3.4
1000/T (K-1)
0.2
T = 300 - 360 K
VDS =V GS 0.0 -40
-30
-20
-10
0
VDS (V) Fig. 5. Saturation characteristic of a pentacene TFT measured at temperatures ranging from 300 to 360 K. The inset is an Arrhenius plot of the field-effect mobility.
significantly reduced to 103 cm2 V1 s1 , probably because of the natural roughness of PEN substrates. On the other hand, VT was around zero-applied voltage. 4. Discussion These previous results seem to indicate that, besides the deposition conditions, the growth process of pentacene is also affected by the base layer. It has been reported that the properties of the surface onto which pentacene is grown influence the quality of the material. In this sense, the incorporation of self-assembling monolayers (SAM) leads to highly ordered pentacene films [2]. As shown in Section 3.1, the XRD peaks of pentacene films on PMMA are slightly shifted towards lower diffraction angles compared to films on silicon for dioxide. The lattice spacings of 15.29 and 14.30 A phase 1 and 2 correspond to a tilt of the molecules of 17.2 and 26.7 to the surface normal. In this calculation it is assumed a triclinic single crystal structure and [3]. In the a length of the pentacene molecule of 16.01 A case of pentacene films on silicon dioxide, tilt angles of 20.7 and 29.2 were obtained for phase 1 and 2, respectively. These results seem to indicate that pentacene molecules prefer to grow more vertically on the PMMA surface. Similar results have been reported with the use of octadecyltrichlorosilane (OTS), which is one of the most widely studied SAM for pentacene films [2]. Actually, like OTS, PMMA has the methyl ending groups (–CH3 ) which promote the growth of highly ordered pentacene layers [6]. It could be concluded that the use of PMMA as a gate dielectric layer in pentacene
TFTs yields several advantages (a) it can be easily deposited over large areas by spin coating, (b) its low baking temperature allows the use of plastic substrates, and finally (c) the methyl ending groups improve the pentacene ordering like a SAM does. The thermal dependence of the field-effect mobility shows an activated behavior that has been attributed to hole trapping near the valence band edge [7]. A band tail of trap states is usually observed in amorphous and polycrystalline materials due to their inherent structural disorder. The presence of an Urbach’s front in the photothermal deflection spectra also indicates an exponential band tail in pentacene thin-films [8]. The relatively high activation energy of the field-effect mobility (90 meV) compared to the published data (<50 meV) [9] could be due to a broader band tail. Actually, in our case neither the growth rate nor the substrate temperature have been optimized to improve the quality of the films. This could also explain the low field-effect mobilities that have been measured. Additional research is in progress to improve the pentacene TFTs performance by tailoring the deposition conditions. 5. Conclusions Pentacene TFTs with good electrical characteristics were fabricated using PMMA as a gate dielectric layer. This polymeric insulator with low baking temperature (170 C) can be spin cast on inexpensive substrates. Moreover, the particular surface of PMMA seems to enhance the crystallinity of pentacene films. The effect on the ordering of pentacene molecules could be similar to that of SAMs. Thus, PMMA arises as a very promising candidate for replacing inorganic dielectrics hardly compatible with flexible substrates in pentacene TFTs. The deposition conditions of pentacene films should be optimized to guess the actual possibilities of PMMA as a dielectric layer. The state of the art pentacene TFTs are s1 ) and modobtained at low deposition rates (<1 A erate substrate temperatures (<100 C). In the near future we will investigate this range of deposition conditions expecting a certain improvement of the fieldeffect mobility value. Acknowledgements This work has been supported by the CICYT of the Spanish Government under Programme MAT200204263 and by the PICS2002-4 Program of the Generalitat de Catalunya. References [1] J.M. Shaw, P.F. Seidler, IBM J. Res. Dev. 45 (2001) 3. [2] D.J. Gundlach, Y.Y. Lin, T.N. Jackson, IEEE Electron Dev. Lett. 18 (1997) 87.
J. Puigdollers et al. / Journal of Non-Crystalline Solids 338–340 (2004) 617–621 [3] C.D. Dimitrakopoulos, A.R. Brown, A. Pomp, J. Appl. Phys. 80 (1996) 2501. [4] I.P.M. Bouchoms, W.A. Schoonveld, J. Vrijmoeth, T.M. Klapwijk, Synth. Met. 104 (1999) 175. [5] H. Klauk, D.J. Gundlach, J.A. Nichols, C.D. Sheraw, M. Bonse, T.N. Jackson, Solid State Technol. 43 (2000) 63. [6] S.H. Jin, J.S. Yu, J.W. Kim, C.A. Lee, B.G. Park, J.D. Lee, J.H. Lee, Society for Information Display International Symposium,
621
Seminar and Exhibition (SID 2003), 18–23 May 2003, Baltimore, MD, USA. [7] R.A. Street, D. Knipp, R. V€ olkel, Appl. Phys. Lett. 80 (9) (2002) 1658. [8] J. Puigdollers, C. Voz, A. Orpella, I. Martin, M. Vetter, R. Alcubilla, Thin Solid Films 427 (2003) 367. [9] D. Knipp, R.A. Street, A. V€ olkel, App. Phys. Lett. 82 (22) (2003) 3907.
Pentacene thin-film transistors on polymeric gate dielectric: device fabrication and electrical characterization J. Puigdollers *, C. Voz, I. Martin, A. Orpella, M. Vetter, R. Alcubilla Departament d’Enginyeria Electronica, Universitat Politecnica de Catalunya c/ Jordi Girona 1-3, Modul C4, Barcelona 08034, Spain Available online 9 April 2004
Abstract Pentacene thin-film transistors using polymethyl methacrylate as a gate dielectric have been fabricated. A bottom gate, inverted staggered structure was selected to study the influence of the dielectric on the device performance. Crystalline silicon wafers and polyethylenenaphtalate polymer foils were used as substrates. Pentacene thin-films were deposited by thermal evaporation in a highvacuum system. The maximum process temperature was 170 C, corresponding to the baking of polymethyl methacrylate. These devices showed satisfactory p-type electrical characteristics with on/off ratios exceeding 103 for VGS ranging from )30 to 30 V. The field-effect mobility and threshold voltage were around 0.01 cm2 V1 s1 and )14 V, respectively. The polymethyl methacrylate dielectric also seems to provide some advantages of the so-called self-assembling monolayers. 2004 Elsevier B.V. All rights reserved. PACS: 61.10.H; 73.61.P; 72.80.L; 85.30.T
1. Introduction Organic thin-film transistors (OTFT) have the key advantage of relatively simple and low temperature processing. Therefore, OTFTs could be competitive for applications requiring large area coverage on inexpensive substrates. Such applications include smart cards, radio frequency identification tags and displays. The performance of OTFTs has considerably improved during the last years [1]. Among the variety of organic semiconductors, pentacene has allowed the highest electrical performance. Pentacene TFTs have already reached field-effect mobilities over 1 cm2 V1 s1 [2]. These values are comparable to those obtained with hydrogenated amorphous silicon (a-Si:H) TFTs, which are the devices commonly used in large area active matrix arrays. So far most of the pentacene TFTs have been fabricated using inorganic dielectrics such as thermally
*
Corresponding author. Tel.: +34-93 401 1002; fax: +34-93 401 6756. E-mail address: [email protected] (J. Puigdollers). 0022-3093/$ - see front matter 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.jnoncrysol.2004.03.054
grown silicon dioxide or plasma-enhanced chemical vapor deposited silicon nitride. In addition, OTFTs are usually fabricated on non-flexible substrates, like crystalline silicon or glass. However, the use of plastic substrates to obtain flexible devices is more challenging. Nevertheless, some plastic substrates could not be compatible with the high or moderate temperature processes used to obtain standard inorganic dielectrics. Alternative polymeric dielectrics which can be spin cast or dip coated on inexpensive substrates are more desirable. In this paper we present pentacene TFTs using polymethyl methacrylate (PMMA) as a gate dielectric material. The thermal and mechanical stability of PMMA, together with its high resistivity (>2 · 1015 X cm) and suitable dielectric constant (e ¼ 2:6 @ 1 MHz, e ¼ 3:9 @ 60 Hz), make of PMMA a good candidate as a dielectric layer for OTFTs. In addition, its low baking temperature (<170 C) is compatible with plastic substrates. The first part of the paper deals with the influence of the substrate on the structural properties of thermally evaporated pentacene thin-films. Unlike with other inorganic semiconductors as a-Si:H, the properties of pentacene layers are strongly dependent on the base layer. In particular, we have studied the
618
J. Puigdollers et al. / Journal of Non-Crystalline Solids 338–340 (2004) 617–621
structural properties of pentacene films grown on bare and PMMA-coated glass substrates. The last part of the paper presents the electrical characteristics of the fabricated pentacene TFTs using PMMA as a gate dielectric. The temperature dependence of the field-effect mobility can provide valuable information about the electronic transport in pentacene TFTs.
pentacene layer is about 800 nm. It is worth mentioning that these devices are fabricated without any photolithographic step. Besides, the maximum process temperature is 170 C that corresponds to the baking of PMMA. The electrical characterization of the fabricated devices was done by means of a HP4145B parameter analyzer and a MMR Technologies K-20 temperature controller.
2. Experimental 3. Results
source and drain contacts (Au) pentacene
3.1. Material characterization The microstructure of the pentacene thin-films was studied by X-ray diffraction (XRD). Fig. 2 shows the XRD pattern of pentacene films deposited in the same run on bare and on PMMA-coated glass substrates. The thickness of these layers was around 1 lm. An overall increase of the diffraction pattern is observed for the pentacene film on PMMA. Nevertheless, both samples exhibit high structural order and the coexistence of thinfilm (phase 1) and bulk (phase 2) triclinic phases, labeled (0 0 l) and (0 0 l0 ) respectively [3]. It has been shown that s1 ) or high substrate either low deposition rates (<1 A temperatures (>80 C) enhance the bulk crystalline phase [4]. Although these are not the conditions used to grow our pentacene films, both XRD patterns evidence a high bulk phase fraction. We could attribute this effect to the relatively thick pentacene films used for the XRD measurements. As might be expected, the bulk phase of pentacene is enhanced with the thickness of the film [4]. Considering the pentacene film on bare glass, first order diffraction peaks appear at 5.90 (phase 1) and 6.32 (phase 2). These diffraction angles correspond to vertical respectively. The periodicities of 14.98 and 13.98 A, pentacene film grown on PMMA shows diffraction
(001) 6.18°
Counts(a.u.)
Pentacene thin-films were deposited by thermal evaporation in a high-vacuum system with base pressure 106 mbar. The pentacene source is available from Aldrich Chemical (98%) and further purification processes were not performed. The pentacene thin-films were grown at room temperature and high deposition rates s1 ). Both bare and PMMA spin-coated glass (>20 A substrates (Corning 7059) were used to study the influence of the polymeric dielectric on the properties of pentacene films. The PMMA was spun at 4000 r.p.m. for 40 s to form an uniform dielectric coating around 700 nm thick. X-ray diffraction (XRD) and atomic force microscope (AFM) techniques were used to evaluate the microstructure and surface morphology of the films. All these experiments were done with pentacene layers around 1 lm thick. In addition, pentacene TFTs were fabricated to evaluate the feasibility of PMMA as a gate dielectric material in field-effect devices. An inverted staggered configuration was selected, which schematic structure is shown in Fig. 1. The bottom-gate was a chromium layer thermally evaporated on both crystalline silicon and polyethylenenaphtalate (PEN) substrates. Crystalline silicon was used because of its flatness, whereas PEN substrates were also tested to fabricate flexible devices. In order to define and isolate the devices, pentacene was evaporated through a metallic mask. Finally, gold contacts were thermally evaporated through a shadow mask to form the drain and source electrodes. The pentacene TFTs thereby obtained have a channel length and width of 120 and 600 lm, respectively. The thickness of the
on PMMA (001') 5.78°
on bare glass
PMMA gate dielectric gate electrode(Cr) c-Si substrate
Fig. 1. Schematic cross-section of a pentacene TFT. The width of the channel was 600 lm, its length 120 lm, and the thickness of the PMMA gate dielectric was 700 nm.
(002) 12.34°
(001') 5.90°
5
(001) 6.32°
10
(004) 24.82°
(003) 18.56°
(002') 11.50°
(004') 24.08°
(003') 17.32°
15
20
25
2θ(°) Fig. 2. XRD spectra of pentacene films deposited in the same run on bare and PMMA-coated glass substrates. The first order diffraction peak of the sample on bare glass has been also indexed to evidence the angle shift.
J. Puigdollers et al. / Journal of Non-Crystalline Solids 338–340 (2004) 617–621
619
Fig. 3. AFM topographic images of pentacene films deposited on thermally grown silicon dioxide (a) and PMMA layers spin cast on crystalline silicon (b).
0.0
10 10 10 10 10
-0.1 VGS =-20 V
-1
ID ( µA)
10
ID ( µA)
peaks at 5.78 and 6.18, for layer-by-layer spacings of 15.29 and 14.30 A. In order to investigate the influence of the PMMA surface on the microstructure of pentacene layers, we have compared AFM images of films deposited on PMMA and on silicon dioxide. The topographic image of the pentacene film on silicon dioxide (Fig. 3(a)) shows a uniform and smooth surface. By contrast, when deposited on PMMA (Fig. 3(b)), a granular microstructure with a root mean square roughness around 70 nm is observed. Bigger crystalline domains for the pentacene film on PMMA could explain this morphology, though further research on thinner samples is under way for more confident conclusions.
-2
-0.2 -0.3
VGS =-30 V
-0.4 -0.5
-3
VGS =-40 V -0.6 -40 -30 -20
-4
-10
0
VDS (V)
-5
-6
V DS = -40V
3.2. Device characterization -40
Several pentacene TFTs have been fabricated using either silicon dioxide or PMMA as a gate dielectric. The pentacene active film of the devices was deposited in the same run. All the devices on silicon dioxide showed poor electrical characteristics. However, the use of PMMA as a dielectric layer allowed us the fabrication of devices with good electrical performance. Fig. 4 shows the electrical characteristics of a pentacene TFT fabricated on PMMA-coated crystalline silicon. The main plot is the transfer characteristic measured at room temperature, i.e., the drain current (ID ) as a function of the gate-source voltage (VGS ) at a drain–source voltage (VDS ) of )40 V. The inset shows the output characteristic, i.e., ID as a function of VDS for different VGS values. The device exhibits typical ptype characteristics with on/off ratios over 103 for VGS ranging from )30 to 30 V. It can be observed that these devices are off for zero-applied VGS voltages. This is an important advantage to be considered for low power consumption applications [5].
-30
-20
-10
0
10
20
30
40
VGS (V) Fig. 4. Transfer characteristic of a pentacene TFT fabricated on PMMA-coated crystalline silicon. The inset shows the output characteristic of the same device measured at different VGS voltages.
The field-effect mobility (l) and threshold voltage (VT ) of the TFT can be calculated from a linear fit to the saturation characteristic (Fig. 5), i.e., the square root of ID as a function of VDS in the saturation regime (VGS ¼ VDS ). The values obtained at room temperature are l ¼ 0:01 cm2 V1 s1 and VT ¼ 14 V. The temperature dependence of l can be obtained by fitting the saturation characteristics measured at different temperatures. A simple Arrhenius behavior with an activation energy of 90 meV was observed (inset of Fig. 5). This result will be discussed in Section 4. Devices with the same structure on flexible PEN substrates also showed satisfactory output and transfer characteristics. Nevertheless, in that case l was
620
J. Puigdollers et al. / Journal of Non-Crystalline Solids 338–340 (2004) 617–621 0.5
-1
µ (cm V s )
0.02
ID ( µA
1/2
)
2
-1
0.4
0.3
0.01 2.8
0.1
3.0
3.2
3.4
1000/T (K-1)
0.2
T = 300 - 360 K
VDS =V GS 0.0 -40
-30
-20
-10
0
VDS (V) Fig. 5. Saturation characteristic of a pentacene TFT measured at temperatures ranging from 300 to 360 K. The inset is an Arrhenius plot of the field-effect mobility.
significantly reduced to 103 cm2 V1 s1 , probably because of the natural roughness of PEN substrates. On the other hand, VT was around zero-applied voltage. 4. Discussion These previous results seem to indicate that, besides the deposition conditions, the growth process of pentacene is also affected by the base layer. It has been reported that the properties of the surface onto which pentacene is grown influence the quality of the material. In this sense, the incorporation of self-assembling monolayers (SAM) leads to highly ordered pentacene films [2]. As shown in Section 3.1, the XRD peaks of pentacene films on PMMA are slightly shifted towards lower diffraction angles compared to films on silicon for dioxide. The lattice spacings of 15.29 and 14.30 A phase 1 and 2 correspond to a tilt of the molecules of 17.2 and 26.7 to the surface normal. In this calculation it is assumed a triclinic single crystal structure and [3]. In the a length of the pentacene molecule of 16.01 A case of pentacene films on silicon dioxide, tilt angles of 20.7 and 29.2 were obtained for phase 1 and 2, respectively. These results seem to indicate that pentacene molecules prefer to grow more vertically on the PMMA surface. Similar results have been reported with the use of octadecyltrichlorosilane (OTS), which is one of the most widely studied SAM for pentacene films [2]. Actually, like OTS, PMMA has the methyl ending groups (–CH3 ) which promote the growth of highly ordered pentacene layers [6]. It could be concluded that the use of PMMA as a gate dielectric layer in pentacene
TFTs yields several advantages (a) it can be easily deposited over large areas by spin coating, (b) its low baking temperature allows the use of plastic substrates, and finally (c) the methyl ending groups improve the pentacene ordering like a SAM does. The thermal dependence of the field-effect mobility shows an activated behavior that has been attributed to hole trapping near the valence band edge [7]. A band tail of trap states is usually observed in amorphous and polycrystalline materials due to their inherent structural disorder. The presence of an Urbach’s front in the photothermal deflection spectra also indicates an exponential band tail in pentacene thin-films [8]. The relatively high activation energy of the field-effect mobility (90 meV) compared to the published data (<50 meV) [9] could be due to a broader band tail. Actually, in our case neither the growth rate nor the substrate temperature have been optimized to improve the quality of the films. This could also explain the low field-effect mobilities that have been measured. Additional research is in progress to improve the pentacene TFTs performance by tailoring the deposition conditions. 5. Conclusions Pentacene TFTs with good electrical characteristics were fabricated using PMMA as a gate dielectric layer. This polymeric insulator with low baking temperature (170 C) can be spin cast on inexpensive substrates. Moreover, the particular surface of PMMA seems to enhance the crystallinity of pentacene films. The effect on the ordering of pentacene molecules could be similar to that of SAMs. Thus, PMMA arises as a very promising candidate for replacing inorganic dielectrics hardly compatible with flexible substrates in pentacene TFTs. The deposition conditions of pentacene films should be optimized to guess the actual possibilities of PMMA as a dielectric layer. The state of the art pentacene TFTs are s1 ) and modobtained at low deposition rates (<1 A erate substrate temperatures (<100 C). In the near future we will investigate this range of deposition conditions expecting a certain improvement of the fieldeffect mobility value. Acknowledgements This work has been supported by the CICYT of the Spanish Government under Programme MAT200204263 and by the PICS2002-4 Program of the Generalitat de Catalunya. References [1] J.M. Shaw, P.F. Seidler, IBM J. Res. Dev. 45 (2001) 3. [2] D.J. Gundlach, Y.Y. Lin, T.N. Jackson, IEEE Electron Dev. Lett. 18 (1997) 87.
J. Puigdollers et al. / Journal of Non-Crystalline Solids 338–340 (2004) 617–621 [3] C.D. Dimitrakopoulos, A.R. Brown, A. Pomp, J. Appl. Phys. 80 (1996) 2501. [4] I.P.M. Bouchoms, W.A. Schoonveld, J. Vrijmoeth, T.M. Klapwijk, Synth. Met. 104 (1999) 175. [5] H. Klauk, D.J. Gundlach, J.A. Nichols, C.D. Sheraw, M. Bonse, T.N. Jackson, Solid State Technol. 43 (2000) 63. [6] S.H. Jin, J.S. Yu, J.W. Kim, C.A. Lee, B.G. Park, J.D. Lee, J.H. Lee, Society for Information Display International Symposium,
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Seminar and Exhibition (SID 2003), 18–23 May 2003, Baltimore, MD, USA. [7] R.A. Street, D. Knipp, R. V€ olkel, Appl. Phys. Lett. 80 (9) (2002) 1658. [8] J. Puigdollers, C. Voz, A. Orpella, I. Martin, M. Vetter, R. Alcubilla, Thin Solid Films 427 (2003) 367. [9] D. Knipp, R.A. Street, A. V€ olkel, App. Phys. Lett. 82 (22) (2003) 3907.