- Email: [email protected]
Electrical characterization of MOS memory devices containing metallic nanoparticles and a high-k control oxide layer
Surface Science 601 (2007) 2859–2863 www.elsevier.com/locate/susc
Electrical characterization of MOS memory devices containing metallic nanoparticles and a high-k control oxide layer Ch. Sargentis a
a,*
, K. Giannakopoulos b, A. Travlos b, D. Tsamakis
a
Department of Electrical and Computer Engineering, National Technical University of Athens, Iroon Polytechniou 9, Zografou, 157 73 Athens, Greece b Institute of Materials Science, National Center for Scientific Research ‘Demokritos’, 153 10 Ag, Paraskevi Attikis, Athens, Greece Available online 20 December 2006
Abstract We study the electrical characteristics of a MOS structure in which Pt nanoparticles are embedded. This structure has a tunneling oxide of 3.5 nm in thickness (a SiO2 thermal oxide layer) on top of a Si wafer, and a control oxide of 27 nm (HfO2 layer deposited by electron gun evaporation). The nanoparticles are deposited on the SiO2 layer with electron gun evaporation, at room temperature. The electrical study of the structures demonstrates that the ‘‘write’’ process is initiated at low electric fields. This indicates that this type of memory structure can be very promising for the fabrication of high speed MOSFET memory devices with low power consumption. Our charge retention measurements also show promising results. Ó 2006 Elsevier B.V. All rights reserved. Keywords: Nanocrystal memory; Metal nanoparticles; Metallic nanoparticles; Retention time; Nonvolatile memory; C–V; Discharge mechanism; Floating gate memory
1. Introduction Floating gate memory devices, which contain Si or Ge nanoparticles have already attracted the researchers’ attention for some time [1–3], because in this way it is expected that one can obtain longer retention times in comparison to those obtained with the use of conventional floating gate memory devices. In such memories each nanoparticle is electrically isolated from the rest, so that when there is a charge leakage towards the substrate, this will involve only one or a few nanoparticles, and not the whole floating gate. Additionally, these memories, due to the fact that they operate with a smaller number of carriers, have a lower power consumption, very fast write–erase operation speed, very high density of cells and increased reliability. During the last years [4–6] floating gate memories which contain metallic nanoparticles are under study. These
*
Corresponding author. E-mail address: [email protected] (Ch. Sargentis).
0039-6028/$ - see front matter Ó 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.susc.2006.11.064
memories have some advantages in comparison to the memories that contain semiconductor nanoparticles [4]. Firstly they are more immune to the Fermi level fluctuations caused by contamination, due to the fact that metals have a higher density of states around the Fermi level than semiconductors. Secondly, with the use of metallic nanoparticles it is easier to create an asymmetric barrier between the nanoparticles and the tunneling oxide and so it is easier to perform the ‘‘write’’ operation without sacrificing the length of the retention time. Another fact that eases the control of properties of memories with embedded metallic nanoparticles, is that bulk metals and their respective nanoparticles have very similar energy band diagrams; semiconductor nanoparticles have a dissimilar energy band diagram when compared to their respective bulk materials, as for example, their energy gap varies. In this work, we study the electrical properties of fabricated MOS capacitors with embedded platinum (Pt) nanoparticles. Nanoparticles with high density are deposited on thermally grown SiO2 layer, at room temperature, using electron beam evaporation in high vacuum conditions.
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Ch. Sargentis et al. / Surface Science 601 (2007) 2859–2863
Initially a 3.5 nm SiO2 layer is thermally grown on nSi(1 0 0) wafers ðq ¼ 1 10 X cmÞ; then, using the LOCOS process (local oxidation of silicon) we isolated areas of the wafer in order to define capacitors with areas of 75; 000 lm2 and 10; 000 lm2 . The nanoparticle deposition step was then performed with the use of an electron gun evaporator system, at room temperature, during which 0.6 nm of Pt (nominal thickness) was deposited. Immediately after we proceeded with the evaporation of an HfO2 control oxide layer at 200 °C with thickness equal to 27 nm; this process is described in more detail in [7]. Then, we evaporated an Al layer (several hundreds of nanometers in thickness) and we defined the plates of the capacitors using standard lithography. We then annealed our samples in forming gas (10% H2) at 200 °C, for 1 h. We also fabricated an identical reference sample omitting only the Pt nanoparticle deposition step. With the electrical characterization performed we demonstrate that the ‘‘write–erase’’ process initiates at a small electric field; we study the mechanism involved. Then, we comment on the retention time data from the fabricated devices. 2. Results and discussion In Fig. 1a, we see a cross-section image of the fabricated structure. We observe that the Pt nanoparticles lie indeed on the SiO2/HfO2 interface; the process leaves the SiO2 tunneling layer unaffected. In Fig. 1b, we see the plan-view image of Pt nanoparticles. They have a diameter of about 4.9 nm and a sheet density of 3:2 1012 nanoparticles/ cm2. They are formed solely during the Pt deposition step mentioned above, in RT and without any annealing, in contrast to similar work [4–6]; the mechanism of formation
Fig. 1b. Plan-view image of Pt nanoparticles embedded in the HfO2/SiO2 interface. The nanoparticles are situated on top of the SiO2 layer.
of our metallic nanoparticles on amorphous materials are clearly of the Volmer–Weber type. In Fig. 2, we see the high frequency (1 Mhz) capacitance-voltage characteristics of the fabricated devices. These measurements were performed from inversion (negative applied voltages to the gate) to accumulation (positive applied voltages to the gate) and back, in order to study any possible hysteresis effects. We observe a clear hysteresis effect, that is attributed to the storage of charges in the nanoparticles. When we apply a negative voltage at the gate, holes are tunneling from the substrate to the nanoparticles. This causes a shift in the C–V curves towards negative voltages. When we apply a positive voltage at the gate, electrons from the substrate are tunneling to the nanoparticles. This causes a shift in the C–V curves towards positive voltages.
1.0 0.8
C/C ox
0.6 0.4 0.2 0.0 -5
-4
-3
-2
-1
0
1
2
3
4
5
Vgate [V]
Fig. 1a. Cross-sectional image of Pt nanoparticles on SiO2, obtained after the deposition of 0.6 nm of Pt (nominal thickness).
Fig. 2. High frequency C–V curves of the MOS device obtained after the deposition of Pt with nominal thickness equal to 0.6 nm. The Pt nanoparticles are embedded in the HfO2/SiO2 interface. V gate ¼ ð2Þ ð2Þ V ðjÞ, ð3Þ ðþ3Þ V ð Þ, ð4Þ ðþ4Þ V.
Ch. Sargentis et al. / Surface Science 601 (2007) 2859–2863
We have calculated (see Fig. 3), the flat band shift ðDV FB Þ – memory window – versus the electric field in the thin tunneling oxide layer. We have calculated this field using the well known formula: Etunnel-oxide ¼
V tunnel-oxide d tunnel-oxide
ð1Þ
where d tunnel-oxide is the thickness of SiO2 tunneling oxide film and V tunnel-oxide is the voltage drop across the tunneling oxide layer. We calculate the V tunnel-oxide and the V control-oxide considering that the tunneling oxide layer (SiO2) and the control oxide layer (HfO2) form two capacitors in series. After some simple calculations we find that: V tunnel-oxide ¼
k HfO2 d SiO2 V gate 4d HfO2 þ k HfO2 d SiO2
ð2Þ
4d HfO2 V gate 4d HfO2 þ k HfO2 d SiO2
ð3Þ
and V control-oxide ¼
where ðdÞ is the thickness of the HfO2 or the SiO2 layer and k HfO2 is the dielectric constant of the HfO2 layer; this constant is calculated from the accumulation region of the C–V measurements ðk HfO2 25Þ. In Figs. 2 and 3, we observe that we obtain a flat band voltage shift of +0.257 V for an applied gate voltage equal to +2 V. The electric field in the tunneling oxide ðEtunnel-oxide Þ is equal to 2.4 MV/cm and the average electric V
gate field E¼ d total-oxide is equal to 0.65 MV/cm. For comparison,
one can find that in Ref. [8] for a MOS memory device witch contains SiGe nanoparticles there is DV FB ¼ 0:35 V for average electric field E ¼ 1:25 MV=cm. Also, in Ref. [5] the obtained DV FB is 1.7 V for average electric field E ¼ 2:35 MV=cm. As we can see in Fig. 3 we obtain almost the same flat band shift for E ¼ 1:3 MV=cm ðEtunnel-oxide ¼ 4:8 MV=cmÞ. We note that the nanoparticle density in our case is one order of magnitude higher than in Ref. [5,8]. It is known that the Coulomb blockade effect limits the operation of memory devices, at low voltages. As this phenomenon has lower intensity in metallic nanoparticles than
2861
in semiconductor nanoparticles (for particles with the same size), it means that such devices can operate at lower electric fields. From Eqs. (2) and (3) we obtain: V control-oxide k SiO2 d HfO2 ¼ ¼ 1:23 V tunnel-oxide k HfO2 d SiO2
ð4Þ
as calculated from the data mentioned above. We note here that the use of high-k dielectric for the control oxide tends to reduce the voltage drop across it in comparison to the tunnel oxide voltage drop. In our case the voltage drop across the control oxide is slightly bigger than the drop in the tunneling oxide, due to the fact that this layer is much thicker than the tunneling oxide layer. As the control oxide is much thicker than the tunneling oxide, the electric field in the control oxide is much smaller than in the tunneling oxide. These observations indicate that our MOS memory structures with thin tunneling oxide can initiate the write–erase process at low electric fields, which in turn indicate that low power consumption MOSFET memory devices with Pt nanoparticles can be produced. Therefore such memory devices can be promising candidates for use in portable electronics, such as computers, and digital cameras. In Fig. 4, we present the high frequency capacitance– voltage characteristics of the reference sample (i.e. the same structure without any nanoparticles). The flat band shift in this sample is DV FB ¼ 0:3 V for Etunnel-oxide ¼ 4:8 MV=cm (much lower than in the reference [5]) and is not affected by the application of different gate voltages. This indicates that in the reference sample exist negative traps, located in the interface between the tunneling and the control oxide, or inside the control oxide, that block the symmetric DV FB shift towards both the positive and the negative direction (Fig. 2). In Fig. 5, we present the leakage current density versus the electric field across the tunnel oxide layer, in the accumulation region. This data are in accordance with the literature [9]. The main tunneling mechanism for the write process that takes place is direct tunneling. This mechanism
2.0 1.0
1.8 1.6
0.8
V
1.2
C/Cox
FB
[V]
1.4 1.0 0.8 0.6
0.6 0.4 0.2
0.4 0.0
0.2 2.0
2.5
3.0
3.5
E tunnel-oxide
4.0
4.5
5.0
(MV/cm)
Fig. 3. Flat band shift ðDV FB Þ versus the electric field across the tunneling oxide layer in the fabricated MOS structures.
-4
-2
0
2
4
Vgate [V]
Fig. 4. High frequency C–V curves of the reference sample (without nanoparticles).
2862
Ch. Sargentis et al. / Surface Science 601 (2007) 2859–2863 1.5 initial
)*100/C
2
(x10 (A/cm )
%
50
20
-C
final
30
10
(C
initial
0.5
J
forward
-6
1.0
40
0 0.0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
10
4.0
E tuunel-oxide (MV/cm)
Fig. 5. Leakage current density versus electric field across the tunneling oxide layer (SiO2) for the fabricated devices, for positive applied gate voltages.
is effective for programming memory devices with SiO2 tunneling dielectric film thickness lower than about 4 nm [10]. The current density is very sensitive on the thickness of the dielectric layer. In Fig. 6 we present a schematic band diagram of the fabricated device for an applied gate voltage of +3 V. In this figure, 1.34 V and 1.66 V is the voltage across the tunneling oxide and the control oxide respectively, calculated using relations Eqs. (2) and (3). The electrons tunnel from the Si substrate through the thin SiO2 barrier with trapezoid shape and are stored into the Pt nanoparticles or in the interface states located in Pt nanoparticles/dielectric layer. In Fig. 7, we present the charge retention characteristics of our memory structure at room temperature. Initially we have applied a gate voltage of +3 V for 20 s in order to charge the nanoparticles with electrons. Then, we measured the value of the capacitance as a function of time, near the flat band voltage. As we observe, the retention time of our structure is more than 1323 s; the retention time is defined as the time for the normalized capacitance to increase by 50% of its initial value (Cinitial). We notice that this retention time is much longer than the retention times that are reported in [11], 148 s and 300 s, in devices that contain Ge nanoparticles and tunneling oxides with EOT (equivalent oxide thickness) of 5 nm (for SiO2 and HfO2 tunneling
100
1000
Time (s) Fig. 7. Charge retention characteristics of MOS capacitors with embedded Pt nanoparticles at room temperature for the storage of electrons.
oxides respectively). In Fig. 7, we observe that the discharge curve can be divided in two regions: the first region (for short times) is characterized from fast discharge effects and a second region (for longer times) that is characterized by slow discharge effects. In the first region, we have fast discharge effects because initially the electric field in the tunneling oxide is very high due to the fact that the amount of charges in the nanoparticles is high. With the evolution of the discharge the electric field is decreased as well as the tunneling probability [12]. The second region we believe that originates by electrons which are stored in the Pt nanoparticles and tunnel to the Si wafer by direct tunneling. This is indicated by the fact that our curve is well fitted by the logarithmic relation [12,8]: jDCj ¼ a log t þ b C initial
ð5Þ
where a, b are constants. In conclusion, we have demonstrated that MOS capacitors embedded with Pt nanoparticles, fabricated at room temperature without any annealing, present memory effects. These memory effects are initiated at low electric fields. This structure is very promising for use in high speed, low power consumption memories. The write process is a direct type tunneling mechanism. The fabricated structure presents good retention characteristics. Acknowledgements This work has been supported under the Greek Program ‘‘Heraklitos’’ of the Ministry of Education and Religious Affairs. K.G. acknowledge for the help of the Program ‘‘ENTER 2004’’, of the General Secretariat for Research and Technology.
1.34 V
1.66 V
References Al gate (+3 V)
HfO2
nc-Pt
SiO 2
n-Si
Fig. 6. Band diagram of n-Si/SiO2 tunneling layer/Pt nanoparticles/HfO2 control oxide/Al (gate), MOS structure for applied gate voltage of +3 V.
[1] S. Tiwari, F. Rhana, K. Chan, L. Shi, H. Hanafi, Appl. Phys. Lett. 69 (1996) 1232. [2] S. Tiwari, J.A. Wahl, H. Silva, F. Rana, J.J. Welser, Appl. Phys. A 71 (2000) 403.
Ch. Sargentis et al. / Surface Science 601 (2007) 2859–2863 [3] Y. Shi, K. Saito, H. Ishikuro, T. Hiramoto, Jpn. Appl. Phys. 38 (1999) 425. [4] Z. Liu, C. Lee, V. Narayanan, G. Pei, E.C. Kan, IEEE Trans. El. Dev. 49 (9) (2002) 1606. [5] Z. Tan, S.K. Samanta, W.J. Yoo, S. Lee, Appl. Phys. Lett. 86 (2005) 013107. [6] Q. Wang, Z.T. Song, W.L. Liu, C.L. Lin, T.H. Wang, Appl. Surf. Sci. 230 (2004) 8. [7] Ch. Sargentis, K. Giannakopoulos, A. Travlos, N. Boukos, D. Tsamakis, Appl. Phys. Lett. 88 (2006) 073106.
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[8] D.W. Kim, F.E. Prins, T. Kim, S. Hwang, C.H. Lee, D.L. Kwong, S.K. Banerjee, IEEE Trans. El. Dev. 50 (2) (2003) 510. [9] H.-J. Thees, M. Wittmaack, K.-H. Stegemann, J.v. Borany, K.-H. Heinig, T. Gebel, Microelectron. Reliab. 40 (2000) 867. [10] B. De Salvo, G. Ghibaudo, P. Luthereau, T. Baron, B. Guilaumot, G. Reimbold, Solid-state Electron. 45 (2001) 1513. [11] T.H. Ng, V. Ho, L.W. Teo, M.S. Tay, B.H. Koh, W.K. Chim, W.K. Choi, A.Y. Du, C.H. Tung, Thin Solid Films 462–463 (2004) 46. [12] C. Busseret, A. Souifi, T. Baron, G. Guillot, F. Martin, M.N. Semeria, J. Gautier, Superlattice Microst. 28 (5–6) (2000) 493.
Electrical characterization of MOS memory devices containing metallic nanoparticles and a high-k control oxide layer Ch. Sargentis a
a,*
, K. Giannakopoulos b, A. Travlos b, D. Tsamakis
a
Department of Electrical and Computer Engineering, National Technical University of Athens, Iroon Polytechniou 9, Zografou, 157 73 Athens, Greece b Institute of Materials Science, National Center for Scientific Research ‘Demokritos’, 153 10 Ag, Paraskevi Attikis, Athens, Greece Available online 20 December 2006
Abstract We study the electrical characteristics of a MOS structure in which Pt nanoparticles are embedded. This structure has a tunneling oxide of 3.5 nm in thickness (a SiO2 thermal oxide layer) on top of a Si wafer, and a control oxide of 27 nm (HfO2 layer deposited by electron gun evaporation). The nanoparticles are deposited on the SiO2 layer with electron gun evaporation, at room temperature. The electrical study of the structures demonstrates that the ‘‘write’’ process is initiated at low electric fields. This indicates that this type of memory structure can be very promising for the fabrication of high speed MOSFET memory devices with low power consumption. Our charge retention measurements also show promising results. Ó 2006 Elsevier B.V. All rights reserved. Keywords: Nanocrystal memory; Metal nanoparticles; Metallic nanoparticles; Retention time; Nonvolatile memory; C–V; Discharge mechanism; Floating gate memory
1. Introduction Floating gate memory devices, which contain Si or Ge nanoparticles have already attracted the researchers’ attention for some time [1–3], because in this way it is expected that one can obtain longer retention times in comparison to those obtained with the use of conventional floating gate memory devices. In such memories each nanoparticle is electrically isolated from the rest, so that when there is a charge leakage towards the substrate, this will involve only one or a few nanoparticles, and not the whole floating gate. Additionally, these memories, due to the fact that they operate with a smaller number of carriers, have a lower power consumption, very fast write–erase operation speed, very high density of cells and increased reliability. During the last years [4–6] floating gate memories which contain metallic nanoparticles are under study. These
*
Corresponding author. E-mail address: [email protected] (Ch. Sargentis).
0039-6028/$ - see front matter Ó 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.susc.2006.11.064
memories have some advantages in comparison to the memories that contain semiconductor nanoparticles [4]. Firstly they are more immune to the Fermi level fluctuations caused by contamination, due to the fact that metals have a higher density of states around the Fermi level than semiconductors. Secondly, with the use of metallic nanoparticles it is easier to create an asymmetric barrier between the nanoparticles and the tunneling oxide and so it is easier to perform the ‘‘write’’ operation without sacrificing the length of the retention time. Another fact that eases the control of properties of memories with embedded metallic nanoparticles, is that bulk metals and their respective nanoparticles have very similar energy band diagrams; semiconductor nanoparticles have a dissimilar energy band diagram when compared to their respective bulk materials, as for example, their energy gap varies. In this work, we study the electrical properties of fabricated MOS capacitors with embedded platinum (Pt) nanoparticles. Nanoparticles with high density are deposited on thermally grown SiO2 layer, at room temperature, using electron beam evaporation in high vacuum conditions.
2860
Ch. Sargentis et al. / Surface Science 601 (2007) 2859–2863
Initially a 3.5 nm SiO2 layer is thermally grown on nSi(1 0 0) wafers ðq ¼ 1 10 X cmÞ; then, using the LOCOS process (local oxidation of silicon) we isolated areas of the wafer in order to define capacitors with areas of 75; 000 lm2 and 10; 000 lm2 . The nanoparticle deposition step was then performed with the use of an electron gun evaporator system, at room temperature, during which 0.6 nm of Pt (nominal thickness) was deposited. Immediately after we proceeded with the evaporation of an HfO2 control oxide layer at 200 °C with thickness equal to 27 nm; this process is described in more detail in [7]. Then, we evaporated an Al layer (several hundreds of nanometers in thickness) and we defined the plates of the capacitors using standard lithography. We then annealed our samples in forming gas (10% H2) at 200 °C, for 1 h. We also fabricated an identical reference sample omitting only the Pt nanoparticle deposition step. With the electrical characterization performed we demonstrate that the ‘‘write–erase’’ process initiates at a small electric field; we study the mechanism involved. Then, we comment on the retention time data from the fabricated devices. 2. Results and discussion In Fig. 1a, we see a cross-section image of the fabricated structure. We observe that the Pt nanoparticles lie indeed on the SiO2/HfO2 interface; the process leaves the SiO2 tunneling layer unaffected. In Fig. 1b, we see the plan-view image of Pt nanoparticles. They have a diameter of about 4.9 nm and a sheet density of 3:2 1012 nanoparticles/ cm2. They are formed solely during the Pt deposition step mentioned above, in RT and without any annealing, in contrast to similar work [4–6]; the mechanism of formation
Fig. 1b. Plan-view image of Pt nanoparticles embedded in the HfO2/SiO2 interface. The nanoparticles are situated on top of the SiO2 layer.
of our metallic nanoparticles on amorphous materials are clearly of the Volmer–Weber type. In Fig. 2, we see the high frequency (1 Mhz) capacitance-voltage characteristics of the fabricated devices. These measurements were performed from inversion (negative applied voltages to the gate) to accumulation (positive applied voltages to the gate) and back, in order to study any possible hysteresis effects. We observe a clear hysteresis effect, that is attributed to the storage of charges in the nanoparticles. When we apply a negative voltage at the gate, holes are tunneling from the substrate to the nanoparticles. This causes a shift in the C–V curves towards negative voltages. When we apply a positive voltage at the gate, electrons from the substrate are tunneling to the nanoparticles. This causes a shift in the C–V curves towards positive voltages.
1.0 0.8
C/C ox
0.6 0.4 0.2 0.0 -5
-4
-3
-2
-1
0
1
2
3
4
5
Vgate [V]
Fig. 1a. Cross-sectional image of Pt nanoparticles on SiO2, obtained after the deposition of 0.6 nm of Pt (nominal thickness).
Fig. 2. High frequency C–V curves of the MOS device obtained after the deposition of Pt with nominal thickness equal to 0.6 nm. The Pt nanoparticles are embedded in the HfO2/SiO2 interface. V gate ¼ ð2Þ ð2Þ V ðjÞ, ð3Þ ðþ3Þ V ð Þ, ð4Þ ðþ4Þ V.
Ch. Sargentis et al. / Surface Science 601 (2007) 2859–2863
We have calculated (see Fig. 3), the flat band shift ðDV FB Þ – memory window – versus the electric field in the thin tunneling oxide layer. We have calculated this field using the well known formula: Etunnel-oxide ¼
V tunnel-oxide d tunnel-oxide
ð1Þ
where d tunnel-oxide is the thickness of SiO2 tunneling oxide film and V tunnel-oxide is the voltage drop across the tunneling oxide layer. We calculate the V tunnel-oxide and the V control-oxide considering that the tunneling oxide layer (SiO2) and the control oxide layer (HfO2) form two capacitors in series. After some simple calculations we find that: V tunnel-oxide ¼
k HfO2 d SiO2 V gate 4d HfO2 þ k HfO2 d SiO2
ð2Þ
4d HfO2 V gate 4d HfO2 þ k HfO2 d SiO2
ð3Þ
and V control-oxide ¼
where ðdÞ is the thickness of the HfO2 or the SiO2 layer and k HfO2 is the dielectric constant of the HfO2 layer; this constant is calculated from the accumulation region of the C–V measurements ðk HfO2 25Þ. In Figs. 2 and 3, we observe that we obtain a flat band voltage shift of +0.257 V for an applied gate voltage equal to +2 V. The electric field in the tunneling oxide ðEtunnel-oxide Þ is equal to 2.4 MV/cm and the average electric V
gate field E¼ d total-oxide is equal to 0.65 MV/cm. For comparison,
one can find that in Ref. [8] for a MOS memory device witch contains SiGe nanoparticles there is DV FB ¼ 0:35 V for average electric field E ¼ 1:25 MV=cm. Also, in Ref. [5] the obtained DV FB is 1.7 V for average electric field E ¼ 2:35 MV=cm. As we can see in Fig. 3 we obtain almost the same flat band shift for E ¼ 1:3 MV=cm ðEtunnel-oxide ¼ 4:8 MV=cmÞ. We note that the nanoparticle density in our case is one order of magnitude higher than in Ref. [5,8]. It is known that the Coulomb blockade effect limits the operation of memory devices, at low voltages. As this phenomenon has lower intensity in metallic nanoparticles than
2861
in semiconductor nanoparticles (for particles with the same size), it means that such devices can operate at lower electric fields. From Eqs. (2) and (3) we obtain: V control-oxide k SiO2 d HfO2 ¼ ¼ 1:23 V tunnel-oxide k HfO2 d SiO2
ð4Þ
as calculated from the data mentioned above. We note here that the use of high-k dielectric for the control oxide tends to reduce the voltage drop across it in comparison to the tunnel oxide voltage drop. In our case the voltage drop across the control oxide is slightly bigger than the drop in the tunneling oxide, due to the fact that this layer is much thicker than the tunneling oxide layer. As the control oxide is much thicker than the tunneling oxide, the electric field in the control oxide is much smaller than in the tunneling oxide. These observations indicate that our MOS memory structures with thin tunneling oxide can initiate the write–erase process at low electric fields, which in turn indicate that low power consumption MOSFET memory devices with Pt nanoparticles can be produced. Therefore such memory devices can be promising candidates for use in portable electronics, such as computers, and digital cameras. In Fig. 4, we present the high frequency capacitance– voltage characteristics of the reference sample (i.e. the same structure without any nanoparticles). The flat band shift in this sample is DV FB ¼ 0:3 V for Etunnel-oxide ¼ 4:8 MV=cm (much lower than in the reference [5]) and is not affected by the application of different gate voltages. This indicates that in the reference sample exist negative traps, located in the interface between the tunneling and the control oxide, or inside the control oxide, that block the symmetric DV FB shift towards both the positive and the negative direction (Fig. 2). In Fig. 5, we present the leakage current density versus the electric field across the tunnel oxide layer, in the accumulation region. This data are in accordance with the literature [9]. The main tunneling mechanism for the write process that takes place is direct tunneling. This mechanism
2.0 1.0
1.8 1.6
0.8
V
1.2
C/Cox
FB
[V]
1.4 1.0 0.8 0.6
0.6 0.4 0.2
0.4 0.0
0.2 2.0
2.5
3.0
3.5
E tunnel-oxide
4.0
4.5
5.0
(MV/cm)
Fig. 3. Flat band shift ðDV FB Þ versus the electric field across the tunneling oxide layer in the fabricated MOS structures.
-4
-2
0
2
4
Vgate [V]
Fig. 4. High frequency C–V curves of the reference sample (without nanoparticles).
2862
Ch. Sargentis et al. / Surface Science 601 (2007) 2859–2863 1.5 initial
)*100/C
2
(x10 (A/cm )
%
50
20
-C
final
30
10
(C
initial
0.5
J
forward
-6
1.0
40
0 0.0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
10
4.0
E tuunel-oxide (MV/cm)
Fig. 5. Leakage current density versus electric field across the tunneling oxide layer (SiO2) for the fabricated devices, for positive applied gate voltages.
is effective for programming memory devices with SiO2 tunneling dielectric film thickness lower than about 4 nm [10]. The current density is very sensitive on the thickness of the dielectric layer. In Fig. 6 we present a schematic band diagram of the fabricated device for an applied gate voltage of +3 V. In this figure, 1.34 V and 1.66 V is the voltage across the tunneling oxide and the control oxide respectively, calculated using relations Eqs. (2) and (3). The electrons tunnel from the Si substrate through the thin SiO2 barrier with trapezoid shape and are stored into the Pt nanoparticles or in the interface states located in Pt nanoparticles/dielectric layer. In Fig. 7, we present the charge retention characteristics of our memory structure at room temperature. Initially we have applied a gate voltage of +3 V for 20 s in order to charge the nanoparticles with electrons. Then, we measured the value of the capacitance as a function of time, near the flat band voltage. As we observe, the retention time of our structure is more than 1323 s; the retention time is defined as the time for the normalized capacitance to increase by 50% of its initial value (Cinitial). We notice that this retention time is much longer than the retention times that are reported in [11], 148 s and 300 s, in devices that contain Ge nanoparticles and tunneling oxides with EOT (equivalent oxide thickness) of 5 nm (for SiO2 and HfO2 tunneling
100
1000
Time (s) Fig. 7. Charge retention characteristics of MOS capacitors with embedded Pt nanoparticles at room temperature for the storage of electrons.
oxides respectively). In Fig. 7, we observe that the discharge curve can be divided in two regions: the first region (for short times) is characterized from fast discharge effects and a second region (for longer times) that is characterized by slow discharge effects. In the first region, we have fast discharge effects because initially the electric field in the tunneling oxide is very high due to the fact that the amount of charges in the nanoparticles is high. With the evolution of the discharge the electric field is decreased as well as the tunneling probability [12]. The second region we believe that originates by electrons which are stored in the Pt nanoparticles and tunnel to the Si wafer by direct tunneling. This is indicated by the fact that our curve is well fitted by the logarithmic relation [12,8]: jDCj ¼ a log t þ b C initial
ð5Þ
where a, b are constants. In conclusion, we have demonstrated that MOS capacitors embedded with Pt nanoparticles, fabricated at room temperature without any annealing, present memory effects. These memory effects are initiated at low electric fields. This structure is very promising for use in high speed, low power consumption memories. The write process is a direct type tunneling mechanism. The fabricated structure presents good retention characteristics. Acknowledgements This work has been supported under the Greek Program ‘‘Heraklitos’’ of the Ministry of Education and Religious Affairs. K.G. acknowledge for the help of the Program ‘‘ENTER 2004’’, of the General Secretariat for Research and Technology.
1.34 V
1.66 V
References Al gate (+3 V)
HfO2
nc-Pt
SiO 2
n-Si
Fig. 6. Band diagram of n-Si/SiO2 tunneling layer/Pt nanoparticles/HfO2 control oxide/Al (gate), MOS structure for applied gate voltage of +3 V.
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