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Electron beam writes next-generation IC patterns
World Abstracts continued from page 75 precious metal-based materials. These differences are primarily related to the ease of oxidation of the solder alloy powders. The relationship between solder flux chemistry and the reactivity of solder powders is described in terms of functional performance.
2.
Production and Processing
Computer-aided design of VLSI circuits A R T H U R RICHARD NEWTON Proc. IEEE69 (I0), 1189 (October 1981) With the rapid evolution of integrated circuit (IC) technology to larger and more complex circuits, new approaches are needed for the design and verification of these very-large-scale integrated (VLSI) circuits. A large number of design methods are currently in use. However, the evolution of these computer aids has occurred in an ad hoc manner. In most cases, computer programs have been written to solve specific problems as they have arisen and no truly integrated computer-aided design (CAD) systems exist for the design of ICs. A structured approach both to circuit design and to circuit verification, as well as the development of integrated design systems, is necessary to produce cost-effective error-free VLSI circuits. This paper presents a review of the CAD techniques which have been used in the design of ICs, as well as a number of design methods to which the application of computer aids has proven most successful. The successful application of design-aids to VLSI circuits requires an evolution from these techniques and design methods. Ion implantation gettering; a fundamental approach S. PRUSSIN Solid&ate Technology 52 (July 1981) The use of ion implantation damage as a gettering technique is discussed. The operation has the capability of being easily introduced during the processing sequence. It can be applied to the back surface without protecting the front surface and it can use non-electrically active species which avoid problems of contamination associated with diffusion gettering operations. Concepts of point defect equilibria which are applicable to the understanding ofgettering phenomena are reviewed. Electron-beam projector suits up for submicrometer race RODNEY WARD Electronics 142 (3 Nov 1981 ) Lithography machine can define chip features as small as 0.2 p m ; system throughput can be as high as twenty-five 4 in wafers an hour. Automated parametric testers to monitor the integrated circuit process ULRICH K A E M P F Solid&. TechnoL 81 (Sept 1981) The use of automatic test equipment for the monitoring of critical material properties and in the detection of process deviations is discussed. The application of computer-controlled test sytems for electrical circuit testing of completed wafers is presented. Emphasis is placed on the ease of programming and meaningful presentation of the test data for feedback to the process engineer to enhance product quality and yield. Some of 76
the physical properties of the materials and the electrical circuits that need to be measured and how these measurements are implemented are also discussed. Examples of devices to be tested and suitable test apparatus are presented. Three unique measurements techniques are examined. Electrostatic discharge failures of semiconductor devices B. A. UNGER IEEE/Proc. IRPS 193 (1981) ESD (Electrostatic Discharge) is a significant cause of device failures at all stages of device and equipment production, assembly, test, installation and field use. Even though device designs include protection circuitry, it is relatively easy to generate static potentials during handling and shipping that exced the limits of the protection networks. Damage from ESDs can cause either complete device failure by parametric shifts, or device weakness by locally heating, melting, or otherwise damaging oxides, junctions or device components. There are three principal sources of charge which can give rise to damaging ESD events. (1) A charged person touches a device and discharges the stored charge to or through the device to ground. (2) The device itself acting as one plate of a capacitor can store charge. Upon contact with an effective ground the discharge pulse can create damage. (3) An electrostatic field is always associated with charged objects. Under particular circumstances, a device inserted in this field can have a potential induced across an oxide that creates breakdown. All devices and technologies are susceptible to damaging ESDs. The difference is in their degree of susceptibility. MOS structures appear to be the most susceptible to ESD damage. The generation of charge varies with materials, environment, and conditions of contact. All materials can be charged, however with conductors the charge is readily dissipated by grounding. With insulators, the charge is immobile and not readily dissipated. Two basic measures for avoiding ESD damage and failures are: (1) Ahvays wear a grounding strap when handling electronic components. (2) For transport, storage or assembly, a static-free environment must be created by selection of materials, shielding and proper grounding. Electron beam writes next-generation IC patterns R. MOORE, G. CACCOMA, H. PFEIFFER, E. WEBER and O. WOODWARD Electronics 138 (3 Nov 1981) Variable spot shaping and subfield vector-writing technlques let beam write from 20 to 45 three-inch wafers per hour. Implanted p-channel MOS transistor threshold voltage dependence on impurity segregation during oxidation ANDRZEJ A. CZERWINKSI and JAN Z. OLENSKI Electron Technology 12 (4), 35 (1979) The influence of phosphorus segregation in the Si-SiO2 interface region during thermal oxidation on p-channel MOS transistor threshold voltage is analysed in the present paper. The case of boron implanation into originally uniformly doped n-type substrate performed after all high temperature processes to tailor the
2.
Production and Processing
Computer-aided design of VLSI circuits A R T H U R RICHARD NEWTON Proc. IEEE69 (I0), 1189 (October 1981) With the rapid evolution of integrated circuit (IC) technology to larger and more complex circuits, new approaches are needed for the design and verification of these very-large-scale integrated (VLSI) circuits. A large number of design methods are currently in use. However, the evolution of these computer aids has occurred in an ad hoc manner. In most cases, computer programs have been written to solve specific problems as they have arisen and no truly integrated computer-aided design (CAD) systems exist for the design of ICs. A structured approach both to circuit design and to circuit verification, as well as the development of integrated design systems, is necessary to produce cost-effective error-free VLSI circuits. This paper presents a review of the CAD techniques which have been used in the design of ICs, as well as a number of design methods to which the application of computer aids has proven most successful. The successful application of design-aids to VLSI circuits requires an evolution from these techniques and design methods. Ion implantation gettering; a fundamental approach S. PRUSSIN Solid&ate Technology 52 (July 1981) The use of ion implantation damage as a gettering technique is discussed. The operation has the capability of being easily introduced during the processing sequence. It can be applied to the back surface without protecting the front surface and it can use non-electrically active species which avoid problems of contamination associated with diffusion gettering operations. Concepts of point defect equilibria which are applicable to the understanding ofgettering phenomena are reviewed. Electron-beam projector suits up for submicrometer race RODNEY WARD Electronics 142 (3 Nov 1981 ) Lithography machine can define chip features as small as 0.2 p m ; system throughput can be as high as twenty-five 4 in wafers an hour. Automated parametric testers to monitor the integrated circuit process ULRICH K A E M P F Solid&. TechnoL 81 (Sept 1981) The use of automatic test equipment for the monitoring of critical material properties and in the detection of process deviations is discussed. The application of computer-controlled test sytems for electrical circuit testing of completed wafers is presented. Emphasis is placed on the ease of programming and meaningful presentation of the test data for feedback to the process engineer to enhance product quality and yield. Some of 76
the physical properties of the materials and the electrical circuits that need to be measured and how these measurements are implemented are also discussed. Examples of devices to be tested and suitable test apparatus are presented. Three unique measurements techniques are examined. Electrostatic discharge failures of semiconductor devices B. A. UNGER IEEE/Proc. IRPS 193 (1981) ESD (Electrostatic Discharge) is a significant cause of device failures at all stages of device and equipment production, assembly, test, installation and field use. Even though device designs include protection circuitry, it is relatively easy to generate static potentials during handling and shipping that exced the limits of the protection networks. Damage from ESDs can cause either complete device failure by parametric shifts, or device weakness by locally heating, melting, or otherwise damaging oxides, junctions or device components. There are three principal sources of charge which can give rise to damaging ESD events. (1) A charged person touches a device and discharges the stored charge to or through the device to ground. (2) The device itself acting as one plate of a capacitor can store charge. Upon contact with an effective ground the discharge pulse can create damage. (3) An electrostatic field is always associated with charged objects. Under particular circumstances, a device inserted in this field can have a potential induced across an oxide that creates breakdown. All devices and technologies are susceptible to damaging ESDs. The difference is in their degree of susceptibility. MOS structures appear to be the most susceptible to ESD damage. The generation of charge varies with materials, environment, and conditions of contact. All materials can be charged, however with conductors the charge is readily dissipated by grounding. With insulators, the charge is immobile and not readily dissipated. Two basic measures for avoiding ESD damage and failures are: (1) Ahvays wear a grounding strap when handling electronic components. (2) For transport, storage or assembly, a static-free environment must be created by selection of materials, shielding and proper grounding. Electron beam writes next-generation IC patterns R. MOORE, G. CACCOMA, H. PFEIFFER, E. WEBER and O. WOODWARD Electronics 138 (3 Nov 1981) Variable spot shaping and subfield vector-writing technlques let beam write from 20 to 45 three-inch wafers per hour. Implanted p-channel MOS transistor threshold voltage dependence on impurity segregation during oxidation ANDRZEJ A. CZERWINKSI and JAN Z. OLENSKI Electron Technology 12 (4), 35 (1979) The influence of phosphorus segregation in the Si-SiO2 interface region during thermal oxidation on p-channel MOS transistor threshold voltage is analysed in the present paper. The case of boron implanation into originally uniformly doped n-type substrate performed after all high temperature processes to tailor the