Experimental characterization of the subthreshold leakage current in triple-gate FinFETs

Solid-State Electronics 53 (2009) 359–363

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Experimental characterization of the subthreshold leakage current in triple-gate FinFETs A. Tsormpatzoglou a,*, C.A. Dimitriadis a, M. Mouis b, G. Ghibaudo b, N. Collaert c a

Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece IMEP, MINATEC, Parvis Louis Néel, 38054 Grenoble Cedex 9, France c IMEC, Kapeldreef 75, 3001 Heverlee, Belgium b

a r t i c l e

i n f o

Article history: Received 29 July 2008 Received in revised form 4 December 2008 Accepted 9 January 2009 Available online 12 February 2009 The review of this paper was arranged by S. Cristoloveanu Keywords: Interface state density FinFET Leakage current Tunneling

a b s t r a c t The gate and subthreshold drain leakage currents are investigated experimentally in triple-gate FinFETs for power supply voltage Vdd = 1 V. The gate and drain leakage currents are analyzed in terms of the fin width and gate length to clarify their origin. In wide FinFETs, the measured subthreshold drain current is much larger than the gate tunneling current due to the short-channel effects. In narrow FinFETs with negligible short-channel effects, the importance of the trap-assisted sidewall-gate edge tunneling current on the drain leakage current has been demonstrated. This leakage current behavior with decreasing the fin width has been attributed to the higher sidewall-gate interface trap density compared to the top-gate interface trap density. Ó 2009 Elsevier Ltd. All rights reserved.

1. Introduction According to the International Technology Roadmap for Semiconductor (ITRS) [1], MOS transistors will have gate lengths of around 10 nm in 2015, enabling the realization of very high performance VLSI circuits. The performance of these transistors is expected to be severely degraded by short-channel effects (SCEs). For sub-100 nm scaling of MOSFETs, triple-gate field-effect transistors like FinFETs have attracted considerable attention due to their immunity to SCEs and proximity to standard bulk planar CMOS processing [2–7]. Since the advanced triple-gate FinFETs require ultra-thin gate dielectrics, gate tunneling currents may affect the drain leakage current in the subthreshold region of operation, leading to a substantial increase of the leakage energy which is harmful for applications in circuits of low power consumption. Recently, in FinFET structures with ultra-thin HfO2 and SiON as gate dielectrics, the gate tunneling current has been investigated experimentally with the source, drain and substrate electrodes grounded [8]. The reported experimental results provide evidence for reduction of the gate tunneling current density in narrow FinFET structures compared to their counterpart quasi-planar structures [8]. However, until the present time there is no experimental work

* Corresponding author. Tel.: +30 2310998212. E-mail address: [email protected] (A. Tsormpatzoglou). 0038-1101/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2009.01.008

on the gate and drain leakage currents in FinFETs with the drain bias set equal to the power supply voltage. In this work, we investigate experimentally the subthreshold behavior of triple-gate FinFETs, with the drain bias set equal to the power supply voltage of Vdd = 1 V and with the source/substrate biases set to zero volts. The leakage current is investigated in terms of the effective gate width and gate length to ascertain if devices of the present technology meet the ITRS requirements for the year 2015. The gate and drain leakage currents are analyzed, showing that the sidewall-gate tunneling current can dominate the off-state current of narrow width devices only and, thus, strongly contribute to the off-state power consumption. The possible explanation for the observed effect is discussed. 2. FinFET structure The n-channel triple-gate FinFETs were fabricated at IMEC (Leuven) on SOI wafers with 145 nm buried oxide thickness, following the process described elsewhere [8]. The structure of the triplegate FinFET is schematically represented in Fig. 1. The channel of the transistors is silicon undoped with background boron doping of 1015 cm 3. As gate insulator, HfO2 was deposited by atomic layer deposition (ALD) with equivalent gate oxide thickness 1.7 nm, whereas 5 nm thick of ALD TiN film was deposited for gate metallization. The dimensions of the devices are defined as following: the distance between gate and the large source/drain pads is

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Fig. 1. (a) Schematic representation of the triple-gate FinFET, (b) top-down view of the device structure.

fs = 0.2 m with doping about 2  1020 cm 3 in the source/drain areas, the spacer width is about 50 nm with doping 5  1019 cm 3, the fin height Hfin is kept constant at 65 nm, the fin width Wfin is varying from 25 to 875 nm and the gate length Lg is varying from 50 to 910 nm. Static I–V measurements were performed at room temperature at wafer level using a SussMicroTec LT probe station and an HP 4155 semiconductor parameter analyzer. 3. Results and discussion The transfer characteristics of FinFETs with fin height Hfin = 65 nm and fin widths Wfin = 25, 55, 125 and 875 nm, mea-

sured at drain voltage Vds = 1.02 V, are shown in Fig. 2. Except the subthreshold leakage current arising from drift–diffusion of carriers from source to drain, an additional large drain leakage current is observed in the low gate voltage region, which increases with decreasing Vgs. Such large drain leakage current, which was observed in MOSFETs with thin gate oxide at drain voltages much below than the usually considered ‘‘breakdown voltage”, is referred as sub-breakdown leakage current caused by band-to-band tunneling in the drain–gate overlap region and it is known as Gate Induced Drain Leakage (GIDL) [9,10]. This leakage current is substantially enhanced with increasing the fin width, deteriorating the off-state current as shown in Fig. 2. For large fin widths (Wfin > 100 nm), it is seen that operational devices can be obtained if Lg > 0.7Wfin due to SCEs. However, for narrower fins (Wfin < 100 nm), operational devices are obtained when Lg > 2Wfin. Thus, in order to achieve operational devices with gate lengths in compliance with the ITRS specifications, optimization work is required for the respective device dimensions. To explore if the investigated devices meet the ITRS requirements for the year 2015, the subthreshold leakage current Isd,leak is studied for power supply voltage Vdd = 1 V. The subthreshold leakage current Isd,leak is defined as the drain current per micron of the device width, with the drain bias set equal to the power supply voltage Vdd = 1 V and with the gate, source and substrate biases set to zero volts. The gate width of the FinFET is defined as W = Wfin + 2Hfin. Fig. 3 shows the experimental Isd,leak versus gate length Lg plots of FinFETs with fin widths Wfin = 25, 55, 125 and 785 nm, along with the ITRS requirements for three types of products: (i) high performance (HP), (ii) low operating power (LOP) and (iii) low standby power (LSTP) technologies in extended planar bulk (PB) and ultra-thin body fully depleted (UTB-FD) SOI MOSFETs. It is clear that with reducing the fin width down to 25 nm, the devices become more suitable to meet the ITRS projections for HP and LOP technologies. However, Fig. 3 also shows that the ITRS requirement for LSTP technology is difficult to be achieved by the present devices. Thus, in order to explore the feasibility for attaining the ITRS requirement for LSTP technology, a comprehensive study of the subthreshold leakage in FinFET structures is required. In nanometer scale devices, the main leakage current components are the subthreshold leakage and the gate tunneling leakage

Fig. 2. Drain current versus gate voltage in n-channel FinFETs with different fin widths Wfin and gate lengths Lg, measured at drain voltage Vds = 1.02 V.

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Fig. 3. Subthreshold leakage current versus gate length in n-channel FinFETs with fin height Hfin = 65 nm and different fin widths Wfin. The leakage current was measured at Vgs = Vds = 1.02 V. The ITRS requirements for different technologies are also shown: ITRS 2001: N Pl HP, . Pl LOP, ITRS 2007: + UTB-FD HP,  Pl HP, d UTBFD LSTP, j Pl LSTP.

which is composed of the direct and edge tunneling currents [11,12]. Fig. 4 shows the experimental gate current Ig as a function of the gate voltage, obtained from FinFETs with Lg = 410 nm at Vds = 1.02 V and Wfin = 25, 55 and 875 nm. In the narrow-fin device with Wfin = 25 nm where the side fin surfaces play significant role, a sharp ‘‘dip” is observed in the measured gate tunneling current, with Ig increasing fast when the gate voltage Vgs is decreased below the threshold voltage Vt, such a gate current behavior has been observed in MOSFETs with ultra-thin gate oxide, explained by the combined effect of gate-to-channel tunneling and drain-to-gate tunneling currents in opposite directions [12]. With increasing the fin width to 55 nm, the observed gate current ‘‘dip” becomes smoother, followed by a significant reduction of the gate current compared to the device with Wfin = 25 nm. For fin width Wfin = 785 nm where the top surface dominates, for Vgs < Vt, the gate current remains invariant with Vgs. For the FinFETs with fin width Wfin = 875 nm and gate lengths Lg = 410, 610 and 910 nm, the gate current is orders of magnitude lower than the drain current in the measured gate bias range as shown in Fig. 5. Thus, in wide-fin FinFETs where the top fin surface is dominant, the gate tunneling current is not contributing to the measured drain leakage current. As shown in Fig. 6a, the drain leakage current increases substantially with decreasing the gate length, implying that the drain leakage current in wide-fin devices is mainly due to SCEs. Since the electric field in the gate-to-drain extension region is proportional to the drain-to-gate voltage Vdg = Vds Vgs, according to the tunneling theory the drain leakage

Fig. 4. Gate current Ig versus gate voltage Vgs in n-channel FinFETs with channel length Lg = 410 nm and different fin widths Wfin, measured at Vds = 1.02 V.

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Fig. 5. Drain current versus gate voltage in n-channel FinFETs with different fin width Wfin = 875 nm and different gate lengths Lg, measured at drain voltage Vds = 1.02 V. For comparison, the corresponding gate current values are also presented.

Fig. 6. (a) Plots of drain leakage current at Vgs = 0 V versus drain voltage Vds in nchannel FinFETs with fin width Wfin = 875 nm and different gate lengths Lg, (b) plots of Ids/Vdg versus 1/Vdg in n-channel FinFETs with fin width Wfin = 25 nm. The voltage Vgs = Vds Vgs and the darin leakage current Ids were extracted from the experimental transfer characteristics for a constant either gate voltage or drain voltage.

current should be the same for the same Vdg, regardless of the different Vds or Vgs values [13]. The linear dependence of log (Ids/Vdg) versus 1/Vdg data in Fig. 6b indicates that the drain leakage current is due to the band-to-band tunneling mechanism. In narrow-fin devices, the effect of the gate tunneling current on the drain current is shown in Fig. 7 for FinFETs with Wfin = 25 nm and gate lengths large enough so that SCEs can be ignored. It is noted that the off-state drain current at Vgs = 0 V is largely determined by the gate tunneling current. We observe also that for Vgs < Vt, the gate current is independent on the gate length, implying that the gate edge tunneling current is dominant on the gate current in this bias range. Thus, in narrow-fin FinFETs, the gate edge tunneling current can have strong impact on the drain current for Vgs < Vt, and large Vds.

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Fig. 7. Drain current versus gate voltage in n-channel FinFETs with different fin width Wfin = 25 nm and different gate lengths Lg, measured at drain voltage Vds = 1.02 V. For comparison, the corresponding gate current values are also presented.

To identify the conduction mechanism of the drain leakage current, the drain current was measured as a function of Vds in the subthreshold region for Vgs < Vt, in narrow-fin FinFETs, where the SCEs have negligible contribution. The plots of the drain current measured at V gs = 0 V versus Vds for FinFETs with Wfin = 25 nm and different gate lengths are presented in Fig. 8a. The independence of the drain leakage current on the gate length Lg (i.e. the gate area) indicates that the drain leakage current is caused by tunneling at the gate edges. The plots of log (Ids/Vdg) versus 1/Vdg for different values of Vgs and Vds are presented in Fig. 8b. A straight line fits the data in the higher field region, proving that the drain leakage current conduction is dominated by the band-to-band tunneling mechanism. The observed band-to-band tunneling at relatively low electric fields indicates that this mechanism is interface trap-assisted [14,15].

Fig. 8. (a) Plots of drain leakage current at Vgs = 0 V versus drain voltage Vds in nchannel FinFETs with fin width Wfin = 25 nm and different gate lengths Lg, (b) plots of Ids/Vdg versus 1/Vdg in n-channel FinFETs with fin width Wfin = 25 nm. The voltage Vgs = Vds Vgs and the drain leakage current Ids were extracted from the experimental transfer characteristics for a constant either gate voltage or drain voltage.

In order to investigate the contribution of the top-gate edge tunneling to the measured drain leakage current, the drain current was measured as a function of Vds in the subthreshold region for Vgs < Vt, in FinFETs with gate length Lg = 410 nm and different fin widths where SCEs are negligible. Fig. 9a shows the plots of the drain current versus Vds for FinFETs with fin-widths Wfin = 25, 55 and 125 nm, measured at V gs = 0 V. It is clearly shown that the measured drain current is independent on the fin width, suggesting that the drain leakage current originates predominantly from trap-assisted sidewall-gate edge tunneling current. The linear dependence of log (Ids/Vdg) versus 1/Vdg data in Fig. 9b indicates also that the drain leakage current is due to the band-to-band tunneling mechanism. The dominance of the sidewall-gate edge tunneling is consistent with the results of previous work, where the trap density at the sidewall-gate interfaces was found to be higher compared to the top-gate interface trap density, attributed to the higher fin sidewall roughness and not to the different crystallographic orientation of the sidewall [16]. Furthermore, this finding is consistent with the top and sidewall mobility values extracted in FinFETs from maximum transconductance [17] and split capacitance–voltage and output conductance measurements [18], from which the carrier mobility of the side-channels was found to be lower than the mobility of the top-channel. However, in triple-gate FinFETs with low channel carrier concentration the threshold voltages corresponding to the top and sidewall channels coincide [19], suggesting that the interface states are closely related only with the sidewall edge tunneling current and the carrier mobility. The aforementioned results show that the increase of the gate current with decreasing Vgs is enhanced as the technology is scaled down. Fig. 10 shows the ratio of the gate leakage current to the overall drain leakage current (Ig/Ids) as a function of the fin width, measured at Vds = 1.02 V and Vgs = 0 V in FinFETs with different

Fig. 9. (a) Plots of drain leakage current at Vgs = 0 V versus drain voltage Vds in nchannel FinFETs with gate length Lg = 410 nm and different fin widths Wfin, (b) plots of Ids/Vdg versus 1/Vdg for n-channel FinFETs with gate length Lg = 410 nm. The voltage Vgs = Vds Vgs and the drain leakage current Ids were extracted from the experimental transfer characteristics for a constant either gate voltage or drain voltage.

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sidewall-gate interface trap density compared to the top-gate interface trap density. The results presented in this work can be useful for fabricating future generations of low power devices. Acknowledgments This work has been partially supported by the PullNANO European Project. The authors A. Tsormpatzoglou and C.A. Dimitriadis are grateful to the Greek General Secreteriat for Research and Technology for financial support under the contract PENED 2003 (03ED709). References Fig. 10. Ratio of gate leakage current Ig to overall drain leakage current versus fin width Wfin, measured at Vds = 1.02 V and Vgs = 0 V.

gate lengths. For all gate lengths, the ratio Ig/Ids increases as the fin width is scaled down. It is clearly shown that for fin widths below 100 nm the ratio Ig/Ids tends to unity for all gate lengths, indicating the dominance of the sidewall-gate edge tunneling current in the measured gate leakage current. However, for wider fin widths the ratio Ig/Ids becomes larger with increasing the gate length due to enhancement of the SCEs. The overall experimental results show that, in the bias region of Vgs < Vt, with high Vds value, the sidewall-gate edge tunneling current increases considerably for extremely narrow FinFETs deteriorating the drain leakage current. For wide FinFETs, the gate tunneling current level is low without affecting the drain leakage current. This leakage current behavior is caused by changing the conduction from the top fin surface to the side fin surfaces characterized by interface states of higher density. These results indicate the necessity for reduction of the sidewall interface state density to enhance the performance of narrow width FinFETs. Recently, it has been demonstrated that after NH3 plasma treatment of nano-SOI FinFETs, the leakage current is suppressed dramatically [20]. 4. Conclusions The subthreshold leakage current in triple-gate FinFETs has been investigated experimentally for power supply voltage Vdd = 1 V in terms of the fin width and gate length. The studied devices have fin height Hfin = 65 nm, fin width Wfin = 25, 55, 125 and 875 nm, and the gate length is varying from 50 to 910 nm. Whereas the present devices satisfy the ITRS requirements for HP and LOP technologies, the ITRS projections for LSTP technology cannot be achieved. Detailed investigation of the gate and drain leakage currents was made to clarify the origin of these currents. In wide FinFETs where the top-gate dominates, the measured subthreshold drain current is much larger than the gate tunneling current due to the strong SCEs. In narrow FinFETs (Wfin = 25 nm) where the SCEs are negligible, the importance of the trap-assisted sidewall gates edge tunneling current on the drain leakage current has been demonstrated. The observed leakage current behavior with decreasing the fin width has been attributed to the higher

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