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Extraction of gate-edge workfunction of metal gate and its impact on scaled MOSFETs
Microelectronic Engineering 84 (2007) 2201–2204 www.elsevier.com/locate/mee
Extraction of gate-edge workfunction of metal gate and its impact on scaled MOSFETs N. Mise*, T. Matsuki, T. Watanabe, T. Eimori, Y. Nara Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki, 305-8569, Japan
Abstract The gate-edge properties of a metal/high-k gate stack are of crucial importance, but they have not been quantitatively investigated. In this paper, we have proposed a new method for extracting the local workfunction of the gate electrode by using a sideways overturned stack. We revealed that the TaSiN workfunction on their 10-nm long gate-edges shifted for 0.1 eV after a 1000ºC annealing. Based on these parameters, we simulated the impact of the gate-edge metamorphoses (GEM) and found that GEM increased the threshold voltage for scaled devices with a 60-nm long or shorter gate without suppressing a short-channel effect. Keywords: metal gate; high-k gate dielectric; gate-edge metamorphoses; workfunction; scaled device
1. Introduction Gate stack with a metal gate electrode and a high-k gate dielectric plays an essential role in aggressively scaled MOSFETs. The properties of such stacks have been extensively investigated with focus on the bulk properties. However, we have to pay a close attention to the gate-edge properties as well first because the metal/high-k gate stack will be introduced in short-channel devices with 20 nm or shorter gates and secondly because the properties of the metal and the high-k are more subject to change
Corresponding author. Tel.:+ 81 29 849 1187; fax: +81 29 849 1186. E-mail address:[email protected] (N. Mise)
0167-9317/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2007.04.040
by a high-temperature process step than a conventional poly-Si gate and SiO2 gate dielectric. For example, increase in equivalent oxide thickness (EOT), especially in its interfacial layer, was inferred from a TEM image only on the gate-edges [1-3]. This is one of the most typical gate-edge metamorphoses (GEM) in a metal/high-k gate stack. Shift in workfunction Im of the metal gate in Fig. 1 is one of the other GEM. The workfunction shift without and with a high-temperature annealing is often discussed for screening thermally robust gate materials. The edge properties, however, have never been focused on from this point of view. Since the metamorphoses are limited only on the gate edges, they are not reflected in the performance of the longchannel devices. In contrast, it is difficult to extract
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N. Mise et al. / Microelectronic Engineering 84 (2007) 2201–2204
the gate-edge properties from the performance of the short-channel devices because they usually suffer from a short-channel effect.
metamorphosed workfunction Im,GEM and its range LGEM were extracted form the C-V characteristics and their thickness dependence. The metamorphosed gate-edges were thus simulated with these overturned stacks. Since the offset-spacer SiN is amorphous, the grain of TaSiN is not regularly ordered and the influence of annealing is independent of the lateral or vertical direction of the sample, the extracted values are estimated to reflect the properties in a standard MOSFET except for the influence of dry etch and halo implantation [3].
Fig. 1. Cross sectional view of a typical metal/high-k gate stack and a magnified image of metamorphosed workfunction Im,GEM on gate edges and its range LGEM.
Therefore, we developed a new method to extract a local workfunction on the gate edges and actually extracted the gate-edge workfunction. Based on these extracted parameters, we also projected the shortchannel performance by numerical simulation. 2. Experimental Figure 2 illustrates our proposed method to quantify the gate-edge workfunction by overturning a lateral sidewall (offset spacer)-metal stack. First, SiN/TaSiN/SiO2 gate stacks with different TaSiN thicknesses (5, 10, 20, and 50 nm) were prepared. The TaSiN gate was chosen as a gate electrode for nMOSFETs [4]. The SiN film was made from hexachlorodisilane (Si2Cl6) and ammonia (NH3) at 600ºC. This vertical SiN/TaSiN stack simulated the lateral stack with SiN sidewall and the TaSiN gate in a standard MOSFET as shown in Fig. 1. The 10-nm thick SiO2 gate dielectric instead of high-k gate dielectric was used in order to extract the workfunction of the TaSiN gate without an unwanted flatband voltage shift or EOT increase due to the metamorphoses in the high-k gate dielectric or its interfacial layer. Some of these samples were then annealed at 1000ºC. Next, the SiN was removed, W and TiN were deposited, and the gates were defined. Finally, the capacitance-voltage (C-V) characteristics of the TiN/W/TaSiN/SiO2 stacks were measured. The
Fig. 2. Process flow for extraction of metamorphosed workfunction Im,GEM and its range LGEM by using a overturned stack.
3. Results and discussion Figure 3 shows the C-V curves of the TaSiN/SiO2 stacks without and with 1000ºC annealing. No difference was observed between the samples with different TaSiN thicknesses without the annealing. On the contrary, the C-V curves with the annealing were thickness-dependent; those for a 20- and 50-nm thick one were virtually identical while that for a 5nm thick one was basically a shift and the curve for a 10-nm thick one was something between that for a 5and a 20-nm thick one. Judging from the frequency-
N. Mise et al. / Microelectronic Engineering 84 (2007) 2201–2204
independence for all C-V curves, the 10-nm thick TaSiN was estimated to be partially metamorphosed in its TaSiN/SiO2 interface.
Fig. 3. C-V characteristics are identical for different TaSiN thicknesses without the annealing (a) while they are dependent of TaSiN thickness with the annealing (b).
4. Projection of the scaled devices Based on the extracted Im,GEM and LGEM, the performances of nMOSFETs as shown in Fig. 5 were simulated. For each gate length Lg, two cases without and with GEM were simulated [5]. The assumed workfunction of the gate was 4.3 eV without GEM and 4.4 eV with GEM. The GEM range covered the 10-nm long gate edges. For 40-nm long gate, for example, the 20-nm long center of the gate was attributed to 4.3 eV while the 10-nm long source edge and the same long drain edge were to 4.4 eV. The EOT was set to be 1 nm and the source and drain extensions was to be 5-nm deep. The overlap length was assumed to be 0 nm for simplicity. The drain current to gate voltage (Id-Vg) characteristics at 1 V of drain bias Vd were shown in Fig. 6. As Lg became small, not only a short-channel effect became more obvious for both cases, but also the difference between the two Id-Vg curves without and with GEM became large.
Figure 4 summarizes the flatband voltage Vfb as a function of TaSiN thickness without and with the annealing. The flatband voltage for 10-nm thick or thinner TaSiN positively shifted for 0.1 V from the initial Vfb while that for 20-nm thick or thicker TaSiN stayed constant. From these results, the metamorphosed effective workfunction Im,GEM was extracted to be 0.1 eV higher than the initial Im and the metamorphoses range LGEM was to be 10 nm. Fig. 5. Simulated device structure without and with 100 mV shift in Im on 10-nm long gate edges. The constant parameters are: EOT=1 nm, Xj = 5nm, and concentration of the channel Na = 1018 cm-3.
Fig. 4. The flatband voltage Vfb is independent of the TaSiN thickness without the 1000ºC annealing. A 100 mV of Vfb shift was observed for 10-nm thick or thinner TaSiN with the annealing. The shift, however, was not observed for 20-nm thick or thicker TaSiN.
The difference in threshold voltage 'Vth as a function of Lg was plotted in Fig. 7. The difference 'Vth was defined as the difference between the threshold voltage with GEM VthGEM and that without GEM Vth, that is, 'Vth = VthGEM - Vth. The difference 'Vth was as small as 0.013 V for a 60-nm long gate. In contrast, it rapidly increased as Lg shrunk beyond 60 nm. When the gate length was 40 and 30nm, 'Vth was 0.038 and 0.063 V respectively. When it became 20 nm or shorter, 'Vth stayed constant at 0.1 V because all part of the gate was attributed to the metamorphosed workfunction Im,GEM.
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Although GEM increased Vth, it did not suppress a short-channel effect as shown in Fig. 8; GEM only increased Vth without decreasing the subthreshold swing. This means that the on-state current was supposed to be smaller with GEM and that GEM should be suppressed. Since GEM are thus reflected only in the shortchannel performance, they are not observed in the long-channel devices and are subject to be buried in the short-channel effect. Suppression of GEM, however, is indispensable for scaled devices.
Fig. 8. The threshold voltage with GEM is always higher at the same subthreshold swing, which results in a smaller onstate current.
5. Conclusions
Fig. 6. Simulated Id-Vg characteristics without and with GEM for Lg=20, 60 and 100 nm.
We have introduced the concept of gate-edge metamorphoses (GEM) that determine the performance of the short-channel MOSFETs. We revealed that the effective workfunction of 10-nm long TaSiN gate edges shifted for 0.1 eV after 1000ºC annealing by using an overturned stack. These GEM increase the threshold voltage of the devices especially for 60-nm or shorter gates without suppressing a short-channel effect. Control of GEM is essential for scaled metal/high-k MOSFETs. References
Fig. 7. The threshold voltage difference ǻVth induced by GEM rapidly increases when Lg shrinks to 60 nm or smaller.
[1] T. Iwamoto, T. Ogura, M. Terai, H. Watanabe, H. Watanabe, N. Ikarashi, M. Miyamura, T. Tatsumi, M. Saitoh, A. Morioka, K. Watanabe, Y. Saito, Y. Yabe, T. Ikarashi, K. Masuzaki, Y. Mochizuki, T. Mogami, IEDM Tech. Dig. (2003) 639. [2] T. Watanabe, M. Takayanagi, K. Kojima, K. Sekine, H. Yamasaki, K. Eguchi, K. Ishimaru, H. Ishiuchi, IEDM Tech. Dig. (2004) 507. [3] S-C. Song, Z. Zhang, C. Huffman, J. H. Sim, S. H. Bae, P. D. Kirsch, P. Majhi, R. Choi, N. Moumen, B. H. Lee, IEEE Trans. Electron. Dev. 53 (2006) 979. [4] F. Ootsuka Y. Tamura, Y. Akasaka , S. Inumiya, H. Nakata, M. Ohtsuka, T. Watanabe, M Kitajima, Y. Nara, K. Nakamura, Ext. Abst. SSDM (2006) 1116. [5] T. Wada and N. Kotani, IEICE Trans. Electron. E82-C (1999) 839.
Extraction of gate-edge workfunction of metal gate and its impact on scaled MOSFETs N. Mise*, T. Matsuki, T. Watanabe, T. Eimori, Y. Nara Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki, 305-8569, Japan
Abstract The gate-edge properties of a metal/high-k gate stack are of crucial importance, but they have not been quantitatively investigated. In this paper, we have proposed a new method for extracting the local workfunction of the gate electrode by using a sideways overturned stack. We revealed that the TaSiN workfunction on their 10-nm long gate-edges shifted for 0.1 eV after a 1000ºC annealing. Based on these parameters, we simulated the impact of the gate-edge metamorphoses (GEM) and found that GEM increased the threshold voltage for scaled devices with a 60-nm long or shorter gate without suppressing a short-channel effect. Keywords: metal gate; high-k gate dielectric; gate-edge metamorphoses; workfunction; scaled device
1. Introduction Gate stack with a metal gate electrode and a high-k gate dielectric plays an essential role in aggressively scaled MOSFETs. The properties of such stacks have been extensively investigated with focus on the bulk properties. However, we have to pay a close attention to the gate-edge properties as well first because the metal/high-k gate stack will be introduced in short-channel devices with 20 nm or shorter gates and secondly because the properties of the metal and the high-k are more subject to change
Corresponding author. Tel.:+ 81 29 849 1187; fax: +81 29 849 1186. E-mail address:[email protected] (N. Mise)
0167-9317/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2007.04.040
by a high-temperature process step than a conventional poly-Si gate and SiO2 gate dielectric. For example, increase in equivalent oxide thickness (EOT), especially in its interfacial layer, was inferred from a TEM image only on the gate-edges [1-3]. This is one of the most typical gate-edge metamorphoses (GEM) in a metal/high-k gate stack. Shift in workfunction Im of the metal gate in Fig. 1 is one of the other GEM. The workfunction shift without and with a high-temperature annealing is often discussed for screening thermally robust gate materials. The edge properties, however, have never been focused on from this point of view. Since the metamorphoses are limited only on the gate edges, they are not reflected in the performance of the longchannel devices. In contrast, it is difficult to extract
2202
N. Mise et al. / Microelectronic Engineering 84 (2007) 2201–2204
the gate-edge properties from the performance of the short-channel devices because they usually suffer from a short-channel effect.
metamorphosed workfunction Im,GEM and its range LGEM were extracted form the C-V characteristics and their thickness dependence. The metamorphosed gate-edges were thus simulated with these overturned stacks. Since the offset-spacer SiN is amorphous, the grain of TaSiN is not regularly ordered and the influence of annealing is independent of the lateral or vertical direction of the sample, the extracted values are estimated to reflect the properties in a standard MOSFET except for the influence of dry etch and halo implantation [3].
Fig. 1. Cross sectional view of a typical metal/high-k gate stack and a magnified image of metamorphosed workfunction Im,GEM on gate edges and its range LGEM.
Therefore, we developed a new method to extract a local workfunction on the gate edges and actually extracted the gate-edge workfunction. Based on these extracted parameters, we also projected the shortchannel performance by numerical simulation. 2. Experimental Figure 2 illustrates our proposed method to quantify the gate-edge workfunction by overturning a lateral sidewall (offset spacer)-metal stack. First, SiN/TaSiN/SiO2 gate stacks with different TaSiN thicknesses (5, 10, 20, and 50 nm) were prepared. The TaSiN gate was chosen as a gate electrode for nMOSFETs [4]. The SiN film was made from hexachlorodisilane (Si2Cl6) and ammonia (NH3) at 600ºC. This vertical SiN/TaSiN stack simulated the lateral stack with SiN sidewall and the TaSiN gate in a standard MOSFET as shown in Fig. 1. The 10-nm thick SiO2 gate dielectric instead of high-k gate dielectric was used in order to extract the workfunction of the TaSiN gate without an unwanted flatband voltage shift or EOT increase due to the metamorphoses in the high-k gate dielectric or its interfacial layer. Some of these samples were then annealed at 1000ºC. Next, the SiN was removed, W and TiN were deposited, and the gates were defined. Finally, the capacitance-voltage (C-V) characteristics of the TiN/W/TaSiN/SiO2 stacks were measured. The
Fig. 2. Process flow for extraction of metamorphosed workfunction Im,GEM and its range LGEM by using a overturned stack.
3. Results and discussion Figure 3 shows the C-V curves of the TaSiN/SiO2 stacks without and with 1000ºC annealing. No difference was observed between the samples with different TaSiN thicknesses without the annealing. On the contrary, the C-V curves with the annealing were thickness-dependent; those for a 20- and 50-nm thick one were virtually identical while that for a 5nm thick one was basically a shift and the curve for a 10-nm thick one was something between that for a 5and a 20-nm thick one. Judging from the frequency-
N. Mise et al. / Microelectronic Engineering 84 (2007) 2201–2204
independence for all C-V curves, the 10-nm thick TaSiN was estimated to be partially metamorphosed in its TaSiN/SiO2 interface.
Fig. 3. C-V characteristics are identical for different TaSiN thicknesses without the annealing (a) while they are dependent of TaSiN thickness with the annealing (b).
4. Projection of the scaled devices Based on the extracted Im,GEM and LGEM, the performances of nMOSFETs as shown in Fig. 5 were simulated. For each gate length Lg, two cases without and with GEM were simulated [5]. The assumed workfunction of the gate was 4.3 eV without GEM and 4.4 eV with GEM. The GEM range covered the 10-nm long gate edges. For 40-nm long gate, for example, the 20-nm long center of the gate was attributed to 4.3 eV while the 10-nm long source edge and the same long drain edge were to 4.4 eV. The EOT was set to be 1 nm and the source and drain extensions was to be 5-nm deep. The overlap length was assumed to be 0 nm for simplicity. The drain current to gate voltage (Id-Vg) characteristics at 1 V of drain bias Vd were shown in Fig. 6. As Lg became small, not only a short-channel effect became more obvious for both cases, but also the difference between the two Id-Vg curves without and with GEM became large.
Figure 4 summarizes the flatband voltage Vfb as a function of TaSiN thickness without and with the annealing. The flatband voltage for 10-nm thick or thinner TaSiN positively shifted for 0.1 V from the initial Vfb while that for 20-nm thick or thicker TaSiN stayed constant. From these results, the metamorphosed effective workfunction Im,GEM was extracted to be 0.1 eV higher than the initial Im and the metamorphoses range LGEM was to be 10 nm. Fig. 5. Simulated device structure without and with 100 mV shift in Im on 10-nm long gate edges. The constant parameters are: EOT=1 nm, Xj = 5nm, and concentration of the channel Na = 1018 cm-3.
Fig. 4. The flatband voltage Vfb is independent of the TaSiN thickness without the 1000ºC annealing. A 100 mV of Vfb shift was observed for 10-nm thick or thinner TaSiN with the annealing. The shift, however, was not observed for 20-nm thick or thicker TaSiN.
The difference in threshold voltage 'Vth as a function of Lg was plotted in Fig. 7. The difference 'Vth was defined as the difference between the threshold voltage with GEM VthGEM and that without GEM Vth, that is, 'Vth = VthGEM - Vth. The difference 'Vth was as small as 0.013 V for a 60-nm long gate. In contrast, it rapidly increased as Lg shrunk beyond 60 nm. When the gate length was 40 and 30nm, 'Vth was 0.038 and 0.063 V respectively. When it became 20 nm or shorter, 'Vth stayed constant at 0.1 V because all part of the gate was attributed to the metamorphosed workfunction Im,GEM.
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N. Mise et al. / Microelectronic Engineering 84 (2007) 2201–2204
Although GEM increased Vth, it did not suppress a short-channel effect as shown in Fig. 8; GEM only increased Vth without decreasing the subthreshold swing. This means that the on-state current was supposed to be smaller with GEM and that GEM should be suppressed. Since GEM are thus reflected only in the shortchannel performance, they are not observed in the long-channel devices and are subject to be buried in the short-channel effect. Suppression of GEM, however, is indispensable for scaled devices.
Fig. 8. The threshold voltage with GEM is always higher at the same subthreshold swing, which results in a smaller onstate current.
5. Conclusions
Fig. 6. Simulated Id-Vg characteristics without and with GEM for Lg=20, 60 and 100 nm.
We have introduced the concept of gate-edge metamorphoses (GEM) that determine the performance of the short-channel MOSFETs. We revealed that the effective workfunction of 10-nm long TaSiN gate edges shifted for 0.1 eV after 1000ºC annealing by using an overturned stack. These GEM increase the threshold voltage of the devices especially for 60-nm or shorter gates without suppressing a short-channel effect. Control of GEM is essential for scaled metal/high-k MOSFETs. References
Fig. 7. The threshold voltage difference ǻVth induced by GEM rapidly increases when Lg shrinks to 60 nm or smaller.
[1] T. Iwamoto, T. Ogura, M. Terai, H. Watanabe, H. Watanabe, N. Ikarashi, M. Miyamura, T. Tatsumi, M. Saitoh, A. Morioka, K. Watanabe, Y. Saito, Y. Yabe, T. Ikarashi, K. Masuzaki, Y. Mochizuki, T. Mogami, IEDM Tech. Dig. (2003) 639. [2] T. Watanabe, M. Takayanagi, K. Kojima, K. Sekine, H. Yamasaki, K. Eguchi, K. Ishimaru, H. Ishiuchi, IEDM Tech. Dig. (2004) 507. [3] S-C. Song, Z. Zhang, C. Huffman, J. H. Sim, S. H. Bae, P. D. Kirsch, P. Majhi, R. Choi, N. Moumen, B. H. Lee, IEEE Trans. Electron. Dev. 53 (2006) 979. [4] F. Ootsuka Y. Tamura, Y. Akasaka , S. Inumiya, H. Nakata, M. Ohtsuka, T. Watanabe, M Kitajima, Y. Nara, K. Nakamura, Ext. Abst. SSDM (2006) 1116. [5] T. Wada and N. Kotani, IEICE Trans. Electron. E82-C (1999) 839.