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Further improvements in equivalent-circuit model with levelized incomplete LU factorization for mixed-level semiconductor device and circuit simulation
Solid-State Electronics 48 (2004) 1181–1188 www.elsevier.com/locate/sse
Further improvements in equivalent-circuit model with levelized incomplete LU factorization for mixed-level semiconductor device and circuit simulation Jing-Fu Dai, Chia-Cherng Chang, Szu-Ju Li, Yao-Tsung Tsai
*
Department of Electrical Engineering, National Central University, Chungli 320, Taiwan, ROC Received 23 July 2003
The review of this paper was arranged by Prof. Y. Arakawa
Abstract Numerical simulation of semiconductor devices plays a very important role in the design and development of integrated circuits. We have successfully proposed a new level of convergence performance, when truncation parameter a ¼ 1, by combining a simplified, decoupled Gummel-like method (DM) equivalent-circuit model and levelized incomplete LU (L-ILU) factorization in simulating arbitrary, planar semiconductor devices. Further, in order to overcome the problem of decoupled method that the boundary of the device’s terminal must be connected to a voltage source, we present a partial decoupled equivalent-circuit model (PDM) with levelized incomplete LU factorization. The complementary techniques for enhancing matrix diagonal dominance and helping program convergence are successfully combined to yield an efficient and robust decoupled nonlinear solution method for numerical simulation. It not only saves memory consumption but also can provide an effective matrix solver for mixed-level semiconductor device and circuit simulation. 2004 Elsevier Ltd. All rights reserved. Keywords: Truncation parameter; Gummel-like method; Levelized incomplete LU
1. Introduction Numerical analysis of semiconductor device generally requires solving large sparse matrix equations. Matrix solver plays a very important role in semiconductor device simulation, especially in two or three-dimensional device simulation. From the above, developing a matrix solver with fewer system resource is needed for the device simulation. However, in a largescale simulation, the memory consumption in solving the linear equation readily increases with the grid-point scale. Therefore, in the conventional Newton-like coupled method (CM) with 3N simultaneous equations,
*
Corresponding author. Tel.: +886-3-4227151x4450; fax: +886-3-4255830. E-mail address: [email protected] (Y.-T. Tsai).
3N 3N memory space is required for A in solving matrix equation Ax ¼ b. The programs conventionally use the CM, with relatively high memory requirements. Hence, it is not suitable for large-scale simulation, i.e., simulation with larger grid points cannot be done in a PC environment. From the above, developing a matrix solver uses fewer system resources is needed for the device simulation. On the other hand, in order to provide the semiconductor device simulation an effective development circumstance, we used the equivalent-circuit method to simplify the programming. Poisson’s and continuity equations which control the behavior of charge carriers inside a semiconductor device are formulated into equivalent-circuit, so that circuit elements such as voltage sources, resistors and capacitors can be used to implement the device equations [1]. The device is converted to an equivalent-circuit, which makes the device
0038-1101/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.01.004
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simulation problem become a circuit analysis problem and allows simultaneous solution of an electrical network containing both external circuit elements and 1D or 2D numerical device models. However, in the conventional equivalent-circuit model for the CM, some voltage-controlled current source (VCCS) models are included in the equivalent-circuit, and it is also more difficult in programming and debugging. Hence, we have successfully presented a more efficient equivalent-circuit model for DM in semiconductor device simulation. It not only save the required memory space effectively but also simplify the complex VCCS to nonlinear resistor form. A new level of convergence performance [2], when truncation parameter a ¼ 1, has been achieved by combining a simplified, decoupled Gummel-like method equivalent-circuit model and levelized incomplete LU (L-ILU) factorization in simulating arbitrary, planar semiconductor devices. Further, in recent years, the mixed-level semiconductor device and circuit simulation is an extensively discussed topic. It can provide a direct link between technology parameters and circuit performance, and predict the effects due to variations in technology and device design. However, the boundary of the device’s terminal must be connected to a voltage source (not current source or others) in the DM equivalent-circuit model. In order to overcome the problem, we propose a partial decoupled method equivalent-circuit model with levelized incomplete LU factorization [3,4]. In equivalent-circuit, it is more realistic to calculate current with coupling the two carrier equivalent-circuits. The effectiveness of the new method exhibits a good stability and convergence rate, and user interaction with the computational process is significantly reduced. Low memory requirements and efficiency should pave the method to its widespread application in multidimensional mixedlevel semiconductor device and circuit simulation.
2. The levelized incomplete LU factorization In semiconductor devices simulation, we must solve large matrix equations. In order to obtain accurate numerical analysis in semiconductor device simulation, we have to divide the device into many elements. This leads into large size matrix equations. Because of the super-linear growth rate of solution costs in direct methods, direct methods are not suitable in semiconductor devices simulation for large matrix equations. In order to have an efficient circuit simulation environment, we develop a new sparse matrix solver using the L-ILU method based on ILU decomposition. During LU decomposition, every nonzero entry has its own level. Users can choose a suitable level ‘‘a’’, which is called the truncation parameter, according to the property of matrix A. If the generated fill-in level is
greater than a, the fill-in is considered to be of minor importance and must be rejected. Otherwise, it must be retained and may cause the generation of other fill-ins. The truncation parameter a plays the most important role in the L-ILU method. When a is equal to 0, the linear iteration scheme is Gauss–Jacobi iteration, only the diagonal entries need to be considered, so we do not need to factor the matrix. If a is equal to 1, it represents complete LU decomposition. We can adjust the parameter a to control the direct method or iterative method strength. Therefore, we can dynamically choose the a from 0 to 1 to increase the speed of the solutions and ensure the accuracy of the solutions. 3. The equivalent-circuit model development In the past, we use Newton–Raphson [5] and complete LU method in device simulation. Usually, Poisson’s and continuity equations govern the semiconductor behavior. Most of the existing device simulations are based on the drift-diffusion (DD) description of carrier transport, and employ specialized techniques to obtain the one, two, or three-dimensional solutions in time domain. The carrier transport in semiconductor is described by three coupled partial differential equations, namely, the Poisson equation, the electron continuity equation and hole equation [6,7] as follows: q r2 u ¼ ½p n þ NDþ NA ; ð1Þ e on 1 ¼ r ~ J n R; ot q
ð2Þ
op 1 ¼ r ~ J p R: ot q
ð3Þ
For one-dimensional device simulation, a device can be partitioned into n 1 elements and n nodes. Fig. 2 shows the one-dimensional device’s equivalent-circuit model [8]. With the equivalent circuit approach, the simulated device can be replaced by a circuit representation. The number of unknown variables will be 3n by using a circuit simulator. It can be seen that each grid point is represented by three circuit nodes, which includes the electrostatic potential and the electron quasiFermi potential and the hole quasi-Fermi potential. First of all, the box-integration method [9] based on element by element is used to discrete Poisson’s equation. The element-by-element method is better for computer simulation than the node-by-node method. For the ith element in Fig. 1(a), Poisson’s equation can be rewritten as ui uiþ1 hi eA þ qðn p NDþ þ NA Þi A ¼ 0; ð4Þ hi 2 where A is the cross area.
J.-F. Dai et al. / Solid-State Electronics 48 (2004) 1181–1188
2
3 ofu o/p 7 " # 7 Duk ofun 7 k 7 D/n o/p 7 D/kp 3N 1 7 ofup 5 o/p 3N 3N 3 k fu ðu ; /kn ; /kp Þ ¼ 4 fun ðuk ; /kn ; /kp Þ 5 ; fup ðuk ; /kn ; /kp Þ 3N 1
ofu 6 ou 6 6 ofun 6 6 ou 6 4 ofup ou 2
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ofu o/n ofun o/n ofup o/n
ð8Þ
and
Fig. 1. One-dimensional equivalent-circuit model for semiconductor device of the CM: (a) ith element in one-dimensional simulation; (b) equivalent-circuit for Poisson’s equation; (c) circuit for electron continuity equation; (d) circuit for hole continuity equation.
Eq. (4) can be simplified as Iu1 þ Iu2 ¼ 0;
ð5Þ
where Iu1
eA ¼ ðui uiþ1 Þ; hi
Iu2 ¼ qðn p NDþ þ NA Þi
ð6Þ hi A: 2
ð7Þ
Similarly, we can obtain the equivalent-circuits for the electron continuity equation and the hole continuity Eq. [4]. We use LU method in 1D semiconductor device simulation. The matrix equations Ax ¼ b can be solved by Newton–Raphson. The Newton–Raphson method is written as follows:
ukþ1 ¼ uk þ Duk ;
ð9Þ
¼ /kn þ D/kn ; /kþ1 n
ð10Þ
¼ /kp þ D/kp : /kþ1 p
ð11Þ
If Duk , D/kn and D/kp are close to zero, the solution u, /n , /p will be obtained at the same time. The dimension of matrix A is 3N 3N . Therefore, in the conventional CM with 3N simultaneous equations, 3N 3N memory space is required for A in solving matrix equation Ax ¼ b. It spends much memory space by using the conventional CM. If we solve the potential u, /n , /p respectively, the matrix must be modified by Gummel’s method [10]. The Newton–Raphson method for solving the Poisson’s equation is written as follows: 2 3 ofu1 ofu1 ofu1 ofu1 2 3 Du1 6 ou ou2 ou3 oun 7 6 1 7 6 7 6 7 6 Du2 7 .. 7 .. .. 6 .. 6 7 . 6 . . 7 . . 4 .. 5 6 7 4 ofum ofum ofum 5 ofum Dum 3N 1 ou1 ou2 ou3 oum N N 2 3 fu1 6 fu2 7 6 7 ¼ 6 . 7 ; 4 .. 5 fum N 1 ð12Þ If Du, D/n and D/p are close to zero, then the potential u, /n and /p can be obtained respectively. The simplified DM equivalent-circuit model as shown in Fig. 2 can reduce the memory space effectively from 3N 3N to N N , nine times smaller and simplify the conventional equivalent-circuit model successfully by using a nonlinear resistor to replace the VCCS. The complicated Gummel’s method is automatically included in the DM. However, in mixed-level semiconductor device and circuit simulation, the boundary of the device’s terminal must be connected to a voltage source (not current) source or others) in the DM equivalent-circuit model with levelized incomplete LU factorization. The PDM first solves Poisson’s equation in the form:
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Fig. 3. The comparison of A matrix size for the CM, DM and the PDM.
ization mentioned above is discussed. For the aforementioned section, we use the DM and the PDM to solve the matrix equation Ax ¼ b, and they will reduce memory space effectively, as shown in Fig. 3. The large a will cause insufficient memory space and the program will be stopped if the CM is chosen for large-scale simulation, i.e., simulation with larger grid points cannot be done in a PC environment [2]. Furthermore, by comparing with mixed-level equivalent-circuit model, as shown in Fig. 4(a), if we use the CM to solve the Poisson equation, the Iuy , as indicated in Fig. 4(b), is written as follows: Fig. 2. One-dimensional equivalent-circuit model for semiconductor device of the DM: (a) ith element in one-dimensional simulation; (b) equivalent-circuit for Poisson’s equation; (c) circuit for electron continuity equation; (d) circuit for hole continuity equation.
ofu ou
½DuN 1 ¼ ½fu N 1 ;
ð13Þ
N N
Then it 2 of /n 6 o/n 6 6 4 of/p o/n
solves the two continuity equations in the form: of/n 3 o/p 7 f/n D/n 7 ¼ : ð14Þ 7 f/p 2N 1 D/p 2N 1 of/p 5 o/p
2N 2N
4. Simulation and comparison In this section, the implementation and simulation using the CM, DM and the PDM with L-ILU factor-
hi A 2 kþ1 kþ1 kþ1 ¼ f ðu ; /n ; /p Þ ¼ VCCS:
Iuy ¼ qðn p NDþ þ NA Þi
ð15Þ
The variables u, /n and /p are node variables, and Iuy will form a voltage-controlled current source (VCCS). Hence, the difficultly in programming and debugging will be enhanced. Therefore, if we solve the Poisson’s equation and continuity equations respectively, the Eq. (15) can be re-written as follows: Iuy ¼ qðn p NDþ þ NA Þi ¼ nonlinear resistor;
hi A ¼ f ðukþ1 ; /kn ; /kp Þ 2 ð16Þ
in Eq. (16), only u is unknown variable parameter, i.e., /n and /p are constants. Hence, a nonlinear resistor can be obtained in the PDM mixed-level circuit, as shown in Fig. 4(c), and the complexity of the equivalent-circuit will be simplified
J.-F. Dai et al. / Solid-State Electronics 48 (2004) 1181–1188
drastically, i.e., the complex VCCS will be simplified as grounded nonlinear resistance and this will enhance matrix diagonal dominance and help the convergence of program. Further, by comparing the memory consumption between the PDM and the DM, PDM needs more, but it can provide a direct link between device and external circuit, and solve the uncertainty of the electric-potential at the boundary of the device’s terminal in a mixed-level semiconductor device and circuit simulation. For instance, in Fig. 4(d), we separate the continuity equations and solve /n , /p respectively, i.e. DM, and we exchange the voltage source for current source. Thus, we cannot confirm what percentage of current is injected into the electron and the hole continuity equations. Therefore, to compare with the identical potential (Va ) in the PDM mixed-level circuit as shown in Fig. 4(c), we cannot ensure the potentials (Va ) at the boundary of the device’s terminal identical in the DM mixed-level circuit. Hence, the program does not work if the DM is chosen. We present the simulation of 2D MOSFET and CMOS devices to illustrate the capabilities and efficiency
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of the PDM equivalent-circuit model with L-ILU factorization. This device’s width is 1 lm, the thickness of gate oxide is 0.05 lm and the channel length is 1 lm. The doping concentration of the p-type substrate for the N-MOSFET device employed is NA ¼ 2 1016 cm3 and that for the n-type source and drain regions are both ND ¼ 1 1018 cm3 . The mobility of electron and hole are 1350 and 430 cm2 /V s ðlp Þ. The lifetime of electron and hole are 1 · 106 s (tn ) and 3 · 106 s (tp ). The device is partitioned into 21 · 13 rectangular grids. Fig. 5 shows the I–V curves for the MOSFET device evaluated by the CM, DM and the PDM with L-ILU factorization. The electric characteristic obtained by the PDM is in good agreement to that obtained by the CM and DM. Fig. 6 shows the dependence of the computation effort of the L-ILU factorization for the DM and the PDM with the lower truncation parameters. The CPU-time efficiency for the PDM is similar to the DM at the lower truncation parameter ‘‘a’’. A CMOS device is composed of P-MOSFET and N-MOSFET. In this study, both of the N-MOSFET and P-MOSFET have the same channel (0.6 lm),
Fig. 4. (a) The mixed-level semiconductor device and circuit schematic; (b) The CM mixed-level equivalent-circuit model; (c) The PDM mixed-level equivalent-circuit model; (d) The DM mixed-level equivalent-circuit model.
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Fig. 4 (continued)
J.-F. Dai et al. / Solid-State Electronics 48 (2004) 1181–1188
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Fig. 5. The ID –VDS characteristic of 2D MOSFET for the CM, DM and the PDM.
Fig. 6. Dependence of the computation effort of the L-ILU method on the different truncation parameter.
gate oxide thickness (0.05 lm), impurity concentration of the substrate (2 · 1016 cm3 ) and source (or drain) regions (1 · 1018 cm3 ). However, the width is 2 lm for NMOS and the width is 6 lm for PMOS. The values of the ln , lp , tn , tp are all the same with the aforementioned ones. The external capacitance is 1
lF. For a CMOS, the requirement of memory space is more than a single MOSFET. This is the reason that why we need to develop more efficiency equivalent-circuit model with L-ILU factorization to save the consumption of memory space. Furthermore, at numerical simulation circumstance, the CMOS output
Fig. 7. (a) The mixed-level CMOS inverter circuit diagram; (b) The CMOS DC transfer characteristic and operating regions; (c) The 2D CMOS structure schematic; (d) A coefficient matrix pattern representation. ( ) diagonal entries, () off-diagonal entries.
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J.-F. Dai et al. / Solid-State Electronics 48 (2004) 1181–1188
5. Conclusion
Fig. 8. The Vo =Vi transfer characteristic of 2D CMOS for the CM and the PDM.
terminal connects with a capacitance to help the convergence of the program. The capacitor ‘‘Cload ’’ is composed of internal parasitic capacitance and external capacitance. Internal parasitic capacitances include Cgd;n Cgd;p , Cdb;n , Cdb;p , Cgb . External capacitance is referred to the input capacitance of next level or the capacitance of interconnection line. Fig. 7(a) and (b) show a CMOS inverter circuit and its DC transfer characteristic and operating regions, respectively. The CMOS structure, as shown in Fig. 7(c), indicated that the channel differential resistances (ro1 and ro2 ) are very large when both of the N-MOSFET and the P-MOSFET are operating in saturation mode, i.e., the CMOS device is operating in c region as shown in Fig. 7(b). Therefore, the VOUT node is floatinglike and by employing Newton–Raphson method, the diagonal dominance will be reduced as shown in Fig. 7(d). Hence, the potentials of u, /n and /p for VOUT node will be uncertain and the program will be difficult to converge. Therefore, the CMOS output terminal needs to connect with a capacitance to help the program convergence. However, the mixed-level circuit will cause the potential (VOUT ) at the boundary of the device’s terminal being uncertain and the program will be stopped if the DM is chosen. Therefore, based on the aforementioned, we use the improved PDM equivalent circuit-model with L-ILU factorization for CMOS device simulation. It not only saves memory consumption but also can provide an effective matrix solver for mixed-level semiconductor device and circuit simulation. Fig. 8 shows the characteristics of the Vo /Vi transfer curves for the CMOS device evaluated by the CM and the PDM. The transfer characteristic obtained by the PDM is in good agreement to that obtained by the CM.
We present an improved equivalent-circuit model (PDM) to solve matrix equation Ax ¼ b which has various advantages over the CM and the DM. This method not only saves memory consumption but also simplifies the complex VCCS as grounded nonlinear resistor. It can enhance matrix diagonal dominance and help program convergence. Furthermore, the programming and debugging for the nonlinear resistor model are much easier than that for the VCCS model. The more important is that the PDM equivalent-circuit model overcomes the problem of the boundary at the device’s terminal. Otherwise, in the DM equivalent-circuit model, the device’s terminal must be connected to a voltage source since the other ones (current source or others) will cause the electric-potential at the boundary of the device’s terminal being uncertain. Therefore, it should pave the method to its widespread application in mixed-level semiconductor device and circuit simulation.
References [1] Leblebici Y, Unlu MS, Morkoc H, Kang SM. Transient simulation of heterojunction photodiodes-part I: computational methods. IEEE J Light Wave Technol 1995;13: 396–405. [2] Dai JF, Chang CC, Li SJ, Tsai YT. A more equivalentcircuit model for levelized incomplete LU factorization in semiconductor device simulation. Int Electron Dev Mater Sym 2002;13:278–81. [3] Eickhoof KM, Engl WL. Levelized incomplete LU factorization and its application to large-scale circuit simulation. IEEE Trans Comput-aided Des 1995;14:720–7. [4] Tsai YT, Lee CY, Tsai MK. Levelized incomplete LU method and its application to semiconductor device simulation. Solid State Electron 2000;44:1069–75. [5] Vlach J, Singhal K. Computer methods for circuit analysis and design. New York: Van Nostrand Reinhold; 1994. 428–430. [6] Chan PCH, Sah CT. Exact equivalent-circuit model for steady-state characterization of semiconductor devices with multiple-energy-level recombination centers. IEEE Trans Electr Dev 1979;ED-26:924–36. [7] Mayaram K, Pederson DO. Coupling algorithms for mixed-level circuit and device simulation. IEEE Trans Comput-aided Des 1992;11:1003–12. [8] Tsai YT, Dai JF, Tsai MK. An improved levelized incomplete LU method and its application to 2D semiconductor device simulation. J Chinese Inst Eng 2001;24:389–96. [9] Tsai YT, Huang LC. Simulation of amorphous silicon thin-film transistor including adapted Gummel method. Int J Num Model Electr Networks, Dev Fields 1997;10:3–11. [10] Selberherr S. Analysis and simulation of semiconductor devices. Berlin: Springer; 1984.
Further improvements in equivalent-circuit model with levelized incomplete LU factorization for mixed-level semiconductor device and circuit simulation Jing-Fu Dai, Chia-Cherng Chang, Szu-Ju Li, Yao-Tsung Tsai
*
Department of Electrical Engineering, National Central University, Chungli 320, Taiwan, ROC Received 23 July 2003
The review of this paper was arranged by Prof. Y. Arakawa
Abstract Numerical simulation of semiconductor devices plays a very important role in the design and development of integrated circuits. We have successfully proposed a new level of convergence performance, when truncation parameter a ¼ 1, by combining a simplified, decoupled Gummel-like method (DM) equivalent-circuit model and levelized incomplete LU (L-ILU) factorization in simulating arbitrary, planar semiconductor devices. Further, in order to overcome the problem of decoupled method that the boundary of the device’s terminal must be connected to a voltage source, we present a partial decoupled equivalent-circuit model (PDM) with levelized incomplete LU factorization. The complementary techniques for enhancing matrix diagonal dominance and helping program convergence are successfully combined to yield an efficient and robust decoupled nonlinear solution method for numerical simulation. It not only saves memory consumption but also can provide an effective matrix solver for mixed-level semiconductor device and circuit simulation. 2004 Elsevier Ltd. All rights reserved. Keywords: Truncation parameter; Gummel-like method; Levelized incomplete LU
1. Introduction Numerical analysis of semiconductor device generally requires solving large sparse matrix equations. Matrix solver plays a very important role in semiconductor device simulation, especially in two or three-dimensional device simulation. From the above, developing a matrix solver with fewer system resource is needed for the device simulation. However, in a largescale simulation, the memory consumption in solving the linear equation readily increases with the grid-point scale. Therefore, in the conventional Newton-like coupled method (CM) with 3N simultaneous equations,
*
Corresponding author. Tel.: +886-3-4227151x4450; fax: +886-3-4255830. E-mail address: [email protected] (Y.-T. Tsai).
3N 3N memory space is required for A in solving matrix equation Ax ¼ b. The programs conventionally use the CM, with relatively high memory requirements. Hence, it is not suitable for large-scale simulation, i.e., simulation with larger grid points cannot be done in a PC environment. From the above, developing a matrix solver uses fewer system resources is needed for the device simulation. On the other hand, in order to provide the semiconductor device simulation an effective development circumstance, we used the equivalent-circuit method to simplify the programming. Poisson’s and continuity equations which control the behavior of charge carriers inside a semiconductor device are formulated into equivalent-circuit, so that circuit elements such as voltage sources, resistors and capacitors can be used to implement the device equations [1]. The device is converted to an equivalent-circuit, which makes the device
0038-1101/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.01.004
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J.-F. Dai et al. / Solid-State Electronics 48 (2004) 1181–1188
simulation problem become a circuit analysis problem and allows simultaneous solution of an electrical network containing both external circuit elements and 1D or 2D numerical device models. However, in the conventional equivalent-circuit model for the CM, some voltage-controlled current source (VCCS) models are included in the equivalent-circuit, and it is also more difficult in programming and debugging. Hence, we have successfully presented a more efficient equivalent-circuit model for DM in semiconductor device simulation. It not only save the required memory space effectively but also simplify the complex VCCS to nonlinear resistor form. A new level of convergence performance [2], when truncation parameter a ¼ 1, has been achieved by combining a simplified, decoupled Gummel-like method equivalent-circuit model and levelized incomplete LU (L-ILU) factorization in simulating arbitrary, planar semiconductor devices. Further, in recent years, the mixed-level semiconductor device and circuit simulation is an extensively discussed topic. It can provide a direct link between technology parameters and circuit performance, and predict the effects due to variations in technology and device design. However, the boundary of the device’s terminal must be connected to a voltage source (not current source or others) in the DM equivalent-circuit model. In order to overcome the problem, we propose a partial decoupled method equivalent-circuit model with levelized incomplete LU factorization [3,4]. In equivalent-circuit, it is more realistic to calculate current with coupling the two carrier equivalent-circuits. The effectiveness of the new method exhibits a good stability and convergence rate, and user interaction with the computational process is significantly reduced. Low memory requirements and efficiency should pave the method to its widespread application in multidimensional mixedlevel semiconductor device and circuit simulation.
2. The levelized incomplete LU factorization In semiconductor devices simulation, we must solve large matrix equations. In order to obtain accurate numerical analysis in semiconductor device simulation, we have to divide the device into many elements. This leads into large size matrix equations. Because of the super-linear growth rate of solution costs in direct methods, direct methods are not suitable in semiconductor devices simulation for large matrix equations. In order to have an efficient circuit simulation environment, we develop a new sparse matrix solver using the L-ILU method based on ILU decomposition. During LU decomposition, every nonzero entry has its own level. Users can choose a suitable level ‘‘a’’, which is called the truncation parameter, according to the property of matrix A. If the generated fill-in level is
greater than a, the fill-in is considered to be of minor importance and must be rejected. Otherwise, it must be retained and may cause the generation of other fill-ins. The truncation parameter a plays the most important role in the L-ILU method. When a is equal to 0, the linear iteration scheme is Gauss–Jacobi iteration, only the diagonal entries need to be considered, so we do not need to factor the matrix. If a is equal to 1, it represents complete LU decomposition. We can adjust the parameter a to control the direct method or iterative method strength. Therefore, we can dynamically choose the a from 0 to 1 to increase the speed of the solutions and ensure the accuracy of the solutions. 3. The equivalent-circuit model development In the past, we use Newton–Raphson [5] and complete LU method in device simulation. Usually, Poisson’s and continuity equations govern the semiconductor behavior. Most of the existing device simulations are based on the drift-diffusion (DD) description of carrier transport, and employ specialized techniques to obtain the one, two, or three-dimensional solutions in time domain. The carrier transport in semiconductor is described by three coupled partial differential equations, namely, the Poisson equation, the electron continuity equation and hole equation [6,7] as follows: q r2 u ¼ ½p n þ NDþ NA ; ð1Þ e on 1 ¼ r ~ J n R; ot q
ð2Þ
op 1 ¼ r ~ J p R: ot q
ð3Þ
For one-dimensional device simulation, a device can be partitioned into n 1 elements and n nodes. Fig. 2 shows the one-dimensional device’s equivalent-circuit model [8]. With the equivalent circuit approach, the simulated device can be replaced by a circuit representation. The number of unknown variables will be 3n by using a circuit simulator. It can be seen that each grid point is represented by three circuit nodes, which includes the electrostatic potential and the electron quasiFermi potential and the hole quasi-Fermi potential. First of all, the box-integration method [9] based on element by element is used to discrete Poisson’s equation. The element-by-element method is better for computer simulation than the node-by-node method. For the ith element in Fig. 1(a), Poisson’s equation can be rewritten as ui uiþ1 hi eA þ qðn p NDþ þ NA Þi A ¼ 0; ð4Þ hi 2 where A is the cross area.
J.-F. Dai et al. / Solid-State Electronics 48 (2004) 1181–1188
2
3 ofu o/p 7 " # 7 Duk ofun 7 k 7 D/n o/p 7 D/kp 3N 1 7 ofup 5 o/p 3N 3N 3 k fu ðu ; /kn ; /kp Þ ¼ 4 fun ðuk ; /kn ; /kp Þ 5 ; fup ðuk ; /kn ; /kp Þ 3N 1
ofu 6 ou 6 6 ofun 6 6 ou 6 4 ofup ou 2
1183
ofu o/n ofun o/n ofup o/n
ð8Þ
and
Fig. 1. One-dimensional equivalent-circuit model for semiconductor device of the CM: (a) ith element in one-dimensional simulation; (b) equivalent-circuit for Poisson’s equation; (c) circuit for electron continuity equation; (d) circuit for hole continuity equation.
Eq. (4) can be simplified as Iu1 þ Iu2 ¼ 0;
ð5Þ
where Iu1
eA ¼ ðui uiþ1 Þ; hi
Iu2 ¼ qðn p NDþ þ NA Þi
ð6Þ hi A: 2
ð7Þ
Similarly, we can obtain the equivalent-circuits for the electron continuity equation and the hole continuity Eq. [4]. We use LU method in 1D semiconductor device simulation. The matrix equations Ax ¼ b can be solved by Newton–Raphson. The Newton–Raphson method is written as follows:
ukþ1 ¼ uk þ Duk ;
ð9Þ
¼ /kn þ D/kn ; /kþ1 n
ð10Þ
¼ /kp þ D/kp : /kþ1 p
ð11Þ
If Duk , D/kn and D/kp are close to zero, the solution u, /n , /p will be obtained at the same time. The dimension of matrix A is 3N 3N . Therefore, in the conventional CM with 3N simultaneous equations, 3N 3N memory space is required for A in solving matrix equation Ax ¼ b. It spends much memory space by using the conventional CM. If we solve the potential u, /n , /p respectively, the matrix must be modified by Gummel’s method [10]. The Newton–Raphson method for solving the Poisson’s equation is written as follows: 2 3 ofu1 ofu1 ofu1 ofu1 2 3 Du1 6 ou ou2 ou3 oun 7 6 1 7 6 7 6 7 6 Du2 7 .. 7 .. .. 6 .. 6 7 . 6 . . 7 . . 4 .. 5 6 7 4 ofum ofum ofum 5 ofum Dum 3N 1 ou1 ou2 ou3 oum N N 2 3 fu1 6 fu2 7 6 7 ¼ 6 . 7 ; 4 .. 5 fum N 1 ð12Þ If Du, D/n and D/p are close to zero, then the potential u, /n and /p can be obtained respectively. The simplified DM equivalent-circuit model as shown in Fig. 2 can reduce the memory space effectively from 3N 3N to N N , nine times smaller and simplify the conventional equivalent-circuit model successfully by using a nonlinear resistor to replace the VCCS. The complicated Gummel’s method is automatically included in the DM. However, in mixed-level semiconductor device and circuit simulation, the boundary of the device’s terminal must be connected to a voltage source (not current) source or others) in the DM equivalent-circuit model with levelized incomplete LU factorization. The PDM first solves Poisson’s equation in the form:
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Fig. 3. The comparison of A matrix size for the CM, DM and the PDM.
ization mentioned above is discussed. For the aforementioned section, we use the DM and the PDM to solve the matrix equation Ax ¼ b, and they will reduce memory space effectively, as shown in Fig. 3. The large a will cause insufficient memory space and the program will be stopped if the CM is chosen for large-scale simulation, i.e., simulation with larger grid points cannot be done in a PC environment [2]. Furthermore, by comparing with mixed-level equivalent-circuit model, as shown in Fig. 4(a), if we use the CM to solve the Poisson equation, the Iuy , as indicated in Fig. 4(b), is written as follows: Fig. 2. One-dimensional equivalent-circuit model for semiconductor device of the DM: (a) ith element in one-dimensional simulation; (b) equivalent-circuit for Poisson’s equation; (c) circuit for electron continuity equation; (d) circuit for hole continuity equation.
ofu ou
½DuN 1 ¼ ½fu N 1 ;
ð13Þ
N N
Then it 2 of /n 6 o/n 6 6 4 of/p o/n
solves the two continuity equations in the form: of/n 3 o/p 7 f/n D/n 7 ¼ : ð14Þ 7 f/p 2N 1 D/p 2N 1 of/p 5 o/p
2N 2N
4. Simulation and comparison In this section, the implementation and simulation using the CM, DM and the PDM with L-ILU factor-
hi A 2 kþ1 kþ1 kþ1 ¼ f ðu ; /n ; /p Þ ¼ VCCS:
Iuy ¼ qðn p NDþ þ NA Þi
ð15Þ
The variables u, /n and /p are node variables, and Iuy will form a voltage-controlled current source (VCCS). Hence, the difficultly in programming and debugging will be enhanced. Therefore, if we solve the Poisson’s equation and continuity equations respectively, the Eq. (15) can be re-written as follows: Iuy ¼ qðn p NDþ þ NA Þi ¼ nonlinear resistor;
hi A ¼ f ðukþ1 ; /kn ; /kp Þ 2 ð16Þ
in Eq. (16), only u is unknown variable parameter, i.e., /n and /p are constants. Hence, a nonlinear resistor can be obtained in the PDM mixed-level circuit, as shown in Fig. 4(c), and the complexity of the equivalent-circuit will be simplified
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drastically, i.e., the complex VCCS will be simplified as grounded nonlinear resistance and this will enhance matrix diagonal dominance and help the convergence of program. Further, by comparing the memory consumption between the PDM and the DM, PDM needs more, but it can provide a direct link between device and external circuit, and solve the uncertainty of the electric-potential at the boundary of the device’s terminal in a mixed-level semiconductor device and circuit simulation. For instance, in Fig. 4(d), we separate the continuity equations and solve /n , /p respectively, i.e. DM, and we exchange the voltage source for current source. Thus, we cannot confirm what percentage of current is injected into the electron and the hole continuity equations. Therefore, to compare with the identical potential (Va ) in the PDM mixed-level circuit as shown in Fig. 4(c), we cannot ensure the potentials (Va ) at the boundary of the device’s terminal identical in the DM mixed-level circuit. Hence, the program does not work if the DM is chosen. We present the simulation of 2D MOSFET and CMOS devices to illustrate the capabilities and efficiency
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of the PDM equivalent-circuit model with L-ILU factorization. This device’s width is 1 lm, the thickness of gate oxide is 0.05 lm and the channel length is 1 lm. The doping concentration of the p-type substrate for the N-MOSFET device employed is NA ¼ 2 1016 cm3 and that for the n-type source and drain regions are both ND ¼ 1 1018 cm3 . The mobility of electron and hole are 1350 and 430 cm2 /V s ðlp Þ. The lifetime of electron and hole are 1 · 106 s (tn ) and 3 · 106 s (tp ). The device is partitioned into 21 · 13 rectangular grids. Fig. 5 shows the I–V curves for the MOSFET device evaluated by the CM, DM and the PDM with L-ILU factorization. The electric characteristic obtained by the PDM is in good agreement to that obtained by the CM and DM. Fig. 6 shows the dependence of the computation effort of the L-ILU factorization for the DM and the PDM with the lower truncation parameters. The CPU-time efficiency for the PDM is similar to the DM at the lower truncation parameter ‘‘a’’. A CMOS device is composed of P-MOSFET and N-MOSFET. In this study, both of the N-MOSFET and P-MOSFET have the same channel (0.6 lm),
Fig. 4. (a) The mixed-level semiconductor device and circuit schematic; (b) The CM mixed-level equivalent-circuit model; (c) The PDM mixed-level equivalent-circuit model; (d) The DM mixed-level equivalent-circuit model.
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Fig. 4 (continued)
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Fig. 5. The ID –VDS characteristic of 2D MOSFET for the CM, DM and the PDM.
Fig. 6. Dependence of the computation effort of the L-ILU method on the different truncation parameter.
gate oxide thickness (0.05 lm), impurity concentration of the substrate (2 · 1016 cm3 ) and source (or drain) regions (1 · 1018 cm3 ). However, the width is 2 lm for NMOS and the width is 6 lm for PMOS. The values of the ln , lp , tn , tp are all the same with the aforementioned ones. The external capacitance is 1
lF. For a CMOS, the requirement of memory space is more than a single MOSFET. This is the reason that why we need to develop more efficiency equivalent-circuit model with L-ILU factorization to save the consumption of memory space. Furthermore, at numerical simulation circumstance, the CMOS output
Fig. 7. (a) The mixed-level CMOS inverter circuit diagram; (b) The CMOS DC transfer characteristic and operating regions; (c) The 2D CMOS structure schematic; (d) A coefficient matrix pattern representation. ( ) diagonal entries, () off-diagonal entries.
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5. Conclusion
Fig. 8. The Vo =Vi transfer characteristic of 2D CMOS for the CM and the PDM.
terminal connects with a capacitance to help the convergence of the program. The capacitor ‘‘Cload ’’ is composed of internal parasitic capacitance and external capacitance. Internal parasitic capacitances include Cgd;n Cgd;p , Cdb;n , Cdb;p , Cgb . External capacitance is referred to the input capacitance of next level or the capacitance of interconnection line. Fig. 7(a) and (b) show a CMOS inverter circuit and its DC transfer characteristic and operating regions, respectively. The CMOS structure, as shown in Fig. 7(c), indicated that the channel differential resistances (ro1 and ro2 ) are very large when both of the N-MOSFET and the P-MOSFET are operating in saturation mode, i.e., the CMOS device is operating in c region as shown in Fig. 7(b). Therefore, the VOUT node is floatinglike and by employing Newton–Raphson method, the diagonal dominance will be reduced as shown in Fig. 7(d). Hence, the potentials of u, /n and /p for VOUT node will be uncertain and the program will be difficult to converge. Therefore, the CMOS output terminal needs to connect with a capacitance to help the program convergence. However, the mixed-level circuit will cause the potential (VOUT ) at the boundary of the device’s terminal being uncertain and the program will be stopped if the DM is chosen. Therefore, based on the aforementioned, we use the improved PDM equivalent circuit-model with L-ILU factorization for CMOS device simulation. It not only saves memory consumption but also can provide an effective matrix solver for mixed-level semiconductor device and circuit simulation. Fig. 8 shows the characteristics of the Vo /Vi transfer curves for the CMOS device evaluated by the CM and the PDM. The transfer characteristic obtained by the PDM is in good agreement to that obtained by the CM.
We present an improved equivalent-circuit model (PDM) to solve matrix equation Ax ¼ b which has various advantages over the CM and the DM. This method not only saves memory consumption but also simplifies the complex VCCS as grounded nonlinear resistor. It can enhance matrix diagonal dominance and help program convergence. Furthermore, the programming and debugging for the nonlinear resistor model are much easier than that for the VCCS model. The more important is that the PDM equivalent-circuit model overcomes the problem of the boundary at the device’s terminal. Otherwise, in the DM equivalent-circuit model, the device’s terminal must be connected to a voltage source since the other ones (current source or others) will cause the electric-potential at the boundary of the device’s terminal being uncertain. Therefore, it should pave the method to its widespread application in mixed-level semiconductor device and circuit simulation.
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