Solid-State Electronics 45 (2001) 1793±1798
Hall eect measurements in double-gate SOI MOSFETs A. Vandooren a,*, S. Cristoloveanu b, D. Flandre c, J.P. Colinge d a
Materials and Structures Laboratory, Motorola Digital DNA Labs, 3501 Ed. Bluestein Blvd., MD-K20, Austin TX 78721, USA Laboratoire de Physique des Composants a semiconducteurs (UMR 5531), ENSERG, BP257, 38016 Grenoble Cedex, France c Microelectronics Laboratory, Universite catholique de Louvain, Place du Levant 3, 1348 Louvain-La-Neuve, Belgium d Department of Electrical and Computer Engineering, University of California, Davis, CA 95616, USA
b
Received 20 November 2000; received in revised form 15 May 2001
Abstract The electron mobility and concentration in double-gate silicon-on-insulator (SOI) gate-all-around transistors is extracted by Hall eect measurements at room and liquid nitrogen temperature. The Hall mobility is compared with the drift mobility determined from the transconductance measurement of the devices in strong inversion. The results of this study indicate that the method based on ID =
gm 0:5 provides acceptable values for the drift mobility. The experiment reveals high carrier mobility dominated at room temperature by a phonons scattering mechanism and at low temperature by mixed scattering processes, with a predominance of the surface roughness scattering mechanism. No evidence was found for special transport mechanisms induced by volume inversion in relatively thick SOI ®lms. Ó 2001 Elsevier Science Ltd. All rights reserved. Keywords: Hall eect; Silicon-on-insulator technology; Mobility; Low temperature; Carrier transport; Double-gate MOSFET
1. Introduction Double-gate silicon-on-insulator (SOI) metal-oxidesemiconductor ®eld-eect transistors (MOSFETs), such as gate-all-around (GAA) [1], fully depleted lean-channel transistor (DELTA) [2], surrounding gate transistor (SGT) [3], or FinFET [4] structures, are considered as strong candidates for ultimate ultra-short MOSFETs. These devices bene®t from tremendous advantages: increased drain current and transconductance, reduced leakage currents, nearly ideal subthreshold swing, attenuated short-channel eects and improved scalability. The operation of thin-®lm double-gate transistors is based on the concept of volume inversion [5] according to which the minority carriers are no longer con®ned at
* Corresponding author. Tel.: +1-512-933-5170; fax: +1-512933-6330. E-mail address:
[email protected] (A. Vandooren).
the interfaces but spread out across the silicon ®lm. In the center of the ®lm, far from the interfaces, carriers have presumably a higher mobility. Recent measurements on 3-nm-thick SOI MOSFETs have shown a considerable gain in ®eld-eect mobility for operation in double-gate mode as compared with single-gate mode [6]. It was speculated that the improvement is due to carriers ¯owing in the middle of the ®lm, where they experience less surface roughness scattering events and a much lower vertical ®eld. Although the mobility issue is very critical for the future of double-gate MOSFETs, there has been no attempt so far to measure the carrier mobility accurately, by a direct technique, which does not rely on the transconductance. In this paper, the electron mobility is measured, for the ®rst time, by Hall eect on customized double-gate structures. The variation of the Hall mobility and carrier concentration with gate voltage and vertical ®eld is investigated at room and liquid nitrogen temperature. This method is also compared to conventional techniques for mobility extraction based on transistor characteristics.
0038-1101/01/$ - see front matter Ó 2001 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 0 1 ) 0 0 2 0 7 - 6
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2. Experiment Double-gate Hall structures were fabricated on UNIBONDâ wafers using the GAA process described in Ref. [1]. A cavity was formed underneath the silicon island and resulted in a free-standing silicon bridge which represents the transistor body. The thicknesses of the Si ®lm and gate oxide are tSi 81 nm and tox 30 nm, respectively. The ®lm doping is p-type and approximately homogeneous (NA 1017 cm 3 ). The con®guration of our ®ve-terminal GAA MOS-Hall structure is represented in Fig. 1. It consists of an enhancementmode, fully depleted, n-channel MOSFET with a sur-
rounding gate. Besides the two n end contacts (source and drain), there are two lateral n contacts used for Hall voltage measurements. The Hall contacts connect the active silicon layer through the polysilicon gate material and the gate oxide. Due to the gate extension in the transverse direction, the Hall contacts are actually the series combination of a n diusion resistor, a regular enhancement-mode (n pn ) SOI transistor, and an enhancement-mode GAA transistor. A single gate electrode controls the entire structure. In order to avoid a geometric magnetoresistance effect (i.e., contact-induced local short-cuts) to develop, the aspect ratio L=W must be kept as large as possible and the Hall contact size has to be minimized [7,8]. Due to the formation of the cavity underneath the Si island, the length of GAA transistors cannot be increased above 3±4 lm. This is why the length and width of the HallGAA structure were chosen equal to L 4 lm and W 0:5 lm, respectively. The Hall contact is 0.5 lm wide, which is much smaller than the device length. The Hall eect measurement consists in supplying a current ID between source and drain, while a magnetic ®eld B is applied perpendicular to the surface. The carriers tend to be de¯ected by the Lorentz force. Since no current is allowed in the transversal direction, a Hall electric ®eld develops to oppose the Lorentz force. The device is operated with a low drain bias (VD 50±250 mV) in order to keep the channel properties constant along the device. The Hall eect measurement is performed as a function of magnetic ®eld (B 0:6±1:1 T) and gate voltage from moderate to strong inversion. In weak inversion, the Hall signal suers from noise, while in very strong inversion, the in-depth distribution of minority carriers is highly inhomogeneous and most of the electrons ¯ow near the two interfaces. The Hall voltage measured between the transverse contacts is expressed as a function of drain voltage or current: VH
lH WVDS B RH BI L tSi
1
The Hall mobility lH and Hall coecient RH are respectively related to the electron drift mobility lD and carrier concentration n by lH rH lD
Fig. 1. Top-view (a) schematic and (b) photograph of the GAA Hall-MOS structure.
RH
rH qn
2
The Hall scattering factor rH reduces to 1 under the assumption of monokinetic carriers. In general, rH re¯ects the carrier energy distribution and the scattering mechanism [7]. At room and higher temperature, the Hall scattering factor is governed by collisions with acoustic phonons (rH 1:18). At low temperature, rH is dominated by ionized impurities (rH 1:93). Other mechanisms may come into play, including surface roughness
A. Vandooren et al. / Solid-State Electronics 45 (2001) 1793±1798
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scattering at high gate voltage, optical and surface phonons, stress-induced piezoelectric eect, etc. The in¯uence of the magnetoresistance and contact misalignment was eliminated by performing measurements for opposite directions of the applied magnetic ®eld. Averaging the measurement for B VH
VH
B
VH
B 2
3
yields an accurate value of the Hall voltage [8]. Further averaging by current inversion ID was performed as an additional precaution.
3. Results 3.1. Mobility The Hall voltage varies linearly with electric ®eld (or drain voltage, Fig. 2a) and magnetic ®eld (Fig. 2b). The Hall mobility is calculated from Eq. (1). Fig. 3 shows lH values, at room and liquid nitrogen temperature, as a function of the gate bias. The Hall mobility decreases in strong inversion, where the vertical ®eld increases and accentuates the electron con®nement near the interfaces. On the other hand, the Hall mobility is improved at low temperature by about 35% to 50%. This is less than expected from pure acoustic phonon scattering (lH T 1:5 ). In order to compare Hall and drift mobilities, we have used the drain current ID
VG and transconductance gm
VG characteristics of the GAA transistor at B 0. In the linear region of operation, we have: gm
lo Cox VDS 2W =L 1 h
VG
VT 2
4
and lD
lo 1 h
VG
VT
5
where lo is the maximum (nominal) mobility and h is the mobility reduction factor in strong inversion, which includes the in¯uence of series resistances. The idea is to extract lo and h and then reconstruct lD
VG . The mobility attenuation factor is obtained from ID 1 1
6 h gm
VG VT VG VT Three methods have been used to determine the intrinsic mobility lo : (1) Measurement of the transconductance peak (method 1 in Fig. 3). This popular method ignores the denominator of Eq. (4). The theoretical peak (for VG VT ) cannot be measured. In practice, the transconduc-
Fig. 2. Evolution of the Hall voltage as a function of (a) drain voltage and (b) magnetic ®eld, at room temperature and VG 2:5 V.
tance is actually maximum for a gate voltage that exceeds VT by about 0.2 V; this induces a severe underestimation of lo . (2) First-order development of gm (method 2 in Fig. 3). The transconductance can be linearized using gm lo 1 2h
VG VT , for easy extraction of lo and h. This approximation is inaccurate when h is large (which is the case in our devices: h 0:05 V 1 at 300 K and h 1:1 V 1 at 300 K) and leads to an overestimation of lo at high VG . At least second-order terms should be taken into account. (3) Calculating the ratio ID =
gm 0:5 (method 3 in Fig. 3). This method allows eliminating the coecient h[7,9]:
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Fig. 3. Drift mobility and Hall mobility versus gate voltage for n-channel transistors. (( ) method 1, ( - -) method 2, (Ð) method 3, (j) Hall as described in the text) at T 300 and 77 K.
r ID lo Cox WVDS
VG p L gm
VT
7
The maximum, nominal mobility (lo 1150 cm2 /V s at 300 K and lo 3000 cm2 /V s at 77 K) is determined from the slope of ID =
gm 0:5 . The horizontal intercept provides the threshold voltage: VT 0:15 V at 300 K and VT 0:4 V at 77 K. A very good agreement is obtained between the variations with gate voltage of the Hall mobility and the drift mobility, calculated using Eq. (5) and the lo value extracted from Eq. (7). In strong inversion, both mobilities decrease with gate bias (Fig. 3) due to the increase of vertical electric ®eld, which tends to `push' the electrons closer to the interfaces; this situation is similar in GAA and regular MOS transistors. At room temperature, the drift mobility is excellent (varying from 800 to 500 cm2 /V s for 1 < VG < 2:5 V and a doping concentration of 1017 cm 3 ) compared to values published in the literature for thin ®lm SOI MOSFETs [1,7]. This con®rms the very good quality of the top silicon ®lm in UNIBONDâ wafers, which becomes equivalent to that of bulk silicon. The ratio lH =lD 1:1±1:2 suggests a strong in¯uence of acoustic phonon scattering that is con®rmed by the temperature dependence of the mobility lD (Fig. 4). As the temperature is lowered, the mobility increases quasi-linearly. There is no trace of Coulomb scattering, which would force the mobility to drop (lD T 1:5 ) and the ratio lH =lD to increase to 1.93. Instead, in our experiment the ratio lH =lD tends to decrease to unity at low temperature. Two reasons can be invoked. Firstly, a mixed scattering mechanism occurs involving mainly phonons and surface roughness. From our experimental
Fig. 4. Temperature evolution of the drift and Hall mobility at VG 2 V.
viewpoint, the latter mechanism looks realistic because it is characterized by a weak temperature dependence (lD T 1=3 ) [10] and a scattering coecient close to unity. Second, the in-depth distributions of carrier mobility and concentration are inhomogeneous, such that lH and lD should be averaged across the ®lm thickness: R n
zl
z dz lD R D
8 n
z dz R lH
n
zlD
zlH
z dz R n
zlD
z dz
9
z being the depth axis. Fig. 5 shows the in-depth carrier pro®les simulated using S I L V A C O software. The silicon ®lm is too thick (80 nm) for enabling signi®cant volume inversion or quantum eects. At room temperature, the middle of the ®lm is only marginally inverted. At 77 K, the double-gate device behaves as the simple superposition of independent front and back channels. The minority carriers are concentrated near the two interfaces, which reinforces the scenario of enhanced surface roughness scattering. The drift and Hall mobilities are plotted in Fig. 6 as a function of the eective electric ®eld. The eective electric ®eld was computed, at dierent gate voltages, using S I L V A C O simulations, according to its de®nition [11]: R n
zjE
zj dz
10 Eeff R n
z dz where n
z is the inversion charge concentration and E
z is the local electric ®eld. Since both the carrier pro®le (Fig. 5) and the threshold voltage are temperature dependent, the eective ®elds, corresponding to a ®xed VG bias, are dierent at 300 and 77 K. This results
A. Vandooren et al. / Solid-State Electronics 45 (2001) 1793±1798
Fig. 5. Electron concentration distributions across the silicon ®lm at VG 1:5, 2 and 2.5 V obtained by S I L V A C O simulations.
Fig. 7. Variation of the electron concentration in the silicon active layer versus gate voltage at 300 and 77 K according to the two methods described by Hall eect, Eq. (2) (j, ) and Eq. (11) (Ð).
Qinv 2Cox
VG
Fig. 6. Hall and drift mobility at room and liquid nitrogen temperature as a function of eective electric ®eld.
in slightly dierent ranges of eective ®eld in Fig. 6. The mobility curves in Fig. 6 actually follow the pattern of conventional single-gate MOSFETs: the ®eld-dependence of the mobility falls within the ``universal'' mobility law and is stronger at low temperature [10,11].
3.2. Minority carrier concentration The electron concentration n in the active silicon ®lm was deduced from the Hall measurements using Eq. (2). The average concentration of minority carriers can also be derived from the MOSFET inversion charge:
1797
VT qtSi n
11
The factor 2 present in the Qinv term takes into account the presence of two interfaces in double-gate structures. The electron concentration, determined by these two methods at room and liquid nitrogen temperature, is illustrated in Fig. 7. The overall agreement between Hall eect and MOSFET measurements is good in strong inversion and con®rms the necessity of a pre-factor 2Cox in Eq. (11). We did not expect a perfect ®t because (i) the carrier pro®les are inhomogeneous (Fig. 5), (ii) the average values of n in Eqs (2) and (11) are calculated by dierent integrals, and (iii) there are small ¯uctuations (5±10%) in Hall eect measurements. Parallel variations of the carrier concentration with gate voltage are obtained at 77 and 300 K. The shift is due to the increase in threshold voltage at low temperature, which is rather small (DVT 0:25 V or DVT =DT 1 mV/K) in fully-depleted GAA MOSFETs.
4. Conclusion For the ®rst time, the minority carrier mobility and concentration were independently measured by Hall effect in double-gate SOI devices. Since Hall eect results are accurate and assumption-free, we could verify the mobility models in double-gate SOI MOSFETs. It was found that only the ID =
gm 0:5 method provides acceptable values for the drift mobility. These measurements have revealed several aspects of interest for double-gate MOSFETs:
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(1) High carrier mobility, dominated at room temperature by phonons and at low temperature by mixed scattering processes. (2) Relatively weak temperature dependence of the carrier concentration and mobility. (3) No evidence was found for special transport mechanisms induced by volume inversion in relatively thick SOI ®lms. We have demonstrated the feasibility of double-gate Hall devices. Such experiments deserve to be reproduced in ultra-thin (<10 nm) devices, where the volume inversion is much stronger and controlled by quantum eects. This is the only reasonable solution for understanding the mobility behavior in DG-MOSFETs.
Acknowledgements The authors wish to thank the Microelectronics Laboratory in Louvain-La-Neuve, Belgium for devices processing. The authors acknowledge J. Shell and T. Cunningham of the Jet Propulsion Laboratory, Pasadena, for assistance with low temperature and Hall effects measurements. Denis Flandre is Senior Research Associate of FNRS (Belgium).
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