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Wafer level measurements and numerical analysis of self-heating phenomena in nano-scale SOI MOSFETs
Microelectronics Reliability 63 (2016) 90–96
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Microelectronics Reliability journal homepage: www.elsevier.com/locate/mr
Wafer level measurements and numerical analysis of self-heating phenomena in nano-scale SOI MOSFETs Giacomo Garegnani, Vincent Fiori ⁎, Gilles Gouget, Frederic Monsieur, Clement Tavernier STMicroelectronics, 850 rue Jean Monnet, F-38926 Crolles, France
a r t i c l e
i n f o
Article history: Received 9 November 2015 Received in revised form 4 March 2016 Accepted 5 March 2016 Available online 8 June 2016 Keywords: Nano-scale MOSFETs Self-heating Temperature measurements FEM simulations Correlation analysis Thermal sensors
a b s t r a c t We present an experimental technique and a Finite Element thermal simulation for the determination of the temperature elevation in Silicon on Insulator (SOI) MOSFETs due to self-heating. We evaluate the temperature elevation in two steps, as we calibrate the gate resistance over temperature with the transistor at off state at a first stage, and then we deduce the temperature elevation through gate resistance measurements. We simulate the self-heating phenomena in a Finite Elements Method (FEM) environment, both with 2D and 3D models. In order to set up the simulations, we weight the effects of several parameters, such as thermal material properties, the modeling of heat generation and a careful setting of boundary conditions. We present typical temperature fields and local heat fluxes, thus giving concrete indications for solving thermal reliability issues. Simulation results show temperature elevations up to approximately 120 K in the hot spot, 70 K in the gate and 7 K in the Back End of Line (BEoL). The 3D model gives results that are satisfying over the whole set of MOSFETs we consider in this work. Temperature elevation strongly depends on physical dimensions, where transistors endowed with shorter gates suffer from more severe self-heating. We propose a simplified model based on geometrical parameters that predict maximum and gate temperatures, obtaining satisfying results. Since correlation with measurements confirms the correctness of our model, we believe that our simulations could be a useful tool to determine accurate reliability rules and in a context of thermal aware design. © 2016 Published by Elsevier Ltd.
1. Introduction Downscaling of MOSFETs characteristic size to 28 nm leads to severe self-heating issues [1,2]. Moreover, the Buried Oxide (BOX) in SOI technology guarantees good electric performances but has the drawback of increasing thermal isolation of the active region, causing a more relevant temperature increase than in bulk transistors [3–6]. Several studies have been published about the self-heating of nanometer-scaled transistors, presenting Technology Computer Aided Design (TCAD) and molecular dynamics simulations that allow predicting the temperature distribution at a local level. Other studies exploit similar approaches to predict the temperature of FinFETs [2], for which the thermal confinement is a critical issue. The common features of those publications are exhaustive analyses of materials' thermal properties [3,7,8], placement of the heat source [1,6], boundary condition settings [4] and heat flux through metal lines in the Back End of Line (BEoL) [9]. Even though a wide range of sophisticated electro-thermal coupled simulations have been built [3,6], in order to produce accurate simulations of thermal phenomena in SOI MOSFETs, we believe that a real effort of correlating simulation results with experimental measures at local level is currently ⁎ Corresponding author. E-mail address: vincent.fi[email protected] (V. Fiori).
http://dx.doi.org/10.1016/j.microrel.2016.03.007 0026-2714/© 2016 Published by Elsevier Ltd.
lacking in the self-heating literature. It is therefore our purpose to measure experimentally the temperature elevation in SOI MOSFETs featured by different physical dimensions. In particular, we test transistors with four different gate lengths L (30, 60, 90, 200 nm) and four different depths of the active zone W (0.5, 2, 5, 10 μm) combining those measures in all possible manners, thus obtaining results for sixteen different structures. In this way, a complete understanding of the dependence of self-heating phenomena on the physical dimension of the transistor is retrieved. Then, we set up a FEM steady-state thermal simulation to compute the temperature field in the whole structure. Besides computing the location and value of the hot spot of the MOSFET, the simulation results allow to predict the heat fluxes in a wafer level configuration, as well as the temperature gradients. Moreover, we extract the value of the average temperature of the gate in order to verify the correlation of FEM results with measurements, thus validating our analysis. Since the correlation of simulations and measurements is promising, we believe that the model we present in this work could be exploited as a tool for careful material selection and in general for thermal aware design, eventually improving overall thermal reliability of SOI devices. We will base our future work on this simulation, verifying the thermal behavior of MOSFETs in different packaging techniques, such as flip-chip and wire bonding, as well as the impact of the BOX thickness and the temperature distribution in metal interconnects. The structure of our
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work is the following. In Section 2, the experimental procedure is presented with a detailed description of the structure calibration and the probing technique. We explain in Section 3 the 2D and 3D FEM analyses we perform, introducing all the physical phenomena and modeling parameters we take into account in order to set up the simulation. In Section 4, simulation assumptions are validated. Besides, in order to account for the heat loss induced by the imperfect contact conditions between wafer bottom and measurement equipment, we switch the corresponding boundary conditions from fixed temperature to an approximated heat transfer coefficient. Then we present and discuss the results of measurements and simulations in Section 5, finally drawing our conclusions in Section 6. 2. Measurement procedure The aim of the experimental procedure is to measure the average temperature elevation of the gate due to the self-heating effect. The structures we use for performing measurements are MOS transistors with double gate access (Fig. 1). A two-step procedure is employed [10]. Firstly, a calibration is performed in order to determine the gate electrical resistance as a function of temperature. The gate resistance is measured with the transistor at off state imposing different substrate temperatures with a variable temperature chuck. The results we obtain are clearly linear (Fig. 2), so we can express the gate electrical resistance at off state Rg,min as Rg; min ¼ f ðT Þ ¼ R0 þ Rt T; where coefficients R0 , Rt are determined empirically. R0 and Rt depend on the geometry of the transistor, and vary in the range [250, 3290] Ω and [0.3,10.5] Ω/K respectively. In the second step we measure the gate resistance Rg , max at on state, i.e., Vd = Vdd = 1 V , Vs = 0. We then exploit the calibration results for deducing the gate average temperature by ΔT ¼
Rg; max −Rg; min Rt
Fig. 2. Electrical resistance of the gate with respect to temperature at off state.
Low-k interconnects. These preliminary investigations allow determining simulation detail requirements. Then, we include the key parameters in order to set up the steady-state FEM models, both physical and simulation-related. In the following, we explain the main assumptions on which we base our model. We present in Section 4 the validation of our hypotheses. 3.1. Geometrical description and model-size-reduction strategy We build the geometry representing the studied structure as follows: • the active region is precisely described. In particular, we include in the model: source/drain, channel, gate and gate oxide, BOX, nitride and oxide spacers; • the STI and substrate are precisely modeled. • above the active region, the conformal Contact-Etching Stop Layer (CESL) and Pre-Metal Dielectrics (PMD) are discretized; • finally, the 10 metal layers BEoL, having a 7.8 μm thick and representing low-k and SiO2 based dielectrics, oxide and nitride passivations, is modeled using a stack of uniform layers;
:
3. Finite Elements modeling Our purpose is to reproduce in a simulation environment the selfheating phenomena in SOI MOSFETs. The inputs of the simulation are the physical dimensions of the transistor, the sample environment and the dissipated power; the outputs are the average temperature in the gate, taken for correlation purposes, the maximum temperature in the channel, as well as the temperature field, heat fluxes and temperature gradients in the whole structure. In order to build an accurate and predictive model while keeping reasonable numerical resource needs, we weighted the effects of several factors, such as model size-reduction and meshing techniques, boundary conditions, material properties, modeling of the heat source, impact of tungsten contacts and BEoL Cu/
Fig. 1. Scheme of the structures used for measurements.
In order to obtain a lighter simulation, both in a meshing and therefore in a solution processes, we decide to reduce the size of the model. Firstly, we reduce the substrate thickness, as building the mesh of the whole substrate would imply the creation of an enormous amount of elements. Thus, we replace a portion of the substrate with a thermal resistance, which is then connected to the heat sink. We assign to the thermal resistance thickness the arbitrary value of 1 μm, and compute its thermal conductivity value using the following formula krth ¼
1 ∙kSi ; t sub;th −t sub; mod
where tsub,th is the theoretical thickness of the substrate, tsub,mod is the thickness of the substrate in the model and kSi is the conductivity of bulk Si. In particular, the value of tsub , mod has to be large enough to allow the heat fluxes being unidirectional towards the bottom of the structure in order to conserve the simulation correctness. Moreover, in order to mimic an isolated heating transistor it is necessary that the model is wide enough to allow the entire horizontal dissipation of the generated heat. For the 2D simulation, it is possible to build the mesh of the whole model. The width has been set to 200 μm to each side of the transistor, as once this measure is reached, the temperature elevation is stable. For the 3D model, it is not practical to build a complete mesh as the number of elements grows dramatically. Therefore, vertical layers with a high conductivity value (1012 W/m K in the simulations) are juxtaposed laterally to a portion of the structure, in order to allow the whole heat transfer to take place. These vertical layers do not represent physical parts of the considered structure and are included in the model only for reducing the computational time. Moreover, they are
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magnitude lower than the correspondent bulk values, the temperature elevation could be largely underestimated exploiting the latter. 3.4. Boundary conditions The choice of boundary conditions is a crucial assumption of the simulation setting [4,12]. In particular, the modeling of the heat sink is delicate, as an imposed temperature boundary condition does not seem a physically adapted choice due to interface thermal resistance between the silicon wafer and the equipment chuck. Our final choices are the following:
Fig. 3. Mesh of the 2D model, zoom on the MOSFET region. In this case, L = 30 nm.
sufficiently far from the active region not to spoil the validity of the solution in the neighborhood of the transistor. A validation of this procedure of model reduction is shown in Section 4.1.
• Convective boundary condition at the top of the BEoL, with a heat transfer coefficient of 30 W/m2 K, adapted for natural convection in micrometer structures [12] together with the environment measures. • Adiabatic boundary conditions at lateral walls, though simulating a periodic structure • Convective boundary conditions at the bottom of the Silicon substrate, with a coefficient determined minimizing the correlation error [13]
3.5. Heat generation modeling
The structures we consider have components whose sizes vary between a few nanometers and several microns. It is therefore important to adapt the mesh to the corresponding component, trying in the meantime to avoid fast variations in element sizes, which would result in badly shaped elements and eventually in inaccurate solutions. Hence, we build the mesh progressively from the smallest parts, i.e., the MOSFET components, to the biggest ones, i.e., the Si substrate and the BEoL layers. The final mesh for both 2D and 3D simulations is depicted in Figs. 3 and 4.
The model we present in this work is exclusively thermal; hence, an appropriate modeling of heat generation is required for claiming the correctness of results. It has been reported in the literature [1,6] that power dissipation due to Joule effect takes mainly place in the channel extension at the drain side. We exploit the measurements to obtain the numerical values of generated heat using the classical Joule law (Q= V ∙ J). We choose to model heat dissipation as a uniform source distributed either in the whole channel or only in its half nearest to the drain. If results are not influenced by these two different choices, considering the whole channel as a heat source would lead to simulate only one fourth of the structure for symmetry reasons, thus allowing a computationally cheaper FEM simulation.
3.3. Material properties
3.6. Back End of Line
Thin films of semiconductors have to be treated carefully in a thermal setting, as their thermal conductivity values are sensibly lower than the corresponding bulk ones [1–3,7,8,11]. In layers characterized by thicknesses in the nanometer scale, boundary scattering phenomena are not negligible since phonon mean free path is in the same order of magnitude of the thickness itself. Hence, in order to study self-heating of nano-scale transistors solving the classic Fourier equation, corrected values of thermal conductivities have to be exploited. The values we used are taken from the literature, where experimental measures [7,8, 11] and analytical models [1,3], are presented. The obtained results are reported in Table 1. Since corrected values are even one order of
The temperature field in the BEoL is a value of interest in a selfheating contest [9]. Since in this work we focus on a wafer level configuration, we believe that the heat flux is directed towards the bottom heat sink. Therefore, the impact on the value of temperature of interconnects in the BEoL could be negligible, especially at a local level. Hence, we believe that a full description of the BEoL is not necessary, and therefore a stack of uniform layers accounts for the BEoL, as described in Section 3.1. We set two different models in order to verify the impact of metal interconnects, i.e., either we do not modify the conductivity values of any layers or we modify these values by averaging them with the thermal conductivity of copper with a 20% weight.
3.2. Meshing technique
Fig. 4. Mesh of the 3D model, top view of MOSFET and STI and perspective zoom on the transistor's components. Top layers are hidden for viewing purposes. In this case, L = 90 nm; W = 2 μm.
G. Garegnani et al. / Microelectronics Reliability 63 (2016) 90–96 Table 1 Effective values of thermal conductivity for semiconductors thin films. Material
Thickness
Thermal conductivity (W/m K)
Silicon Silicon Silicon SiO2 SiO2 SiO2 PolySilicon PolySilicon Si nitride Si nitride
Bulk 20 nm 10 nm Bulk 25 nm 2 nm Bulk 30–200 nm Bulk 10 nm
140 20 13 1.4 0.7 0.3 105 30 30 3
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with respect to measurements is convex (Fig. 6), so we can find a global minimum and choose therefore an optimal heat transfer coefficient, which finally is h = 3.566 ∙ 107 W/m2K. The value of h deduced with the procedure above is high, but not equivalent to imposing a fixed temperature at the bottom of the substrate. We perform simulations of all structures imposing Dirichlet condition, deducing an average reduction of 12% of the gate temperature and an increase in the error with measurements of approximately 70%. Therefore, we believe that the convective boundary conditions with h = 3.566 ∙ 107 W/m2K is more adapted for representing the contact between the substrate and the isothermal chuck.
3.7. Contacts
4.3. Heat generation modeling
We are interested in understanding the impact of the number of contacts on simulation results. Since tungsten has a thermal conductivity approximately two order of magnitude higher than dielectrics, it is reasonable to think that contacts offer a path to heat transfer, decreasing the temperature in the MOSFET in a non-negligible manner. Hence, we probe the temperature elevation and the dissipated power in three structures endowed with the same physical dimensions but with a different number of contacts.
We plot in Fig. 7 the results produced in the reference case by the 2D simulation using either a source distributed over the whole channel (ALLCH) or on its half at the drain side (NEXTDR). Let us remark that these two different choices lead to sensibly different results for the value of maximum temperature, but that there is practically no difference in the gate temperature. Since our correlation effort with measurements regards the average gate temperature, in the 3D model we consider the whole channel as the heat-generating region. In this way, we can exploit the structure's symmetry and set up a lighter simulation, for which the correlation with measurements is still valid. Thus, the results given by the 3D simulation are accurate only for the gate average temperature, as the hot-spot temperature in the channel is systematically underestimated due to a lower density of generated heat. Furthermore, despite the fact temperature peak differences depend on transistor layout, in all the tested configurations the mismatch resulting from the use of a symmetric power source is in the range of the correlation error. Hence, keeping in mind the above mentioned limitations and since peak temperature is a critical reliability concern, we complement the analysis on the gate region with some insights regarding the active area as well.
4. Validation of assumptions 4.1. Model size reduction We compute the solution in a reference case when the entire structure is modeled and when we apply the reduction technique explained in Section 3.1. We extract the temperature profile in the z-direction (i.e., W-wise) from the hot spot to the outer border of the STI to verify whether the lateral layers we juxtapose to the model spoil the local correctness of the solution. Results (Fig. 5) show that this technique does not spoil the correctness of results, as the temperature profiles locally coincide. 4.2. Bottom boundary condition
4.4. Back End of Line
In order to determine the heat transfer coefficient for the bottom convective boundary condition we exploit the following strategy. We perform the simulations for all the physical dimensions of interest using three different values of heat transfer coefficient. We compute the average relative error with respect to measures for each coefficient. Then, we perform a quadratic regression of the error using the heat transfer coefficient as only parameter, finally choosing the point that reaches the global the minimum. As we expected, the average error
The gate temperature results given by the two different choices explained in Section 3.6 differ in average of 6%. We shall then conclude that at wafer level a full description of the BEoL is not fundamental whereas it would be necessary, for example, in a flip-chip configuration, where the heat sink is at the top of the BEoL. The results we present in the following refer to the case in which a 20% of copper is considered for the thermal properties of the BEoL.
Fig. 5. Comparison between the temperature profile in z-direction (i.e., W-wise) of the reduced model (blue line) and the full model (pink line).
Fig. 6. Heat transfer coefficient determination: blue points represent the error on measurements, the dashed line is the quadratic interpolation used to determine the theoretical minimum.
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Fig. 7. Influence on the maximum temperature (TMAX) and on the gate average temperature (TMG) of the heat generation assumption (ALLCH = the entire channel is considered uniformly as the region dissipating power, NEXTDR = only the half of the channel next to the drain side is considered as the region dissipating power). The results of gate average temperature are not sensibly influenced by this choice. Results are divided with respect to the value of W and averaged over L.
4.5. Contacts We measure the temperature elevation in three structures endowed with a different number of contacts as explained in Section 3.7. A higher number of contacts leads to a higher power dissipation in the MOSFET, even though geometrical features are kept constant. Therefore, in order to verify the impact of contacts, we normalize the average temperature elevation in the gate with the power dissipation obtaining a value of thermal resistance Rth. The variation of Rth is negligible (Table 2), thus it is possible to deduce that contacts do not have an impact on selfheating phenomena at wafer level. Therefore, contacts are not included in our FEM simulation environment, as they do not allow a sensible heat discharge towards the lower part of the BEoL.
5. Results and discussion 5.1. Typical results A typical temperature field in the MOSFET is shown in Fig. 8. We cut the MOSFET along its two symmetry planes, so that the temperature in
the internal part of the channel is clearly visible. A strong attenuation of temperature takes place even at a local level. In fact, temperature decreases rapidly inside the BOX, thus confirming that SOI architectures suffer of higher heat isolation than bulk transistors. Even though the BOX causes thermal confinement below the heating component, at a global level the heat flux is mainly directed towards the heat sink at the bottom of the substrate (Fig. 9), meaning that the BEoL does not allow a heat discharge towards the top of the structure. In particular, the heat generated in the channel diffuses mainly upwards towards the gate, with a lateral component that is strongly decreasing with reference to the transistor length L (Table 3). This is representative of the heat confinement caused by the BOX, as globally heat discharge takes place in the heat sink at the bottom of the substrate. Therefore, the temperature in the BEoL is almost constant, and we verified a temperature elevation in the range of 2–8 K, depending on the physical dimensions, that is reached at approximately 2 μm above the active zone. Let us underline that this analysis of thermal fluxes is valid at wafer level, as, for example, a flip-chip configuration would imply a more relevant heat flux through the BEoL. In this case, we claim that the thermal
Table 2 Measurements and 3D simulation results of structures endowed with different numbers of contacts. W (μm)
L (μm)
POW (W)
Measures Contacts (K)
5 5 5
0.03 0.03 0.03
3.17E−03 4 4.16E−03 20 4.27E−03 MAX
57.3 77.1 79.5
Rth (K/W)
Rth relative difference
18,089 18,545 18,619
– 2.52% 2.93%
Fig. 9. Heat flux in the transistor neighborhood, vertical section of 3D simulation. In this case, L = 60 nm; W = 2 μm.
Table 3 Local heat fluxes in the three main directions normalized over the whole dissipated power. Direction labels are graphically explained in Fig. 9.
Fig. 8. Temperature field in the MOSFET region. In this case, L = 60 nm; W = 2 μm.
L (μm)\direction
Down
Up
Lateral
0.03 0.06 0.09 0.2
21% 23% 25% 31%
34% 45% 52% 57%
46% 32% 23% 12%
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Table 4 Error of 2D simulation results over measures. W\L (μm)
0.03
0.06
0.09
0.2
Average
0.5 2 5 10 Average
42% 1% 9% 8% 15%
92% 2% 4% 1% 25%
101% 26% 2% 4% 33%
142% 62% 20% 12% 59%
94% 22% 9% 6% 33%
confinement provided by the BOX would be less severe, as contacts and metal lines would provide a path for heat flux towards the heat sink, placed at the top of the BEoL. Fig. 11. Scatter plot of 3D simulation results over measures. The different measures of W are represented with different colors and the values of L are directly reported on the plot.
5.2. Results discussion 5.2.1. Correlation of results In Tables 4 and 5, we report the relative error of simulation results over measurements. In particular, 2D simulations fail to identify the temperature elevation in case W is small (Table 4). In fact, in this case a non-negligible part of the gate is not laying on the active region but on the STI, where a strong decrease of temperature takes place. It is then justified our choice of building a 3D model, even though its solution is computationally more expensive. It is possible to remark in Fig. 10 and Table 5 that the 3D results correct the impact of W on the goodness of fit of simulation results. We are not claiming though a perfect homoscedasticity of the results, as for small values of L we sensibly underestimate the self-heating effects. This effect is clearly visible in a scatter plot of simulation results over measurements (Fig. 11), where the points relative to small values of L deviate from the plane bisector. Moreover, we noticed that the 3D analysis produces an outlier (L = 0.2 μm , W = 2 μm). Excluding this result, the average error value for structures with W = 2 μm (Table 5) decreases from 15% to 12% and the average error for L = 0.2 μm from 8% to 3.3%. In any case, the overall accuracy of simulations over measures is satisfactory.
Table 5 Error of 3D simulation results over measures.
5.2.2. Effects of physical dimensions We present the results of 3D simulations in Fig. 12. It is possible to notice that the physical dimensions of the transistor have a strong impact on the amount of self-heating effects. In fact, measurements and simulations show that the temperature elevation in the gate is inversely proportional to the gate length L and directly proportional to the active width W. The size of the transistor influences the maximum temperature as well, but in this case the effect of W is less relevant than for the gate temperature. The relative difference between maximum and gate temperatures is decreasing over L, where for 30 nm transistors the temperature peak is in average more than double than the gate temperature. Since we verified the impact of physical dimensions on self-heating effects, it is our aim to build a simplified model predicting temperature elevation in SOI MOSFETs directly from their physical dimensions. We can write the gate temperature elevation and the maximum temperature elevation as ΔT gate ¼ Rth;1 ðW; LÞId ðW; LÞV d ;
W\L (μm)
0.03
0.06
0.09
0.2
Average
0.5 2 5 10 Average
28% 18% 16% 13% 19%
6% 17% 13% 6% 11%
4% 1% 9% 12% 7%
6% 23% 2% 2% 8%
11% 15% 10% 8% 11%
ΔT max ¼ Rth;2 ðW; LÞId ðW; LÞV d ; where Vd is the fixed potential applied to the transistor, Id is the resulting current, Rth,1 , Rth,2 are coefficients of thermal resistance, all depending on L and W. We find empirically the following relations for Rth,1 , Rth,2 and Id, where Vd =1V α0 ; dW1 ¼ 0:5 μm; dL ¼ 0:3 μm; α 0 ðW þ dW1 ÞðL þ dLÞ 2 μm K ; ¼ 30 103 W
Rth;1 ðW; LÞ ¼
β0 ; dW2 ¼ 0:1 μm; dL ¼ 0:3 μm; β0 ðW þ dW2 ÞðL þ dLÞ 2 μm K ; ¼ 50 103 W
Rth;2 ðW; LÞ ¼
Id ðW; LÞ ¼
Fig. 10. Relative difference between 2D and 3D simulations. The impact of W on 2D simulations is displayed.
V dW ; λ ¼ 883 μm Ω; ν ¼ 9818 Ω: λ þ νL
The simple model we propose gives promising results, as it is possible to remark in the scatter plots of Fig. 13. The average relative error between the simplified model and simulations or measures are all below 10%, both for the maximum and for the gate temperature.
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Fig. 12. Effects of physical dimensions on maximum temperature and average gate temperature, 3D simulations.
Fig. 13. Maximum and gate temperature elevations computed with measures, simulation and simplified models.
6. Conclusion We presented a measurement technique and a numerical analysis simulation for determining the self-heating effects in nano-scaled SOI MOSFETs. In particular, we explained a two-stage procedure for measuring the temperature elevation of the polycrystalline gate based on electrical calibration of the transistor. Then, we weighted the effect of parameters that could have been influential on the simulation results, explaining the procedure we followed for the set-up of our simulations. We presented the temperature field and the heat fluxes in a reference case, as well as the correlation between measures and simulation results. In 2D simulations, the goodness of fit strongly depends on the physical dimensions of the transistor. We managed to attenuate this effect in 3D simulations, even though we still underestimate the selfheating effects for structures endowed with short gates. The overall goodness of fit is however completely satisfactory and shows the correctness of our modeling assumptions. Finally, we analyzed the relationship between physical dimensions and temperature elevation, presenting a simplified model to predict temperature elevation in SOI MOSFETs. The results are promising both for gate and maximum temperature elevations, with average relative errors below 10%. References [1] Burenkov, J. Lorenz, Self-heating effects in nano-scaled MOSFETs and thermal aware compact models, THERMINIC, 2011.
[2] L. Wang, et al., 3D Coupled Electro-thermal FinFET Simulations Including the Fin Shape Dependence of the Thermal Conductivity, IEEE University of Glasgow, Gold Standard Simulations Ltd., TU Wien, 2014. [3] D. Vasileka, et al., Electrothermal studies of FDSOI devices that utilize a new theoretical model for the temperature and thickness dependence of the thermal conductivity, IEEE Trans. on Electron Devices 57 (3) (2010) 726–728. [4] D. Vasileka, et al., Self-heating effects in nanoscale FDSOI devices: the role of the substrate, boundary conditions at various interfaces and the dielectric material type for the BOX, IEEE Trans. on Electron Devices 56 (12) (2009) 3064–3071. [5] C. Fiegna, et al., Analysis of self-heating effects in ultrathin-body SOI MOSFETs by device simulation, IEEE Electron Devices 55 (1) (2008) 233–244. [6] A. Burenkov, et al., Self-heating of nano-scale SOI MOSFETs: TCAD and molecular dynamics simulations, THERMINIC, 2013. [7] H. Jianqiang, et al., Thermal conductivity of PECVD silicon-rich silicon nitride films measured with a SiO2/SixNy biomaterial microbridge test structure, J. Semicond. 35 (2014) 4. [8] X. Zhang, C.P. Grigoropoulos, Thermal conductivity and diffusivity of free-standing silicon nitride thin films, Rev. Sci. Instrum. 66 (1995) 2. [9] M. Shrivastava, et al., Physical insight toward heat transport and an improved electrothermal modeling framework for FinFET architectures, IEEE Trans. Electron Devices 59 (5) (2012) 1353–1363. [10] L.T. Su, et al., Measurement and modeling of self-heating in SOI NMOSFET's, IEEE Trans. Electron Devices 41 (1994) 69–75. [11] Z. Hao, et al., Thermal conductivity measurements of ultra-thin single crystal silicon films using improved structure, 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006. [12] X.J. Hu, et al., Investigation of the natural convection boundary condition in microfabricated structures, Int. J. Therm. Sci. 47 (2008) 820–824. [13] P.M. Souare, et al., Thermal correlation between measurements and FEM simulations in 3D ICs, 3D System Integration Conference, 2013.
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Microelectronics Reliability journal homepage: www.elsevier.com/locate/mr
Wafer level measurements and numerical analysis of self-heating phenomena in nano-scale SOI MOSFETs Giacomo Garegnani, Vincent Fiori ⁎, Gilles Gouget, Frederic Monsieur, Clement Tavernier STMicroelectronics, 850 rue Jean Monnet, F-38926 Crolles, France
a r t i c l e
i n f o
Article history: Received 9 November 2015 Received in revised form 4 March 2016 Accepted 5 March 2016 Available online 8 June 2016 Keywords: Nano-scale MOSFETs Self-heating Temperature measurements FEM simulations Correlation analysis Thermal sensors
a b s t r a c t We present an experimental technique and a Finite Element thermal simulation for the determination of the temperature elevation in Silicon on Insulator (SOI) MOSFETs due to self-heating. We evaluate the temperature elevation in two steps, as we calibrate the gate resistance over temperature with the transistor at off state at a first stage, and then we deduce the temperature elevation through gate resistance measurements. We simulate the self-heating phenomena in a Finite Elements Method (FEM) environment, both with 2D and 3D models. In order to set up the simulations, we weight the effects of several parameters, such as thermal material properties, the modeling of heat generation and a careful setting of boundary conditions. We present typical temperature fields and local heat fluxes, thus giving concrete indications for solving thermal reliability issues. Simulation results show temperature elevations up to approximately 120 K in the hot spot, 70 K in the gate and 7 K in the Back End of Line (BEoL). The 3D model gives results that are satisfying over the whole set of MOSFETs we consider in this work. Temperature elevation strongly depends on physical dimensions, where transistors endowed with shorter gates suffer from more severe self-heating. We propose a simplified model based on geometrical parameters that predict maximum and gate temperatures, obtaining satisfying results. Since correlation with measurements confirms the correctness of our model, we believe that our simulations could be a useful tool to determine accurate reliability rules and in a context of thermal aware design. © 2016 Published by Elsevier Ltd.
1. Introduction Downscaling of MOSFETs characteristic size to 28 nm leads to severe self-heating issues [1,2]. Moreover, the Buried Oxide (BOX) in SOI technology guarantees good electric performances but has the drawback of increasing thermal isolation of the active region, causing a more relevant temperature increase than in bulk transistors [3–6]. Several studies have been published about the self-heating of nanometer-scaled transistors, presenting Technology Computer Aided Design (TCAD) and molecular dynamics simulations that allow predicting the temperature distribution at a local level. Other studies exploit similar approaches to predict the temperature of FinFETs [2], for which the thermal confinement is a critical issue. The common features of those publications are exhaustive analyses of materials' thermal properties [3,7,8], placement of the heat source [1,6], boundary condition settings [4] and heat flux through metal lines in the Back End of Line (BEoL) [9]. Even though a wide range of sophisticated electro-thermal coupled simulations have been built [3,6], in order to produce accurate simulations of thermal phenomena in SOI MOSFETs, we believe that a real effort of correlating simulation results with experimental measures at local level is currently ⁎ Corresponding author. E-mail address: vincent.fi[email protected] (V. Fiori).
http://dx.doi.org/10.1016/j.microrel.2016.03.007 0026-2714/© 2016 Published by Elsevier Ltd.
lacking in the self-heating literature. It is therefore our purpose to measure experimentally the temperature elevation in SOI MOSFETs featured by different physical dimensions. In particular, we test transistors with four different gate lengths L (30, 60, 90, 200 nm) and four different depths of the active zone W (0.5, 2, 5, 10 μm) combining those measures in all possible manners, thus obtaining results for sixteen different structures. In this way, a complete understanding of the dependence of self-heating phenomena on the physical dimension of the transistor is retrieved. Then, we set up a FEM steady-state thermal simulation to compute the temperature field in the whole structure. Besides computing the location and value of the hot spot of the MOSFET, the simulation results allow to predict the heat fluxes in a wafer level configuration, as well as the temperature gradients. Moreover, we extract the value of the average temperature of the gate in order to verify the correlation of FEM results with measurements, thus validating our analysis. Since the correlation of simulations and measurements is promising, we believe that the model we present in this work could be exploited as a tool for careful material selection and in general for thermal aware design, eventually improving overall thermal reliability of SOI devices. We will base our future work on this simulation, verifying the thermal behavior of MOSFETs in different packaging techniques, such as flip-chip and wire bonding, as well as the impact of the BOX thickness and the temperature distribution in metal interconnects. The structure of our
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work is the following. In Section 2, the experimental procedure is presented with a detailed description of the structure calibration and the probing technique. We explain in Section 3 the 2D and 3D FEM analyses we perform, introducing all the physical phenomena and modeling parameters we take into account in order to set up the simulation. In Section 4, simulation assumptions are validated. Besides, in order to account for the heat loss induced by the imperfect contact conditions between wafer bottom and measurement equipment, we switch the corresponding boundary conditions from fixed temperature to an approximated heat transfer coefficient. Then we present and discuss the results of measurements and simulations in Section 5, finally drawing our conclusions in Section 6. 2. Measurement procedure The aim of the experimental procedure is to measure the average temperature elevation of the gate due to the self-heating effect. The structures we use for performing measurements are MOS transistors with double gate access (Fig. 1). A two-step procedure is employed [10]. Firstly, a calibration is performed in order to determine the gate electrical resistance as a function of temperature. The gate resistance is measured with the transistor at off state imposing different substrate temperatures with a variable temperature chuck. The results we obtain are clearly linear (Fig. 2), so we can express the gate electrical resistance at off state Rg,min as Rg; min ¼ f ðT Þ ¼ R0 þ Rt T; where coefficients R0 , Rt are determined empirically. R0 and Rt depend on the geometry of the transistor, and vary in the range [250, 3290] Ω and [0.3,10.5] Ω/K respectively. In the second step we measure the gate resistance Rg , max at on state, i.e., Vd = Vdd = 1 V , Vs = 0. We then exploit the calibration results for deducing the gate average temperature by ΔT ¼
Rg; max −Rg; min Rt
Fig. 2. Electrical resistance of the gate with respect to temperature at off state.
Low-k interconnects. These preliminary investigations allow determining simulation detail requirements. Then, we include the key parameters in order to set up the steady-state FEM models, both physical and simulation-related. In the following, we explain the main assumptions on which we base our model. We present in Section 4 the validation of our hypotheses. 3.1. Geometrical description and model-size-reduction strategy We build the geometry representing the studied structure as follows: • the active region is precisely described. In particular, we include in the model: source/drain, channel, gate and gate oxide, BOX, nitride and oxide spacers; • the STI and substrate are precisely modeled. • above the active region, the conformal Contact-Etching Stop Layer (CESL) and Pre-Metal Dielectrics (PMD) are discretized; • finally, the 10 metal layers BEoL, having a 7.8 μm thick and representing low-k and SiO2 based dielectrics, oxide and nitride passivations, is modeled using a stack of uniform layers;
:
3. Finite Elements modeling Our purpose is to reproduce in a simulation environment the selfheating phenomena in SOI MOSFETs. The inputs of the simulation are the physical dimensions of the transistor, the sample environment and the dissipated power; the outputs are the average temperature in the gate, taken for correlation purposes, the maximum temperature in the channel, as well as the temperature field, heat fluxes and temperature gradients in the whole structure. In order to build an accurate and predictive model while keeping reasonable numerical resource needs, we weighted the effects of several factors, such as model size-reduction and meshing techniques, boundary conditions, material properties, modeling of the heat source, impact of tungsten contacts and BEoL Cu/
Fig. 1. Scheme of the structures used for measurements.
In order to obtain a lighter simulation, both in a meshing and therefore in a solution processes, we decide to reduce the size of the model. Firstly, we reduce the substrate thickness, as building the mesh of the whole substrate would imply the creation of an enormous amount of elements. Thus, we replace a portion of the substrate with a thermal resistance, which is then connected to the heat sink. We assign to the thermal resistance thickness the arbitrary value of 1 μm, and compute its thermal conductivity value using the following formula krth ¼
1 ∙kSi ; t sub;th −t sub; mod
where tsub,th is the theoretical thickness of the substrate, tsub,mod is the thickness of the substrate in the model and kSi is the conductivity of bulk Si. In particular, the value of tsub , mod has to be large enough to allow the heat fluxes being unidirectional towards the bottom of the structure in order to conserve the simulation correctness. Moreover, in order to mimic an isolated heating transistor it is necessary that the model is wide enough to allow the entire horizontal dissipation of the generated heat. For the 2D simulation, it is possible to build the mesh of the whole model. The width has been set to 200 μm to each side of the transistor, as once this measure is reached, the temperature elevation is stable. For the 3D model, it is not practical to build a complete mesh as the number of elements grows dramatically. Therefore, vertical layers with a high conductivity value (1012 W/m K in the simulations) are juxtaposed laterally to a portion of the structure, in order to allow the whole heat transfer to take place. These vertical layers do not represent physical parts of the considered structure and are included in the model only for reducing the computational time. Moreover, they are
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magnitude lower than the correspondent bulk values, the temperature elevation could be largely underestimated exploiting the latter. 3.4. Boundary conditions The choice of boundary conditions is a crucial assumption of the simulation setting [4,12]. In particular, the modeling of the heat sink is delicate, as an imposed temperature boundary condition does not seem a physically adapted choice due to interface thermal resistance between the silicon wafer and the equipment chuck. Our final choices are the following:
Fig. 3. Mesh of the 2D model, zoom on the MOSFET region. In this case, L = 30 nm.
sufficiently far from the active region not to spoil the validity of the solution in the neighborhood of the transistor. A validation of this procedure of model reduction is shown in Section 4.1.
• Convective boundary condition at the top of the BEoL, with a heat transfer coefficient of 30 W/m2 K, adapted for natural convection in micrometer structures [12] together with the environment measures. • Adiabatic boundary conditions at lateral walls, though simulating a periodic structure • Convective boundary conditions at the bottom of the Silicon substrate, with a coefficient determined minimizing the correlation error [13]
3.5. Heat generation modeling
The structures we consider have components whose sizes vary between a few nanometers and several microns. It is therefore important to adapt the mesh to the corresponding component, trying in the meantime to avoid fast variations in element sizes, which would result in badly shaped elements and eventually in inaccurate solutions. Hence, we build the mesh progressively from the smallest parts, i.e., the MOSFET components, to the biggest ones, i.e., the Si substrate and the BEoL layers. The final mesh for both 2D and 3D simulations is depicted in Figs. 3 and 4.
The model we present in this work is exclusively thermal; hence, an appropriate modeling of heat generation is required for claiming the correctness of results. It has been reported in the literature [1,6] that power dissipation due to Joule effect takes mainly place in the channel extension at the drain side. We exploit the measurements to obtain the numerical values of generated heat using the classical Joule law (Q= V ∙ J). We choose to model heat dissipation as a uniform source distributed either in the whole channel or only in its half nearest to the drain. If results are not influenced by these two different choices, considering the whole channel as a heat source would lead to simulate only one fourth of the structure for symmetry reasons, thus allowing a computationally cheaper FEM simulation.
3.3. Material properties
3.6. Back End of Line
Thin films of semiconductors have to be treated carefully in a thermal setting, as their thermal conductivity values are sensibly lower than the corresponding bulk ones [1–3,7,8,11]. In layers characterized by thicknesses in the nanometer scale, boundary scattering phenomena are not negligible since phonon mean free path is in the same order of magnitude of the thickness itself. Hence, in order to study self-heating of nano-scale transistors solving the classic Fourier equation, corrected values of thermal conductivities have to be exploited. The values we used are taken from the literature, where experimental measures [7,8, 11] and analytical models [1,3], are presented. The obtained results are reported in Table 1. Since corrected values are even one order of
The temperature field in the BEoL is a value of interest in a selfheating contest [9]. Since in this work we focus on a wafer level configuration, we believe that the heat flux is directed towards the bottom heat sink. Therefore, the impact on the value of temperature of interconnects in the BEoL could be negligible, especially at a local level. Hence, we believe that a full description of the BEoL is not necessary, and therefore a stack of uniform layers accounts for the BEoL, as described in Section 3.1. We set two different models in order to verify the impact of metal interconnects, i.e., either we do not modify the conductivity values of any layers or we modify these values by averaging them with the thermal conductivity of copper with a 20% weight.
3.2. Meshing technique
Fig. 4. Mesh of the 3D model, top view of MOSFET and STI and perspective zoom on the transistor's components. Top layers are hidden for viewing purposes. In this case, L = 90 nm; W = 2 μm.
G. Garegnani et al. / Microelectronics Reliability 63 (2016) 90–96 Table 1 Effective values of thermal conductivity for semiconductors thin films. Material
Thickness
Thermal conductivity (W/m K)
Silicon Silicon Silicon SiO2 SiO2 SiO2 PolySilicon PolySilicon Si nitride Si nitride
Bulk 20 nm 10 nm Bulk 25 nm 2 nm Bulk 30–200 nm Bulk 10 nm
140 20 13 1.4 0.7 0.3 105 30 30 3
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with respect to measurements is convex (Fig. 6), so we can find a global minimum and choose therefore an optimal heat transfer coefficient, which finally is h = 3.566 ∙ 107 W/m2K. The value of h deduced with the procedure above is high, but not equivalent to imposing a fixed temperature at the bottom of the substrate. We perform simulations of all structures imposing Dirichlet condition, deducing an average reduction of 12% of the gate temperature and an increase in the error with measurements of approximately 70%. Therefore, we believe that the convective boundary conditions with h = 3.566 ∙ 107 W/m2K is more adapted for representing the contact between the substrate and the isothermal chuck.
3.7. Contacts
4.3. Heat generation modeling
We are interested in understanding the impact of the number of contacts on simulation results. Since tungsten has a thermal conductivity approximately two order of magnitude higher than dielectrics, it is reasonable to think that contacts offer a path to heat transfer, decreasing the temperature in the MOSFET in a non-negligible manner. Hence, we probe the temperature elevation and the dissipated power in three structures endowed with the same physical dimensions but with a different number of contacts.
We plot in Fig. 7 the results produced in the reference case by the 2D simulation using either a source distributed over the whole channel (ALLCH) or on its half at the drain side (NEXTDR). Let us remark that these two different choices lead to sensibly different results for the value of maximum temperature, but that there is practically no difference in the gate temperature. Since our correlation effort with measurements regards the average gate temperature, in the 3D model we consider the whole channel as the heat-generating region. In this way, we can exploit the structure's symmetry and set up a lighter simulation, for which the correlation with measurements is still valid. Thus, the results given by the 3D simulation are accurate only for the gate average temperature, as the hot-spot temperature in the channel is systematically underestimated due to a lower density of generated heat. Furthermore, despite the fact temperature peak differences depend on transistor layout, in all the tested configurations the mismatch resulting from the use of a symmetric power source is in the range of the correlation error. Hence, keeping in mind the above mentioned limitations and since peak temperature is a critical reliability concern, we complement the analysis on the gate region with some insights regarding the active area as well.
4. Validation of assumptions 4.1. Model size reduction We compute the solution in a reference case when the entire structure is modeled and when we apply the reduction technique explained in Section 3.1. We extract the temperature profile in the z-direction (i.e., W-wise) from the hot spot to the outer border of the STI to verify whether the lateral layers we juxtapose to the model spoil the local correctness of the solution. Results (Fig. 5) show that this technique does not spoil the correctness of results, as the temperature profiles locally coincide. 4.2. Bottom boundary condition
4.4. Back End of Line
In order to determine the heat transfer coefficient for the bottom convective boundary condition we exploit the following strategy. We perform the simulations for all the physical dimensions of interest using three different values of heat transfer coefficient. We compute the average relative error with respect to measures for each coefficient. Then, we perform a quadratic regression of the error using the heat transfer coefficient as only parameter, finally choosing the point that reaches the global the minimum. As we expected, the average error
The gate temperature results given by the two different choices explained in Section 3.6 differ in average of 6%. We shall then conclude that at wafer level a full description of the BEoL is not fundamental whereas it would be necessary, for example, in a flip-chip configuration, where the heat sink is at the top of the BEoL. The results we present in the following refer to the case in which a 20% of copper is considered for the thermal properties of the BEoL.
Fig. 5. Comparison between the temperature profile in z-direction (i.e., W-wise) of the reduced model (blue line) and the full model (pink line).
Fig. 6. Heat transfer coefficient determination: blue points represent the error on measurements, the dashed line is the quadratic interpolation used to determine the theoretical minimum.
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Fig. 7. Influence on the maximum temperature (TMAX) and on the gate average temperature (TMG) of the heat generation assumption (ALLCH = the entire channel is considered uniformly as the region dissipating power, NEXTDR = only the half of the channel next to the drain side is considered as the region dissipating power). The results of gate average temperature are not sensibly influenced by this choice. Results are divided with respect to the value of W and averaged over L.
4.5. Contacts We measure the temperature elevation in three structures endowed with a different number of contacts as explained in Section 3.7. A higher number of contacts leads to a higher power dissipation in the MOSFET, even though geometrical features are kept constant. Therefore, in order to verify the impact of contacts, we normalize the average temperature elevation in the gate with the power dissipation obtaining a value of thermal resistance Rth. The variation of Rth is negligible (Table 2), thus it is possible to deduce that contacts do not have an impact on selfheating phenomena at wafer level. Therefore, contacts are not included in our FEM simulation environment, as they do not allow a sensible heat discharge towards the lower part of the BEoL.
5. Results and discussion 5.1. Typical results A typical temperature field in the MOSFET is shown in Fig. 8. We cut the MOSFET along its two symmetry planes, so that the temperature in
the internal part of the channel is clearly visible. A strong attenuation of temperature takes place even at a local level. In fact, temperature decreases rapidly inside the BOX, thus confirming that SOI architectures suffer of higher heat isolation than bulk transistors. Even though the BOX causes thermal confinement below the heating component, at a global level the heat flux is mainly directed towards the heat sink at the bottom of the substrate (Fig. 9), meaning that the BEoL does not allow a heat discharge towards the top of the structure. In particular, the heat generated in the channel diffuses mainly upwards towards the gate, with a lateral component that is strongly decreasing with reference to the transistor length L (Table 3). This is representative of the heat confinement caused by the BOX, as globally heat discharge takes place in the heat sink at the bottom of the substrate. Therefore, the temperature in the BEoL is almost constant, and we verified a temperature elevation in the range of 2–8 K, depending on the physical dimensions, that is reached at approximately 2 μm above the active zone. Let us underline that this analysis of thermal fluxes is valid at wafer level, as, for example, a flip-chip configuration would imply a more relevant heat flux through the BEoL. In this case, we claim that the thermal
Table 2 Measurements and 3D simulation results of structures endowed with different numbers of contacts. W (μm)
L (μm)
POW (W)
Measures Contacts (K)
5 5 5
0.03 0.03 0.03
3.17E−03 4 4.16E−03 20 4.27E−03 MAX
57.3 77.1 79.5
Rth (K/W)
Rth relative difference
18,089 18,545 18,619
– 2.52% 2.93%
Fig. 9. Heat flux in the transistor neighborhood, vertical section of 3D simulation. In this case, L = 60 nm; W = 2 μm.
Table 3 Local heat fluxes in the three main directions normalized over the whole dissipated power. Direction labels are graphically explained in Fig. 9.
Fig. 8. Temperature field in the MOSFET region. In this case, L = 60 nm; W = 2 μm.
L (μm)\direction
Down
Up
Lateral
0.03 0.06 0.09 0.2
21% 23% 25% 31%
34% 45% 52% 57%
46% 32% 23% 12%
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Table 4 Error of 2D simulation results over measures. W\L (μm)
0.03
0.06
0.09
0.2
Average
0.5 2 5 10 Average
42% 1% 9% 8% 15%
92% 2% 4% 1% 25%
101% 26% 2% 4% 33%
142% 62% 20% 12% 59%
94% 22% 9% 6% 33%
confinement provided by the BOX would be less severe, as contacts and metal lines would provide a path for heat flux towards the heat sink, placed at the top of the BEoL. Fig. 11. Scatter plot of 3D simulation results over measures. The different measures of W are represented with different colors and the values of L are directly reported on the plot.
5.2. Results discussion 5.2.1. Correlation of results In Tables 4 and 5, we report the relative error of simulation results over measurements. In particular, 2D simulations fail to identify the temperature elevation in case W is small (Table 4). In fact, in this case a non-negligible part of the gate is not laying on the active region but on the STI, where a strong decrease of temperature takes place. It is then justified our choice of building a 3D model, even though its solution is computationally more expensive. It is possible to remark in Fig. 10 and Table 5 that the 3D results correct the impact of W on the goodness of fit of simulation results. We are not claiming though a perfect homoscedasticity of the results, as for small values of L we sensibly underestimate the self-heating effects. This effect is clearly visible in a scatter plot of simulation results over measurements (Fig. 11), where the points relative to small values of L deviate from the plane bisector. Moreover, we noticed that the 3D analysis produces an outlier (L = 0.2 μm , W = 2 μm). Excluding this result, the average error value for structures with W = 2 μm (Table 5) decreases from 15% to 12% and the average error for L = 0.2 μm from 8% to 3.3%. In any case, the overall accuracy of simulations over measures is satisfactory.
Table 5 Error of 3D simulation results over measures.
5.2.2. Effects of physical dimensions We present the results of 3D simulations in Fig. 12. It is possible to notice that the physical dimensions of the transistor have a strong impact on the amount of self-heating effects. In fact, measurements and simulations show that the temperature elevation in the gate is inversely proportional to the gate length L and directly proportional to the active width W. The size of the transistor influences the maximum temperature as well, but in this case the effect of W is less relevant than for the gate temperature. The relative difference between maximum and gate temperatures is decreasing over L, where for 30 nm transistors the temperature peak is in average more than double than the gate temperature. Since we verified the impact of physical dimensions on self-heating effects, it is our aim to build a simplified model predicting temperature elevation in SOI MOSFETs directly from their physical dimensions. We can write the gate temperature elevation and the maximum temperature elevation as ΔT gate ¼ Rth;1 ðW; LÞId ðW; LÞV d ;
W\L (μm)
0.03
0.06
0.09
0.2
Average
0.5 2 5 10 Average
28% 18% 16% 13% 19%
6% 17% 13% 6% 11%
4% 1% 9% 12% 7%
6% 23% 2% 2% 8%
11% 15% 10% 8% 11%
ΔT max ¼ Rth;2 ðW; LÞId ðW; LÞV d ; where Vd is the fixed potential applied to the transistor, Id is the resulting current, Rth,1 , Rth,2 are coefficients of thermal resistance, all depending on L and W. We find empirically the following relations for Rth,1 , Rth,2 and Id, where Vd =1V α0 ; dW1 ¼ 0:5 μm; dL ¼ 0:3 μm; α 0 ðW þ dW1 ÞðL þ dLÞ 2 μm K ; ¼ 30 103 W
Rth;1 ðW; LÞ ¼
β0 ; dW2 ¼ 0:1 μm; dL ¼ 0:3 μm; β0 ðW þ dW2 ÞðL þ dLÞ 2 μm K ; ¼ 50 103 W
Rth;2 ðW; LÞ ¼
Id ðW; LÞ ¼
Fig. 10. Relative difference between 2D and 3D simulations. The impact of W on 2D simulations is displayed.
V dW ; λ ¼ 883 μm Ω; ν ¼ 9818 Ω: λ þ νL
The simple model we propose gives promising results, as it is possible to remark in the scatter plots of Fig. 13. The average relative error between the simplified model and simulations or measures are all below 10%, both for the maximum and for the gate temperature.
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Fig. 12. Effects of physical dimensions on maximum temperature and average gate temperature, 3D simulations.
Fig. 13. Maximum and gate temperature elevations computed with measures, simulation and simplified models.
6. Conclusion We presented a measurement technique and a numerical analysis simulation for determining the self-heating effects in nano-scaled SOI MOSFETs. In particular, we explained a two-stage procedure for measuring the temperature elevation of the polycrystalline gate based on electrical calibration of the transistor. Then, we weighted the effect of parameters that could have been influential on the simulation results, explaining the procedure we followed for the set-up of our simulations. We presented the temperature field and the heat fluxes in a reference case, as well as the correlation between measures and simulation results. In 2D simulations, the goodness of fit strongly depends on the physical dimensions of the transistor. We managed to attenuate this effect in 3D simulations, even though we still underestimate the selfheating effects for structures endowed with short gates. The overall goodness of fit is however completely satisfactory and shows the correctness of our modeling assumptions. Finally, we analyzed the relationship between physical dimensions and temperature elevation, presenting a simplified model to predict temperature elevation in SOI MOSFETs. The results are promising both for gate and maximum temperature elevations, with average relative errors below 10%. References [1] Burenkov, J. Lorenz, Self-heating effects in nano-scaled MOSFETs and thermal aware compact models, THERMINIC, 2011.
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