SiGe heterostructure channels

Microelectronic Engineering 97 (2012) 26–28

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High mobility CMOS transistors on Si/SiGe heterostructure channels Jungwoo Oh a,⇑, Kanghoon Jeon b, Se-Hoon Lee c, Jeff Huang d, P.Y. Hung d, Injo Ok d, Barry Sassman d, Dae-Hong Ko e, Paul Kirsch d, Raj Jammy d a

School of Integrated Technology, Yonsei University, Incheon 406-840, South Korea University of California, Berkeley, CA 94720, USA c University of Texas, Austin, TX 78712, USA d SEMATECH, Austin, TX 78741, USA e Yonsei University, Seoul 120-749, South Korea b

a r t i c l e

i n f o

Article history: Received 13 December 2010 Received in revised form 19 August 2011 Accepted 18 February 2012 Available online 27 February 2012 Keywords: SiGe CMOS High mobility channel Hetero-structure Hetero-epitaxy

a b s t r a c t We have demonstrated high mobility CMOS transistors on Si/SiGe heterostructure channels selectively grown on a Si (1 0 0) substrate. Electron and hole mobility is enhanced simultaneously on a single Si/SiGe heterostructure channel by confining electrons in a strained Si channel and holes in a SiGe channel, respectively. Enhanced carrier transports in strained Si or relaxed SiGe channels are confirmed by quantum mechanical simulation. Integration of high mobility CMOS on a single channel is a promising approach to extend Si CMOS technology without the process complexity associated with dual or hybrid channel approaches. Ó 2012 Published by Elsevier B.V.

1. Introduction Strained Si channel CMOS technology has successfully extended device performance along the roadmap [1–6]. Enhancements have been more significant when combined with high-k gate dielectric and metal gate technology. High mobility channel materials are projected to extend performance beyond strained Si CMOS technology [7,8]. The high injection velocity afforded by high mobility channel materials has the potential to achieve high drive currents in quasi-ballistic operation [9–11]. To enhance mobility in nMOS and pMOS, dual channel materials (Ge for pMOS [12–14] or III–V for nMOS [15]) or hybrid Si surface orientation approaches have been demonstrated [16]; however, they might increase integration complexity. For a practical approach, the integration of high mobility CMOS transistors on a single channel is preferable. In the work presented here, we evaluated a Si/SiGe heterostructure for both electron and hole mobility boosters on a single channel architecture. Strained Si films of varying thicknesses (0–7 nm) were deposited on relaxed SiGe-on-Si substrates. Electron mobility was enhanced by transporting electrons in the strained Si channel deposited on relaxed SiGe. Hole mobility was enhanced in the relaxed SiGe channels. Quantum mechanical simulation results confirmed carrier density profiles in the Si/SiGe channels under the surface inversion. Electrons are confined in the strained Si, where ⇑ Corresponding author. E-mail address: [email protected] (J. Oh). 0167-9317/$ - see front matter Ó 2012 Published by Elsevier B.V. doi:10.1016/j.mee.2012.02.030

their energy level is lower than in the SiGe at the surface inversion potential. The best electron mobility in strained Si was achieved when strain relaxation and interface scattering are reduced with an appropriate Si/SiGe thickness. Holes are confined either in strained Si or relaxed SiGe depending on their relative energy levels with varying Si thicknesses. The best hole mobility was achieved when holes transport through the SiGe channel with a Si cap that passivates the interface. 2. Results and discussion Fig. 1 compares the interface charge density (Dit) measured by the charge pumping technique on both p- and nMOSFETs. The high-k/metal gate stack on the relaxed SiGe with a 0 nm Si layer shows a relatively high Dit of 1  1012. The Dit diminishes to 8  1010 after depositing Si (3–7 nm) on relaxed SiGe. An epitaxial Si layer forms a stable SiO2 at the interface of the high-k gate dielectric, which improves interface quality by suppressing unstable Ge oxide formation or Ge diffusion into the dielectric. Low Dit with Si caps and improved gate control over the channel enhance the on-state and off-state characteristics of the MOSFETs. Inset shows a cross-sectional transmission electron microscopy (XTEM) image of a Si/SiGe (Ge = 25%) heterostructure with high-k gate dielectric and metal gate. Si/SiGe heterostructures were selectively grown on Si (1 0 0) substrates with no nucleation on the shallow trench isolation regions. The SiGe epitaxial layer is thicker (60 nm) than the critical thickness and is fully relaxed. The

J. Oh et al. / Microelectronic Engineering 97 (2012) 26–28

Fig. 1. Interface charge density (Dit) measured by charge pumping technique on both p- and nMOSFETs. (Inset) TEM micrographs of Si/SiGe channel MOSFETs fabricated on Si substrates with 40 Å HfSiO2 gate dielectrics and TiN metal gates.

thicknesses of epitaxial Si films on relaxed SiGe, which form strained Si channels or an interface passivation layer, vary from 0 to 7 nm. Defects associated with strain relaxation remained minimal when Si and SiGe films was grown at low substrate temperatures and the partial pressure of precursors was controlled [17]. In the low temperature regime, the growth kinetics are controlled by surface reaction mechanisms. Atomic layer deposition (ALD) of 40 Å HfSiO2 gate dielectrics was done on Si/SiGe channels followed by sputtering of the TiN metal gates. Fig. 2 compares capacitance–voltage (C–V) curves measured at 100 kHz for Si/SiGe MOSFETs with varying Si thicknesses. Effective oxide thickness (EOT) was measured to be 13–14 Å with a leakage current density of 10 1–10 2 A/cm2 at a gate voltage of ±1 V. A minimal C–V hysteresis of 10 mV was measured for different Si thicknesses. Despite the relatively high Dit with 0 nm Si-on-SiGe, the C–V curves exhibit very little difference in EOT and hysteresis

3

(a) pMOSFETs

27

from 3–7 nm Si-on-SiGe. The slight increase in the EOT in the hole inversion capacitance of 3 nm Si-on-SiGe pMOSFETs in Fig. 2(a) are associated with hole confinement in the SiGe channel. For Si/SiGe nMOSFETs in Fig. 2(b), the equivalent EOT and C–V in inversion capacitance suggest electron confinement in the surface SiGe (for 0 nm Si) or Si (with 3–7 nm Si) channels. Fig. 3 shows the quantum mechanical simulation for hole density in Si/SiGe energy bands and hole mobility for pMOSFETs. Hole density is highest on the SiGe surface channel with 0 nm Si-onSiGe. With 3–7 nm Si deposited on SiGe, a quantum well is formed in the SiGe due to the valence band energy off-set. With 3 nm Sion-SiGe, holes are confined to the lowest energy level of the SiGe quantum well channel. As the Si becomes 5 or 7 nm thick, the valence band energy level of SiGe quantum well becomes higher than Si, forming a hole channel in the Si. A SiGe channel without a Si cap shows a 60% enhancement in hole mobility compared to the reference Si. Despite the high Dit without a Si cap, hole mobility is enhanced by the intrinsically high hole mobility of the SiGe channels. With 3 nm Si-on-SiGe, hole mobility is enhanced another 40%, resulting in an overall 100% enhancement. The highest mobility enhancement was seen when holes were confined in the SiGe quantum well with partial Si forming a stable SiO2 passivation. As the Si cap becomes 5 or 7 nm thick, hole channel formation shifts to the strained Si as confirmed by simulation. Hole mobility for strained Si (with 5 or 7 nm Si) is slightly less than for the SiGe quantum well (3 nm Si), but is still higher than the relaxed Si channel because of biaxial tensile strain. For nMOSFETs in Fig. 4, high electron density is formed at the surface channel where the energy level is lowest with or without a Si film on the SiGe. With a Si cap on the SiGe, a small quantum well is formed due to strain-induced conduction band energy offset, which enhances electron confinement in the surface channel. Compared to the 0 nm Si-on-SiGe, the 3–7 nm Si-on-SiGe exhibits high electron density confined in the strained Si channel. Peak electron density is highest with 3 nm Si-on-SiGe, which spreads out as the Si becomes thicker. The 5 and 7 nm Si-on-SiGe have identical electron density profiles. Electron mobility is enhanced in strained (bi-axial tensile) Si-on-SiGe as band splitting becomes wider and intra-valley scattering is reduced. For electron mobility, a SiGe channel without a Si cap exhibits lower electron mobility than the reference Si channel, which is associated with high interface trap density in the gate stack. Without a Si cap and high Dit,

2

Capacitance ( µ F/cm )

2

1

0

(b) nMOSFETs

2

1

0 -2

0nm Si 3nm Si 5nm Si 7nm Si

-1

f =100KHz 0

1

2

Gate voltage (V) Fig. 2. Capacitance–voltage (C–V) curves measured at 100 kHz for Si/SiGe MOSFETs of varying Si thicknesses.

Fig. 3. Quantum mechanical simulation for hole density in Si/SiGe energy bands and hole mobility of pMOSFETs.

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References

Fig. 4. Quantum mechanical simulation for electron density in Si/SiGe energy bands and electron mobility of nMOSFETs.

SiGe pMOSFETs, however, exhibited greater hole mobility than the Si channel. Given the Dit for SiGe pMOS and nMOS, poor electron mobility was attributed to the asymmetric Dit at the conduction band edge, high source/drain series resistance, and heavy conductive effective masses under quantum confinement [18–20]. With a Si cap on SiGe, electron mobility increases dramatically. This enhancement is achieved by electron transport in strained Si channels with less gate stack Dit. At an equivalent Dit for 3–7 nm Si, the highest electron mobility is obtained with 5 nm strained Si on SiGe channels. When a channel is formed in 5 nm Si, electrons are confined in a highly strained Si channel with less scattering at the Si/ SiGe interface. The slightly lower electron mobility enhancement of 7 nm Si-on-SiGe might be due to partial strain relaxation and defect generation as the strained Si approaches critical thickness. The lack of electron mobility enhancement for 3 nm Si-on-SiGe might be caused by carrier scattering at the Si/SiGe interface. 3. Conclusions We have demonstrated high electron and hole mobility CMOS transistors on Si-on-SiGe heterostructures. With a 5 nm Si-on-SiGe channel, the mobility enhancement for electrons and holes is enhanced by 37% and 34%, respectively. With a 3 nm Si-on-SiGe channel, hole mobility is enhanced by 100% without electron mobility degradation as compared to Si channels. Simulation results confirm electron and hole channel formation in the strained Si or relaxed SiGe channels as the Si thickness varies on relaxed SiGe. High mobility CMOS channels on Si/SiGe heterostructures are a promising approach for improving overall performance without adding process complexity.

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