- Email: [email protected]
SiGe heterostructure MOSFETs for low power analog circuit applications
Solid-State Electronics 47 (2003) 1095–1098 www.elsevier.com/locate/sse
High performance Si/SiGe heterostructure MOSFETs for low power analog circuit applications P.W. Li
a,*
a
, W.M. Liao a, C.C. Shih a, T.S. Kuo a, L.S. Lai b, Y.T. Tseng b, M.J. Tsai b
Department of Electrical Engineering, National Central University, ChungLi 320, Taiwan, ROC b Electronics Research and Service Organization, ITRI, Hsinchu, Taiwan, ROC Received 17 October 2002; accepted 7 November 2002
Abstract We have demonstrated a high performance Si1x Gex pMOSFET technology for low power circuit applications. The incorporation of 30% Ge in the strained Si1x Gex channel provides a drive current enhancement by a factor of 2.7 over its counterpart Si bulk pMOSFETs and manifests a marked advantage of two decade in exponential operating region allowing both lower power consumption and a wider dynamic range for low power circuit applications. The measured low frequency noise in Si1x Gex pMOSFETÕs is found to be significantly lower than in Si devices. The experimental results promise the potential of SiGe/Si heterostructure MOSFETs in radio-frequency low power circuit applications. Ó 2003 Elsevier Science Ltd. All rights reserved.
1. Introduction Signal swing, power, and device performance requirements for analog circuit applications result in tradeoffs for scaled MOSFET design. The power dissipation in the analog circuits is given by P ¼ 8kTf SNR Vdd =Vpp , where Vdd is the power supply voltage and Vpp , the signal voltage swing, is restricted by approximately (0:9Vdd Vth ––0.2) [1]. The lowering of the power supply has been proposed as an approach to realize low power CMOS integrated circuits. Nevertheless, this reduction can produce an increase in the gate delay. To avoid this undesirable delay increase, signal voltage swing has to be maximized which requires very low threshold voltages. Generally, threshold voltage scaling is achieved by device scaling as technological changes, but it usually results in a higher subthreshold static current and a degradation of the noise margin. Besides maximized signal range, high
*
Corresponding author. Tel.: +886-3422-7151x4538; fax: +886-3425-5830. E-mail address: [email protected] (P.W. Li).
transconductance (gm ) and high gm =Id ratio are also required for good analog performance. They have been achieved through aggressively device scaling and strict control of short channel effects. For some high performance analog applications, low flicker noise is required since it is up-converted to phase noise and thus sets a fundamental limit on the spectral purity of high-speed communication systems. However, the noise is known to increase with downscaling, which is a consequence of a less efficient fluctuations averaging, when fewer low frequency noise (LFN) sources exist in the device. These issues result in conflicting design requirements for signal swing and device performance. SiGe heterostructure MOSFETs have been experimentally demonstrated to have superior performance in carrier mobility, transconductance, and cut-off frequency for high speed digital [2] and high frequency analog applications [3]. SiGe MOSFETs have also been predicted to have great potential to offer a significant speed advantage at the low power limit of FET operation [4]. The aforementioned reasons have motivated our investigation of Si1x Gex channel pMOSFETsÕ analog performance for low power and high frequency circuit applications.
0038-1101/03/$ - see front matter Ó 2003 Elsevier Science Ltd. All rights reserved. doi:10.1016/S0038-1101(02)00465-3
P.W. Li et al. / Solid-State Electronics 47 (2003) 1095–1098
2. Device fabrication The fabrication of Si1x Gex (x ¼ 0, 0.15, 0.3) pMOSFETs started from growing an undoped tri-layer by UHV-CVD on 1–5 X cm h1 0 0i n-type Si substrates: firstly a 50 nm Si buffer layer, secondly a 15 (8) nm strained Si0:85 Ge0:15 (Si0:7 Ge0:3 ) epilayer, and finally a top-most 7 nm Si cap layer. The Si cap layer is used to protect the underlying Si1x Gex layer from being directly oxidized during gate dielectric formation and serves to provide good Si/SiO2 interface quality. Moreover, the Si cap also screen the channel carriers from Si/SiO2 interface scattering since holes are well-confined within Si1x Gex channel. A portion of this Si cap layer (2.5 nm) would be consumed during the subsequent RCA clean, HF dip, and the initial gate dielectric formation. A 10 nm LPCVD-TEOS oxide was deposited at 700 °C as gate dielectric, and subsequently followed by a 200 nm of undoped polysilicon layer deposition. Polysilicon gate was patterned by optical lithography and HBrplasma etching. Gate and source/drain were doped by BF2 implantation at 20 keV with a dosage of 5 1015 cm2 . A 900 °C, 20 s rapid thermal anneal (RTA) was used to activate the dopants. Finally passivation, contact-hole etch, metal deposition/patterning, and 400 °C forming gas sintering steps were performed to complete device fabrication.
channel as compared to their counterpart Si pMOSFET. This is due to the effective low-field hole mobility enhancement in strained Si1x Gex channels (Fig. 2) and the reduced Si/SiO2 interface scattering effect as well. Typical subthreshold characteristics of Si1x Gex pMOS devices in linear and saturation regions are shown in Fig. 3. The threshold voltage shifts positively with higher Ge content in Si1x Gex channel due to the enhanced Geinduced band offset at Si1x Gex /Si interface, which results in better hole confinement in Si1x Gex quantum well and hence, the onset of heavy inversion occurs at smaller gate voltage. The transistor parameters listed in 200 x=0
180
x=0.15
160
x=0.3
140 2 µ eff (cm /V-s)
1096
120 100 80 60 40 20 0 0
-0.5
-1
-1.5
-2
-2.5
-3
V gs - V th (V)
Fig. 2. Low-field (Vds ¼ 0:1 V) effective channel hole mobility for the Si1x Gex pMOSFETs.
3. Results and discussion The drain currents of Si1x Gex pMOS transistors are compared in Fig. 1. A 270% enhancement in drive current (defined at jVgs Vth j ¼ 3:5 V, jVds j ¼ 4 V) is achieved at 1 lm channel length with the use of Si0:7 Ge0:3
1.E-03 1.E-04 1.E-05
1.E-03 x=0 x=0.15 x=0.3
9.E-04
1.E-07 Id (A)
8.E-04
1.E-06
|V gs - V th | = -3.5 V
7.E-04
Id (A)
6.E-04
1.E-08 1.E-09
5.E-04
1.E-10
x=0
4.E-04 3.E-04 2.E-04 |V gs - V th | = -1 V
1.E-04
1.E-11
x=0.15
1.E-12
x=0.3
1.E-13 -4
0.E+00 0
1
2
3
4
5
-3
-2 -1 V gs (V)
0
1
V ds (V)
Fig. 1. Id –Vd curves for Lg;mask ¼ 1 lm Si1x Gex pMOSFETs with x ¼ 0, 0.15, and 0.3.
Fig. 3. Subthreshold characteristics of Lg;mask ¼ 1 lm Si1x Gex pMOSFETs at Vds ¼ 0:1 V (dashed lines) and )4 V (solid lines).
P.W. Li et al. / Solid-State Electronics 47 (2003) 1095–1098
1097
Table 1 Transistor parameters extracted at 300 K for 1 lm Si1x Gex pMOSFETs Ge content
x¼0
x ¼ 0:15
x ¼ 0:3
Vth (V) Subthreshold slope (mV/dec) Off-state current (nA/lm) Subthreshold swing (mV) Idsat (mA) at jVgs Vth j ¼ 3:5 V gm;linear (mS/mm) leff (cm2 /V s)
)1 122 0.39 380 0.34 9.5 65
)0.28 82.3 0.1 475 0.88 14.1 120
)0.16 83 0.02 500 1.16 17.6 190
W qVgs =nkT e 1 eqVds =kT L W / I0 eqVgs =nkT for Vds > Vds;sat L
Ids ¼ I0
x= 0
Subthreshold slope (mV/dec)
Table 1 demonstrate that there are significant improvements in low-field transconductance, subthreshold slope, low-field mobility, and off-state current for SiGe pMOSFETs as Ge concentration in Si1x Gex channel increases. The improved subthreshold slope and off-state current in Si1x Gex pMOSFETs has been analyzed by simulation [5], and it is found that a strained Si1x Gex channel with higher Ge concentration provides better carrier confinement and leads to lower vertical electric field and potential drop (band bending) in the substrate, which in turn cause higher potential barrier for holes flowing from the source to the drain and hence, lower off-state leakage current [5]. The lowering of threshold voltage in Si1x Gex channel pMOSFETs with improved subthreshold slope and off-state leakage indicates that the signal voltage swing could be enlarged without suffering short-channel effects and manifests a marked advantage of SiGe pMOSFETs for low power applications. For low-power circuit application, CMOS devices are commonly operated in weak-inverted (subthreshold) regime. The current law for a MOSFET in subthreshold operation is exponentially proportional to gate bias as
260
x=0.15 x=0.3
210
160
110
60 0.4
0.2
0
-0.2
V gs -V th (V)
Fig. 4. Subthreshold swing of Si1x Gex pMOSFETs at Vds ¼ 0:1 V.
of the interfaces of the grown epilayers. Si1x Gex pMOS devices with W =L ¼ 10 lm/5 lm were chosen to avoid short-channel or periphery effects. Typical input referred noise (SVg ) spectra versus frequency for Si1x Gex pMOSFETs are presented in Fig. 5. All the spectra for Si1x Gex pMOSFETs are dominated by a 1=f n -like component (n ¼ 1) in the range 1–1000 Hz. No characteristic bumps in the noise spectra, indicating the
ð1Þ 1.E-0 8
Ge 0%
V gs -V th =-0.3V, V ds =-0.1V, V sb =0V
1.E-0 9
2
Input Referred Noise, S Vg , (V /Hz)
Assuming saturation (Vds > Vds;sat ), in which case the Vds dependence can be neglected, this relation simplifies to an exponential law. The region of the exponential channel current on gate voltage dependence for SiGe pMOSFETs is determined by plotting the subthreshold slope with respective to gate bias as shown in Fig. 4. The extent of the plateau in the Si0:7 Ge0:3 pMOSFETÕs curve, which defines the practical low-power design domain, manifests a marked advantage of 2 decades in subthreshold operating region allowing both low power operation and a wider dynamic range. For high performance analog application, very LFN is essential since it will cause an unwanted phase modulation of the signal thus providing a limit on high-speed communications. At the same time LFN has been known to be a powerful tool to characterize the quality
1.E-1 0
Ge 30%
1.E-1 1
1.E-1 2
1/f
1.E-1 3
1.E-1 4
1
10
100 Frequency (Hz)
1000
10000
Fig. 5. (a) The spectral density of drain current noise for the Si0:7 Ge0:3 and Si pMOSFETs. (b) The spectral density of input referred noise voltage for the Si0:7 Ge0:3 and Si pMOSFETs.
1098
P.W. Li et al. / Solid-State Electronics 47 (2003) 1095–1098
contribution of the generation–recombination noise from local levels, were observed. It clearly shows that the input referred gate voltage noise (SVg ) of Si0:7 Ge0:3 pMOSFETs are considerably lower than in Si bulk devices, which was considered owing to a physical separation of the current carriers and the scattering centers by the Si cap layer [6,7]. The gate bias dependence of normalized drain current noise for the Si0:7 Ge0:3 and the Si pMOSFETs at a drain bias of )0.1 V is shown in Fig. 6. Observe that the normalized drain current noise level for the Si0:7 Ge0:3 pMOSFET is significantly lower than that of the Si pMOSFET over the entire range of gate overdrive. To determine the physical mechanism of LFN in Six Ge1x pMOSFETs, the normalized drain current noise, SId =Id2 , was plotted as a function of drain current in Fig. 7. The good correlation of the normalized drain current noise with the corresponding transconductance to drain current ratio squared, ðgm =Id Þ2 , over a wide drain current range (weak inversion regime) indicates 1.E-06 Ge 0%
V ds =-0.1V, V sb =0V, f =10Hz
Ge 30%
1.E-08
2
S Id /Id , (A /Hz)
1.E-07
2
1.E-09 1.E-10
that the carrier number fluctuations dominate due to hole trapping in the oxide. It should be noted that there is slight departure of the noise level from the ðgm =Id Þ2 variation at strong inversion which can be attributed to extra correlated mobility fluctuation [8]. In addition, Fig. 7 also clearly shows that higher transconductance to drain current ratio ðgm =Id Þ in Si0:7 Ge0:3 pMOSFETs than in Si pFETs due to higher carrier mobility in strained Si0:7 Ge0:3 channel, which are essential for good analog performance.
4. Conclusion We report the demonstration of a high performance with low power consumption and low noise MOSFET technology with strained Si1x Gex channels. The incorporation of 30% Ge in the strained Si1x Gex channel provides a drive current enhancement by a factor of 2.7 over its counterpart Si bulk pMOSFETs and manifests a marked advantage of an extended subthreshold region allowing both lower power consumption and a wider dynamic range for low power applications. The relative spectral density of LFN in SiGe pMOSFETÕs is found to be significantly lower than in Si devices. The experimental results indicate that SiGe/Si heterostructure MOSFETs offer a promising extension to the prevailing CMOS technologies affording enhanced performance at relaxed geometries for low power analog circuit applications.
1.E-11 1.E-12
Acknowledgements 0
-0.5
-1
-1.5 -2 -2.5 V gs -V th (V)
-3
-3.5
-4
Fig. 6. Normalized drain current noise for the Si0:7 Ge0:3 and Si pMOSFETs as a function of gate overdrive.
1.E-03
1.E+03
1.E-04
References
2
1.E+01
2
1.E-06
1.E+00
V ds =-0.1V, V sb =0 V, f =10Hz
1.E-08 1.E-09
Ge 0%
1.E-01
Ge 30%
1.E-02
1.E-10 1.E-09
( g m/ Id)2 (V-2)
WL*S Id /Id (µ m /Hz )
1.E+02 1.E-05
1.E-07
The work at NCU was supported by the National Science Council of Republic of China under contract no. NSC 91-2215-E-008-025, and the Ministry of Education of Republic of China under the Program for Promoting Academic Excellence of Universities, 89-E-FA06-1-4.
1.E-08
1.E-07
1.E-06
1.E-05
Normalized Drain Current, -I d *(L /W ), (A)
Fig. 7. Variation of the normalized drain current noise SId =Id2 (solid lines) for Si0:7 Ge0:3 and Si pMOSFETs and corresponding ðgm =Id Þ2 (dashed lines) with drain currents.
[1] Pelgrom MJM et al. IEDM Tech Dig 1998:915. [2] Ismail K, Chu JO, Arafa M. IEEE Electron Dev Lett 1997;18:435. [3] Konig U, Zeuner M, Hock G, Hackbarth T, Gluck M, Ostermann T, et al. Solid-State Electron 1999;43:1383. [4] Papavassiliou C, Fobelets K, Toumazou C. IEICE Trans Electron 2001;E84-C:1414. [5] Li PW, Liao WM. Solid-State Electron 2002;46:39–44. [6] Mathew SJ, Niu G, Dubbelday WB, Cressler JD, Ott JA, Chu JO. IEDM Tech Dig 1997;1:815–8. [7] Li PW, Liao WM. Solid-State Electron 2002;46:2283–7. [8] Boutchacha T, Ghibaudo G, Belmekki B. Proceedings of the IEEE 1999 International Conference on Microelectronic Test Structures, vol. 12; 1999. p. 84.
High performance Si/SiGe heterostructure MOSFETs for low power analog circuit applications P.W. Li
a,*
a
, W.M. Liao a, C.C. Shih a, T.S. Kuo a, L.S. Lai b, Y.T. Tseng b, M.J. Tsai b
Department of Electrical Engineering, National Central University, ChungLi 320, Taiwan, ROC b Electronics Research and Service Organization, ITRI, Hsinchu, Taiwan, ROC Received 17 October 2002; accepted 7 November 2002
Abstract We have demonstrated a high performance Si1x Gex pMOSFET technology for low power circuit applications. The incorporation of 30% Ge in the strained Si1x Gex channel provides a drive current enhancement by a factor of 2.7 over its counterpart Si bulk pMOSFETs and manifests a marked advantage of two decade in exponential operating region allowing both lower power consumption and a wider dynamic range for low power circuit applications. The measured low frequency noise in Si1x Gex pMOSFETÕs is found to be significantly lower than in Si devices. The experimental results promise the potential of SiGe/Si heterostructure MOSFETs in radio-frequency low power circuit applications. Ó 2003 Elsevier Science Ltd. All rights reserved.
1. Introduction Signal swing, power, and device performance requirements for analog circuit applications result in tradeoffs for scaled MOSFET design. The power dissipation in the analog circuits is given by P ¼ 8kTf SNR Vdd =Vpp , where Vdd is the power supply voltage and Vpp , the signal voltage swing, is restricted by approximately (0:9Vdd Vth ––0.2) [1]. The lowering of the power supply has been proposed as an approach to realize low power CMOS integrated circuits. Nevertheless, this reduction can produce an increase in the gate delay. To avoid this undesirable delay increase, signal voltage swing has to be maximized which requires very low threshold voltages. Generally, threshold voltage scaling is achieved by device scaling as technological changes, but it usually results in a higher subthreshold static current and a degradation of the noise margin. Besides maximized signal range, high
*
Corresponding author. Tel.: +886-3422-7151x4538; fax: +886-3425-5830. E-mail address: [email protected] (P.W. Li).
transconductance (gm ) and high gm =Id ratio are also required for good analog performance. They have been achieved through aggressively device scaling and strict control of short channel effects. For some high performance analog applications, low flicker noise is required since it is up-converted to phase noise and thus sets a fundamental limit on the spectral purity of high-speed communication systems. However, the noise is known to increase with downscaling, which is a consequence of a less efficient fluctuations averaging, when fewer low frequency noise (LFN) sources exist in the device. These issues result in conflicting design requirements for signal swing and device performance. SiGe heterostructure MOSFETs have been experimentally demonstrated to have superior performance in carrier mobility, transconductance, and cut-off frequency for high speed digital [2] and high frequency analog applications [3]. SiGe MOSFETs have also been predicted to have great potential to offer a significant speed advantage at the low power limit of FET operation [4]. The aforementioned reasons have motivated our investigation of Si1x Gex channel pMOSFETsÕ analog performance for low power and high frequency circuit applications.
0038-1101/03/$ - see front matter Ó 2003 Elsevier Science Ltd. All rights reserved. doi:10.1016/S0038-1101(02)00465-3
P.W. Li et al. / Solid-State Electronics 47 (2003) 1095–1098
2. Device fabrication The fabrication of Si1x Gex (x ¼ 0, 0.15, 0.3) pMOSFETs started from growing an undoped tri-layer by UHV-CVD on 1–5 X cm h1 0 0i n-type Si substrates: firstly a 50 nm Si buffer layer, secondly a 15 (8) nm strained Si0:85 Ge0:15 (Si0:7 Ge0:3 ) epilayer, and finally a top-most 7 nm Si cap layer. The Si cap layer is used to protect the underlying Si1x Gex layer from being directly oxidized during gate dielectric formation and serves to provide good Si/SiO2 interface quality. Moreover, the Si cap also screen the channel carriers from Si/SiO2 interface scattering since holes are well-confined within Si1x Gex channel. A portion of this Si cap layer (2.5 nm) would be consumed during the subsequent RCA clean, HF dip, and the initial gate dielectric formation. A 10 nm LPCVD-TEOS oxide was deposited at 700 °C as gate dielectric, and subsequently followed by a 200 nm of undoped polysilicon layer deposition. Polysilicon gate was patterned by optical lithography and HBrplasma etching. Gate and source/drain were doped by BF2 implantation at 20 keV with a dosage of 5 1015 cm2 . A 900 °C, 20 s rapid thermal anneal (RTA) was used to activate the dopants. Finally passivation, contact-hole etch, metal deposition/patterning, and 400 °C forming gas sintering steps were performed to complete device fabrication.
channel as compared to their counterpart Si pMOSFET. This is due to the effective low-field hole mobility enhancement in strained Si1x Gex channels (Fig. 2) and the reduced Si/SiO2 interface scattering effect as well. Typical subthreshold characteristics of Si1x Gex pMOS devices in linear and saturation regions are shown in Fig. 3. The threshold voltage shifts positively with higher Ge content in Si1x Gex channel due to the enhanced Geinduced band offset at Si1x Gex /Si interface, which results in better hole confinement in Si1x Gex quantum well and hence, the onset of heavy inversion occurs at smaller gate voltage. The transistor parameters listed in 200 x=0
180
x=0.15
160
x=0.3
140 2 µ eff (cm /V-s)
1096
120 100 80 60 40 20 0 0
-0.5
-1
-1.5
-2
-2.5
-3
V gs - V th (V)
Fig. 2. Low-field (Vds ¼ 0:1 V) effective channel hole mobility for the Si1x Gex pMOSFETs.
3. Results and discussion The drain currents of Si1x Gex pMOS transistors are compared in Fig. 1. A 270% enhancement in drive current (defined at jVgs Vth j ¼ 3:5 V, jVds j ¼ 4 V) is achieved at 1 lm channel length with the use of Si0:7 Ge0:3
1.E-03 1.E-04 1.E-05
1.E-03 x=0 x=0.15 x=0.3
9.E-04
1.E-07 Id (A)
8.E-04
1.E-06
|V gs - V th | = -3.5 V
7.E-04
Id (A)
6.E-04
1.E-08 1.E-09
5.E-04
1.E-10
x=0
4.E-04 3.E-04 2.E-04 |V gs - V th | = -1 V
1.E-04
1.E-11
x=0.15
1.E-12
x=0.3
1.E-13 -4
0.E+00 0
1
2
3
4
5
-3
-2 -1 V gs (V)
0
1
V ds (V)
Fig. 1. Id –Vd curves for Lg;mask ¼ 1 lm Si1x Gex pMOSFETs with x ¼ 0, 0.15, and 0.3.
Fig. 3. Subthreshold characteristics of Lg;mask ¼ 1 lm Si1x Gex pMOSFETs at Vds ¼ 0:1 V (dashed lines) and )4 V (solid lines).
P.W. Li et al. / Solid-State Electronics 47 (2003) 1095–1098
1097
Table 1 Transistor parameters extracted at 300 K for 1 lm Si1x Gex pMOSFETs Ge content
x¼0
x ¼ 0:15
x ¼ 0:3
Vth (V) Subthreshold slope (mV/dec) Off-state current (nA/lm) Subthreshold swing (mV) Idsat (mA) at jVgs Vth j ¼ 3:5 V gm;linear (mS/mm) leff (cm2 /V s)
)1 122 0.39 380 0.34 9.5 65
)0.28 82.3 0.1 475 0.88 14.1 120
)0.16 83 0.02 500 1.16 17.6 190
W qVgs =nkT e 1 eqVds =kT L W / I0 eqVgs =nkT for Vds > Vds;sat L
Ids ¼ I0
x= 0
Subthreshold slope (mV/dec)
Table 1 demonstrate that there are significant improvements in low-field transconductance, subthreshold slope, low-field mobility, and off-state current for SiGe pMOSFETs as Ge concentration in Si1x Gex channel increases. The improved subthreshold slope and off-state current in Si1x Gex pMOSFETs has been analyzed by simulation [5], and it is found that a strained Si1x Gex channel with higher Ge concentration provides better carrier confinement and leads to lower vertical electric field and potential drop (band bending) in the substrate, which in turn cause higher potential barrier for holes flowing from the source to the drain and hence, lower off-state leakage current [5]. The lowering of threshold voltage in Si1x Gex channel pMOSFETs with improved subthreshold slope and off-state leakage indicates that the signal voltage swing could be enlarged without suffering short-channel effects and manifests a marked advantage of SiGe pMOSFETs for low power applications. For low-power circuit application, CMOS devices are commonly operated in weak-inverted (subthreshold) regime. The current law for a MOSFET in subthreshold operation is exponentially proportional to gate bias as
260
x=0.15 x=0.3
210
160
110
60 0.4
0.2
0
-0.2
V gs -V th (V)
Fig. 4. Subthreshold swing of Si1x Gex pMOSFETs at Vds ¼ 0:1 V.
of the interfaces of the grown epilayers. Si1x Gex pMOS devices with W =L ¼ 10 lm/5 lm were chosen to avoid short-channel or periphery effects. Typical input referred noise (SVg ) spectra versus frequency for Si1x Gex pMOSFETs are presented in Fig. 5. All the spectra for Si1x Gex pMOSFETs are dominated by a 1=f n -like component (n ¼ 1) in the range 1–1000 Hz. No characteristic bumps in the noise spectra, indicating the
ð1Þ 1.E-0 8
Ge 0%
V gs -V th =-0.3V, V ds =-0.1V, V sb =0V
1.E-0 9
2
Input Referred Noise, S Vg , (V /Hz)
Assuming saturation (Vds > Vds;sat ), in which case the Vds dependence can be neglected, this relation simplifies to an exponential law. The region of the exponential channel current on gate voltage dependence for SiGe pMOSFETs is determined by plotting the subthreshold slope with respective to gate bias as shown in Fig. 4. The extent of the plateau in the Si0:7 Ge0:3 pMOSFETÕs curve, which defines the practical low-power design domain, manifests a marked advantage of 2 decades in subthreshold operating region allowing both low power operation and a wider dynamic range. For high performance analog application, very LFN is essential since it will cause an unwanted phase modulation of the signal thus providing a limit on high-speed communications. At the same time LFN has been known to be a powerful tool to characterize the quality
1.E-1 0
Ge 30%
1.E-1 1
1.E-1 2
1/f
1.E-1 3
1.E-1 4
1
10
100 Frequency (Hz)
1000
10000
Fig. 5. (a) The spectral density of drain current noise for the Si0:7 Ge0:3 and Si pMOSFETs. (b) The spectral density of input referred noise voltage for the Si0:7 Ge0:3 and Si pMOSFETs.
1098
P.W. Li et al. / Solid-State Electronics 47 (2003) 1095–1098
contribution of the generation–recombination noise from local levels, were observed. It clearly shows that the input referred gate voltage noise (SVg ) of Si0:7 Ge0:3 pMOSFETs are considerably lower than in Si bulk devices, which was considered owing to a physical separation of the current carriers and the scattering centers by the Si cap layer [6,7]. The gate bias dependence of normalized drain current noise for the Si0:7 Ge0:3 and the Si pMOSFETs at a drain bias of )0.1 V is shown in Fig. 6. Observe that the normalized drain current noise level for the Si0:7 Ge0:3 pMOSFET is significantly lower than that of the Si pMOSFET over the entire range of gate overdrive. To determine the physical mechanism of LFN in Six Ge1x pMOSFETs, the normalized drain current noise, SId =Id2 , was plotted as a function of drain current in Fig. 7. The good correlation of the normalized drain current noise with the corresponding transconductance to drain current ratio squared, ðgm =Id Þ2 , over a wide drain current range (weak inversion regime) indicates 1.E-06 Ge 0%
V ds =-0.1V, V sb =0V, f =10Hz
Ge 30%
1.E-08
2
S Id /Id , (A /Hz)
1.E-07
2
1.E-09 1.E-10
that the carrier number fluctuations dominate due to hole trapping in the oxide. It should be noted that there is slight departure of the noise level from the ðgm =Id Þ2 variation at strong inversion which can be attributed to extra correlated mobility fluctuation [8]. In addition, Fig. 7 also clearly shows that higher transconductance to drain current ratio ðgm =Id Þ in Si0:7 Ge0:3 pMOSFETs than in Si pFETs due to higher carrier mobility in strained Si0:7 Ge0:3 channel, which are essential for good analog performance.
4. Conclusion We report the demonstration of a high performance with low power consumption and low noise MOSFET technology with strained Si1x Gex channels. The incorporation of 30% Ge in the strained Si1x Gex channel provides a drive current enhancement by a factor of 2.7 over its counterpart Si bulk pMOSFETs and manifests a marked advantage of an extended subthreshold region allowing both lower power consumption and a wider dynamic range for low power applications. The relative spectral density of LFN in SiGe pMOSFETÕs is found to be significantly lower than in Si devices. The experimental results indicate that SiGe/Si heterostructure MOSFETs offer a promising extension to the prevailing CMOS technologies affording enhanced performance at relaxed geometries for low power analog circuit applications.
1.E-11 1.E-12
Acknowledgements 0
-0.5
-1
-1.5 -2 -2.5 V gs -V th (V)
-3
-3.5
-4
Fig. 6. Normalized drain current noise for the Si0:7 Ge0:3 and Si pMOSFETs as a function of gate overdrive.
1.E-03
1.E+03
1.E-04
References
2
1.E+01
2
1.E-06
1.E+00
V ds =-0.1V, V sb =0 V, f =10Hz
1.E-08 1.E-09
Ge 0%
1.E-01
Ge 30%
1.E-02
1.E-10 1.E-09
( g m/ Id)2 (V-2)
WL*S Id /Id (µ m /Hz )
1.E+02 1.E-05
1.E-07
The work at NCU was supported by the National Science Council of Republic of China under contract no. NSC 91-2215-E-008-025, and the Ministry of Education of Republic of China under the Program for Promoting Academic Excellence of Universities, 89-E-FA06-1-4.
1.E-08
1.E-07
1.E-06
1.E-05
Normalized Drain Current, -I d *(L /W ), (A)
Fig. 7. Variation of the normalized drain current noise SId =Id2 (solid lines) for Si0:7 Ge0:3 and Si pMOSFETs and corresponding ðgm =Id Þ2 (dashed lines) with drain currents.
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