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Low-power low-noise analog signal conditioning chip with on-chip drivers for healthcare applications
Microelectronics Journal 43 (2012) 828–837
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Low-power low-noise analog signal conditioning chip with on-chip drivers for healthcare applications Sanjay Joshi, Viral Thaker, Anvesha Amaravati, Maryam Shojaei-Baghini n Department of Electrical Engineering, Indian Institute of Technology (IIT) - Bombay, Powai, Mumbai, India - 400076
a r t i c l e i n f o
a b s t r a c t
Article history: Received 2 August 2011 Received in revised form 5 May 2012 Accepted 28 June 2012 Available online 26 July 2012
This paper presents an ultra low-noise, low-voltage complete analog signal conditioning chip, fabricated in 180 nm mixed-mode CMOS process. In contrast to many already-reported biomedical chips the test chip has been fabricated in a relatively scaled technology operating at low supply voltage of 1.8 V. This enables targeting energy-efficient hand-held biomedical devices where low-noise analog signal conditioning, preliminary processing and low-power wireless functionalities will be integrated on one chip. The test chip features instrumentation amplifier (INA) with chopper modulation at the first stage. The second stage is a novel area efficient spike removal filter (SRF) for attenuating coupled chopping spikes. The last stage is a differential active RC filter to adjust gain and bandwidth of the forward channel. On-chip non-overlapping clock generators with frequency of 4 kHz and 8 kHz for SRF stage are also implemented on the test. The chip also features a reconfigurable driven-right-leg circuit (DRLC) and shield drive amplifier (SDA) in the feedback path specifically for portable healthcare instruments. The DRLC provides the feedback either with operational amplifier (op-amp) or operational transconductance amplifier (OTA), configurable by the user. The presented test chip, for the first time, demonstrates an integrated OTA-based DRLC along with INA. INA and drivers have been designed and optimized for minimum power dissipation using a power-oriented design pffiffiffiffiffiffi flow. The measurement results show that the INA achieves input-referred noise density of 28 nv= Hz and DC current of 5:9 mA maintaining minimum of 109 dB at 1.91 kHz. Measurements also show that 34 dB interference reduction at 50 Hz is achieved with DRLC. Low operating voltage, wide range of specifications and reconfigurable modules and interconnections enable the chip to be used for broad range of signal conditioning applications. & 2012 Elsevier Ltd. All rights reserved.
Keywords: Chopper modulated instrumentation amplifier Driven right leg circuit Shield drive amplifier Spike removal filter
1. Introduction There is an enormous demand for reducing size and form factor of portable and personal devices, used for monitoring vital signals such as electrocardiogram (ECG), electroencephalogram (EEG) and electromyogram (EMG). Besides biomedical products, there are large number of emerging healthcare applications that involve network of sensors and their associated precise instrumentation and signal conditioning. Low power, miniaturized and low cost monitoring/sensing devices are the key components in such systems. The performance of these devices directly depends on analog signal conditioning, which must extract and amplify extremely small signals amidst a noisy environment. Moreover, to target single-chip solutions all additional functionalities such as shield drive, low-noise buffering and switching modules should n
Corresponding author. Tel.: þ91 22 25767425; fax: þ91 22 25723707. E-mail addresses: [email protected] (S. Joshi), [email protected] (V. Thaker), [email protected] (A. Amaravati), [email protected] (M. Shojaei-Baghini). 0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2012.06.008
be integrated along with the main signal conditioning circuit. This paper presents a complete low-area low-power, low-noise and low-cost general purpose analog signal conditioning chip as a core module for many personal healthcare applications. In contrast to many already-reported biomedical chips, the test chip, presented in this paper, has been fabricated in a relatively scaled technology with a low supply voltage of 1.8 V [1–5]. More features of the presented work, as compared to earlier works [1–4] are on-chip reconfigurable driven right leg circuit (DRLC) which places either the OTA or op-amp in the feedback loop plus ultra low-power and ultra low-noise instrumentation amplifier (INA) with chopper modulation followed by an area efficient chopping spike removal filter (SRF). The test chip features integrated OTA-based DRLC and INA for the first time. The test chip also includes non-overlapping on-chip clock generators for chopper and SRF stage. All required drivers such as shield drive amplifier (SDA) for further reduction of interferences (optional) and low-noise buffers are implemented on the chip. This enables it as a stand-alone general-purpose chip for various low-cost health care monitoring devices. The implemented INA
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exhibits at least 40% reduction in the current consumption, area and input referred noise while maintaining more than 105 dB CMRR (common-mode rejection ratio), as compared to reported INAs. INA works in DC coupled mode with internal high pass filtering capability and hence no AC coupling capacitor is required. Unlike most of the reported INAs we have used a scaled technology for implementation of the entire signal conditioning module. This enables integration of the entire circuit with wireless transceivers all in one single low-power chip. 1.1. Design considerations for extraction of biopotential signals Correct extraction of biopotential signals such as ECG, EMG and EEG with a limited power budget plays a vital role in personal miniaturized monitoring systems. Moreover, conditioning and acquisition of these signals have also extended their significance widely in other areas such as sports, gaming and human– computer interface. Table 1 shows the amplitude and frequency characteristics of biopotential signals [6]. 1.1.1. High CMRR and low-noise performance High CMRR, typically above 90 dB, is required to extract biopotential signals from common-mode noise. Finite transconductance of transistors and mismatch between them, appearing as input offset voltage degrade CMRR drastically. The presence of large 1/f noise at low frequencies in CMOS transistors considerably increases RMS value of the equivalent noise at the input of the conditioning system. Practically internal noise of instrumentation amplifier (INA) determines the minimum detectable signal, around 10 mV here, specifically at low frequencies below few hundred Hz. To reduce 1/f noise and achieve high CMRR and low offset, current feedback INA with chopper modulation technique is designed and used in this work. Various current-feedback INAs have been already reported [1–5,12]. However they have not been implemented for low-voltage technologies such as 180 nm CMOS process. In this paper we present a power-optimized low-noise high-CMRR INA with high input impedance, working with supply levels as low as 1.8 V. 1.1.2. Interference One of major sources of interference in conditioning of biopotential signals, even in battery operated instruments, is the capacitive coupling of measurement cables with the mains, in the surrounding area of the person, shown by C1 and C2 in Fig. 1. The induced currents i1 and i2, shown in Fig. 1, flow through the body via impedances Z1 and Z2 [9]. Other source of interference is capacitive coupling of the human body to the mains (50/60 Hz), shown by Cp in Fig. 1. This capacitive coupling results in a displacement current id and generates a common-mode voltage Vcm as large as few volts on human body [8,9]. In addition to the high common-mode voltage the displacement current may cause a differential input voltage at 50 Hz (or 60 Hz) due to mismatch between electrode impedances and/or single-ended input impedances seen at the input terminals of signal conditioning circuit. This mechanism is often called potential divider effect [6,9,10]. The common mode voltage can be reduced to few mV by employing driven right leg circuit (DRLC) [6,7,9-11]. Moreover,
Fig. 1. General interference model for portable biomedical acquisition system.
the induced differential voltage at the input can be attenuated by employing shield drive amplifier using guarding technique applying average of input signals to the shield [9]. 1.1.3. High pass filtering characteristics While extracting biopotential signals from the body, different skin conditions in the different parts of the body leads to mismatch between half cell voltage of two electrodes [2]. As a result an external DC offset voltage at the input of the analog signal conditioning module may be present of which the amplitude may reach 300 mV. Another low-frequency artifact is base line drift due to motions which should be compensated. Otherwise, the output stage of the device may get saturated and hence device starts malfunctioning. To remove such interference a Gm-C high pass filter (HPF) of selective f 3 dB is designed and used in the test chip, presented in this paper. Accordingly the test chip is used in DC-coupling mode without any series capacitance at the input terminals. We set the cut off frequency of HPF to 0.005 Hz during measurements on the test chip. In addition to all requirements related to signal quality, the entire signal conditioning circuit, integrated on the test chip, must consume minimal power to have long power autonomy. This paper is organized as follows. Section 2 presents architecture and internal modules of the test chip. Section 3 explains the design methodologies. Section 4 shows measurement results of the chip and test outputs. Finally Section 5 concludes the paper.
2. System and architecture of the signal conditioning chip Fig. 2 shows the architecture of a single-channel fully integrated analog conditioning module, implemented on the test chip. According to the requirements number of channels can be easily increased. The channel consists of the following modules.
INA with optional chopper modulation and two Gm-C feed-
Table 1 Biopotential signal characteristics. Parameters
ECG
EMG
EEG
Frequency Amplitude
0.05 Hz–500 Hz 500 mV25 mV
25 Hz–2 kHz 100 mV210 mV
0.1 Hz–100 Hz 1 mV2100 mV
back filters. SRF (spike removal filter). Rail-to-rail programmable differential active RC filter. Two ultra low-noise front end buffers. SDA (shield drive amplifiers) to attenuate effect of noise and interference from ambient.
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Fig. 4. Schematic of the implemented instrumentation amplifier. Fig. 2. Block diagram of the implemented analog signal conditioning chip.
sized transistors for the best operation under supply voltage design of 1.8 V, compared to earlier works at 3.3 V or 5 V supply. The second stage is a novel area efficient DC-coupled SRF to reduce spikes generated by choppers. Schematic of the implemented INA is shown in Fig. 4. As shown in the figure, compound transistors M1 and M4 are the input devices. M2 and M3 constitute voltage feedback transistors. I1–I6 are current sources to bias the circuit where I2 and I5 are also used in internal common-mode feedback loop. If1 and If2 are used for realizing current feedback. The ratio of RL2 and RL1 defines the gain of INA. The main features of the implemented INA are as follows.
Fig. 3. Block diagram of the implemented instrumentation amplifier.
On-chip reconfigurable DRLC which is reconfigurable to an OTA-based or op-amp based driver.
A compact non-overlapping two-phase clock generator of
frequency 4 kHz for chopping and another 8 kHz clock generator with controlled phase and duty cycle for the SRF stage. Bias generator.
The entire signal conditioning channel is able to drive up to 40 pF capacitive load for the case external ICs like data converter and micro-controller are connected to the output of signal conditioning chip.
3. Design of signal conditioning modules 3.1. Instrumentation amplifier A current-mode low-noise INA is designed for minimum power and is implemented on the chip. The current-mode INA is found to be an appropriate choice when power, noise and CMRR performance are of concern [1,5]. Implemented INA is mainly divided into two stages as shown in Fig. 3. First stage is a choppermodulated low-noise current-mode amplifier with gain of 10 V/V. This stage is inspired from INA reported in [1]. However it has been redesigned and power-optimized in 180 nm with carefully
3.1.1. Ultra low noise performance Chopper modulation is a well-known method to reduce the flicker noise [1–4,13,14]. Here chopper modulator can be activated/deactivated according to different requirements. Effectively two-chopper arrangement, shown in Fig. 3 and operating at 4 kHz, up converts the internal low-frequency noise of INA independent of input signal. The modulated noise is then filtered out from the base band signal. PMOS input transistors operating in weak inversion are used to reduce the inherent flicker noise of INA and to reduce thermal noise contribution from the other transistors of INA. 3.1.2. High-pass filter As shown in Fig. 3 high-pass filtering is established by using two Gm-C filters (OTA2 with C ext2 ¼ 2 mF and OTA1 with C ext1 ¼ 1:2 mF) and a Gm1 Gm2 module in the feedback loop. As a result INA is able to attenuate low frequencies, i.e. its transfer function will have bandpass characteristics instead of just low-pass characteristics. Cut-off frequency of the high-pass part of the transfer function is programmed using external capacitors (Cext1 and Cext2) which are a set of capacitors that can be selected using external switches. Gm1 Gm2 module, shown in Fig. 5, is used to produce a differential current from the output voltage and feed it back to the INA at low frequencies only, set by Cext1 and Cext2. One of the benefits of this high-pass filtering action is DC offset cancellation. This is because the current flowing through Gm1 Gm2 block is mirrored back to If1 and If2 (Fig. 4) which will cancel the offset across RL1 due to the negative feedback. In our design offset voltage values up to 740 mV are properly canceled. In Fig. 5 transistors M9 and M10 are used to mirror the current into the main INA module. Fig. 6 shows the simulated high-pass programmable behavior of the circuit. Cext2 and Cext1 have been changed
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from 0:5 mF to 2 mF. Capacitor value of 2 mF leads to high-pass cutoff frequency of 5 mHz. 3.1.3. High CMRR To achieve a high-performance we aimed for minimum CMRR of 100 dB for the INA. Chopper modulation and Gm-C feedback lead to high CMRR. Further improvement is achieved by the composite structure, shown in Fig. 4, for keeping Vds of the input transistors constant as suggested in [1]. All current source transistors have long channel lengths and input transistors are laid down in common centroid technique that reduces mismatch and hence improves CMRR. 3.1.4. Ultra low power dissipation We have developed a power-oriented design methodology for designing the INA. The flow chart shown in Fig. 7 explains the same. Accordingly optimal size of main transistors of INA (Fig. 4) are obtained, which are given in Table 2. Bias currents are already shown in Fig. 4.
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referred noise and area. However at the same time differential input voltage range of INA reduces. Therefore, Eq. (1) is used in an iterative manner in the design flow (Fig. 7) to minimize the power for the desired input referred noise level. 3.2. Common mode feedback circuit Since INA output is differential, it uses a common-mode feedback (CMFB) circuit to adjust a proper DC level at the output terminals. The CMFB circuit reported in [15] is designed and implemented on the chip. As CMFB circuit itself has a differential pair configuration at the input its input offset voltage should be low. So, large transistors are used at the input stage to reduce mismatch effects.
3.1.5. Optimal design for area, noise and power Input referred noise of INA, shown in Fig. 4, is given by v2n,in ¼ 2v2n1;4 þ v2RL1 þ
2g 2mI1 g 2L1
v2n,I1 þ
2g 2mI2 g 2L1
v2n,I2 þ
2g m
I32
g 2L1
v2n,I3
ð1Þ
where vn1;4 is the noise contributed by input transistors M1 and M4, vRL1 is noise contributed by resistor RL1, gL1 is 1/RL1 and g mI1 , g mI2 and g mI3 are transconductance of current sources I1 , I2 and I3, respectively. As Eq. (1) shows decreasing RL1 reduces the input
Fig. 7. Flow chart explaining power oriented design methodology of INA (Fig. 4).
Table 2 Size of main components of INA after optimization (Fig. 4).
Fig. 5. Schematic of the implemented Gm1 Gm2 module for high-pass filtering.
Transistor
W ðmmÞ=L ðmmÞ
M1 and M4 Lower transistors of CMRR improvement circuit M2 and M3 RL2 (on-chip) RL1 (on-chip)
72/1 3/2 and 10/2 15/1 200 KO 20 KO
Fig. 6. Simulated programmable high-pass behavior of INA.
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3.3. Spike removal filter
3.4. On-chip clock generator
The main problem of using chopping circuits in on-chip instrumentation amplifier is switching noise at the output of INA due to charge injection and clock feedthrough. To attenuate switching noise SRF stage is used after INA. Generally SRF is made up of PMOS buffer [1–4]. However it has drawback of shifting the DC level of the signal. This limits the voltage swing at the input of the following DC-coupled stage. Since our aim is to use scaled supply voltage levels effect of threshold voltage of the transistors on swing is not negligible. AC-coupled SRF, on the other hand, needs additional on-chip pair of capacitors which adds to the silicon area. To overcome this problem we propose a novel solution in the presented chip as shown in Fig. 8. Here SRF constitutes of PMOS switches connected to the output of differential buffers having high input capacitance and low output impedance. This configuration enables attenuating spikes while maintaining the DC level of the signal at the output. In Fig. 8 PMOS switch is ON when signal srf_clk is low and hence there is no overlapping with spikes at the output of INA and no ACcoupling capacitor is required. Another advantage of differential buffer with SRF is attenuation of charge injection effect of spike removal switch as the output impedance of the buffer used in SRF is small as compared to the RL2 . Fig. 9 shows simulated output of INA with chopper and SRF stage. Plot (d) shows the differential input signal with 20 mV amplitude. Plot (a) shows the chopped (or modulated) and amplified output with gain of 10 V/V. Plot (b) shows the down converted (demodulated) output before SRF stage, which contains coupled spikes due to chopping. Plot (c) presents output of the SRF stage, in which all the spikes have been removed.
For modulating input signals of INA and demodulating output signals of INA two non-overlapping 4 kHz clock phases are required. For controlling the SRF stage an 8 kHz clock having 10% duty cycle is required. A dual-phase and dual-frequency generator is designed and incorporated on the test chip, of which the schematic is shown in Fig. 10. First an 8 kHz clock is produced using a nine-stage ring oscillator made of current starved inverters (Fig. 10). The 4 kHz non-overlapping clock phases and 8 kHz clock with 10% duty cycle are generated from the main 8 kHz clock [15]. 3.5. Programmable gain and bandwidth stage To suit gain and bandwidth requirements of various signals, first order differential active RC filter is designed. The resistor to realize the variable gain and capacitor to adjust the cut off frequency are off-chip components. Minimum gain of 20 provides minimum total gain of 200 for the channel. 3.6. Configurable DRLC (driven right leg circuit) DRLC is a traditional method to reduce the common-mode noise (or interference) voltage on the body, Vcm. DRLC senses the common-mode (or average) voltage of sensed signals and feeds it back to the right leg using a shunt feedback amplifier. Hence the common-mode voltage is attenuated [6,11]. We have implemented a reconfigurable on-chip DRLC as shown in the Fig. 11. R2 and R3 are averaging resistors. As shown in the figure either op-amp or OTA can be selected to drive the right leg using a multiplexer. In the case of op-amp based DRLC increasing gain of feedback
Fig. 8. Schematic of SRF (spike removal filter).
Fig. 10. Schematic of clock generator circuit and current starved inverter.
Fig. 9. Performance of SRF stage.
Fig. 11. Reconfigurable DRLC and shield drive amplifier (both are on-chip).
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amplifier reduces Vcm as given by the following equation [6,10] (id is the induced displacement current on the body): i V cm ¼ Z 3 d R 1 þ R1f
ð2Þ
Since an on-chip DRLC is desired area and power dissipation of DRLC circuit should be minimized. In this regard using OTA to drive the body is far more advantages than using conventional opamp. These advantages are explained as follows. 1. Ease of loop stabilization. As explained in [17] the transfer function between common-mode voltage (Vcm) and power line voltage results into three poles. One pole is present at the input of the buffer due to electrode impedance (Z1, Z2) and parasitic capacitance (C1, C2) as shown in Fig. 1. The second pole is due to the impedance Z3 and equivalent parasitic capacitance of Cp and Cb (Fig. 1). Third pole is due to the impedance Z3 and parasitic capacitances at the op-amp output. However in the case of OTA the output stage is a current source with high output impedance. Therefore, the stability becomes independent of impedance Z3. As a result number of poles reduces to two poles. The detailed analysis is given in [17]. Moreover, due to high output impedance OTA is compensated easily, compared to an op-amp. As a result total area and power consumption of the on-chip DRLC reduces. 2. In case of OTA based DRLC external resistors Rf and R1 are not required, which is important for a fully on-chip DRLC. Folded cascode OTA is used for OTA-based DRLC. Schematic of the OTA is shown in Fig. 12 [15].
Fig. 13. Schematic of op-amp.
3.7. On-chip SDA (shield drive amplifier) Fig. 14. Schematic of on-chip ultra low-noise buffer.
The difference in electrode impedances induces unwanted differential input voltage Vab as shown in Fig. 1. Different shielding techniques have been discussed in [9]. We employ method of guarding with average of single-ended input signals on the test chip. In this method the shields are driven by the average of the input common-mode voltages. Therefore, there is no potential difference between the shield and inner wire which carries the signal. Hence, there is no sensitivity to the interference due to potential divider effect [9]. The SDA op-amp is a rail-to-rail cascode op-amp with 200 mA current drive capability. High current drive capability is needed in order to drive multiple shields depending upon length of the cable. Fig. 11 shows how SDA is deployed on the test chip. The SDA is unity gain amplifier with R2 and R3 as averaging resistors.
3.8. Op-amp Two-stage op-amp with rail to rail output voltage stage, 100 mA output current drive capability and low power dissipation is designed. The op-amp achieves rail to rail output voltage by using class-AB output stage with class-AB control circuit [18]. Fig. 13 shows schematic of the implemented op-amp. M1_op, M2_op, M7_op, M8_op, M9_op and M10_op form the folded cascode stage. M11_op and M16_op form the class AB control circuit. (M14_op, M16_op, I2) and (M17_op, M18_op, I3) bias M11_op and M16_op, respectively. M3_op and M4_op are output transistors, which source (or sink) the current to (or from) the output. They are kept in moderate inversion to reduce the quiescent current and hence, reduce the current consumption. M11_op and M16_op are common gate amplifiers. M3_op and M4_op have relatively large sizes to be able to drive 100 mA output current. The op-amp is frequency compensated using Miller compensation technique [18]. 3.9. Ultra low-noise buffer Two low-noise buffers are kept before instrumentation amplifier [19]. Low-noise buffers are designed by using two stage op-amp configuration [15], of which the schematic is shown in Fig. 14. PMOS transistors are used as input transistors to reduce the input noise level. Large W and L are used to reduce the flicker noise and offset. 4. Measurement results
Fig. 12. Schematic of OTA used in reconfigurable on-chip DRLC.
The entire signal conditioning circuit and drivers are fabricated on a multi-project test chip in 180 nm UMC mixed-mode CMOS
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Fig. 15. Micro-photograph of the chip.
process. Total area of all modules is quite low (only 655 mm 365 mm), as shown in the chip micro-photograph in Fig. 15. The chip is powered with supply voltage of 1.8 V by using two 1.5 V batteries and a DC–DC converter IC. Fig. 16 shows the designed test board with shield box to measure the specifications of the chip. Fig. 17 illustrates the measurement setup used for characterizing the test chip. Fig. 18 shows measured input-referred noise power spectral density (PSD) of the INA with chopper (specified with black color and corresponding to the values on left Y-axis) and without chopper (specified with red color and corresponding to the values on right Y-axis). SR 530 lock-in amplifier is used for precise noise measurement [16]. As shown in the figure there is a significant reduction in PSD of noise for frequencies below 1 kHz (for better clarity different scales are used on Y axes on the left and right pffiffiffiffiffiffiffi side). Measured noise density of INA with chopper is 28 nv= Hz with corner frequency of flicker noise around 4 Hz. Small component of 50 Hz interference and its harmonics which are not clear in chopper-less case due to higher noise level are observed when chopper is activated. Fig. 19(a) and (b) shows the common-mode gain measurement setup and CMRR of the INA, obtained from measurement when chopper is activated, respectively. SR 530 lock-in amplifier is used to measure common-mode gain accurately. CMRR is obtained as ratio of differential gain to common-mode gain. As the value of common-mode gain is below 90 dB it is impossible to measure the amplitude of the output signal due to common-mode input
Fig. 16. Test board.
Fig. 17. Setup for testing the chip.
Fig. 19. (a) CMRR measurement setup and (b) CMRR versus frequency plot.
Fig. 18. Measured input-referred noise density of INA with and without chopper (Y axes have different scales.) (For interpretation of the references to color in this figure caption, the reader is referred to the web version of this article.)
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Fig. 20. PSRR of INA.
Fig. 21. Percentage change in gain of INA as a function of input CM voltage.
Fig. 22. Percentage change in the INA gain as a function of differential input voltage.
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using DSO. Instead lock-in amplifier is used to precisely measure amplitude of signals in the range of micro-volts. A sync signal along with the signal that is being measured is given to the lockin amplifier as shown in Fig. 19(a). Lock-in amplifier displays the amplitude and phase of the output signal at reference input frequency. As Fig. 19(a) presents minimum achieved CMRR is 109 dB at 1.91 kHz which is quite high. Fig. 20 shows the measured PSRR of the INA. SR 530 lock-in amplifier is again used to accurately measure the output signal resulted from a signal imposed on the power supply. Minimum achieved PSRR is 104 dB at 50 Hz, which is due to common-mode interference at 50 Hz. However it is still more than 100 dB. Fig. 21 presents measured values of INA gain with respect to the input common-mode voltage. The INA gain varies maximum by 71.5% as input common-mode voltage changes from 0.7 V to 1.2 V. Fig. 22 shows that the INA gain changes up to only 71.5% in the wide 720 mV differential input voltage range. Fig. 23 shows the output waveform of 4 kHz non-overlapping clock generator (a) and 8 kHz SRF clock generator (b), respectively. They perfectly match the desired frequency and duty cycle. To compare impact of op-amp based and OTA-based DRLC measurements are performed in different cases. Fig. 24 shows the induced 50 Hz interference voltage on the body for these cases. Fig. 24(a) shows the interference voltage on the body without DRLC. The induced peak to peak voltage (Vpp) is 1.72 V which will saturate INA. Fig. 24(b) presents coupled noise to the body when OTA-based DRLC is activated. As shown in the figure Vpp of 50 Hz interference signal is reduced to 35 mV, which is a significant reduction of interference (34 dB). Fig. 24(c) and (d) shows reduced interference by using op-amp based DRLC in unity gain configuration and with gain of 20, respectively. Vpp is best reduced to 62 mV, as compared to 35 mV for OTA-based DRLC. Slight variation of frequency in Fig. 24 is due to variation of mains frequency during measurements. Fig. 25 shows acquired ECG of human body using the test chip. Table 3 shows the differential voltage generated on the body due to potential divider effect, Vab. Vab reduces by 100 times by applying only DRLC. In addition, it reduces 10 times more by applying both DRLC and SDA. As shown in Table 3, 5 mV differential voltage is generated on the body without SDA. This 5 mV might not be the problem in acquiring ECG but will be troublesome for EEG acquisition. Therefore, the differential voltage is further reduced up to 0:5 mV by SDA. Table 4 summarizes measurement results of the operational amplifier, used in DRLC. Table 5 shows measured power pffiffiffiffiffiffidissipaffi tion of every module on the chip. Considering 28 nv= Hz inputreferred noise density while consuming only 5:9 mA by INA and 5:7 mA by clock generator (for chopping) makes the presented
Fig. 23. Output of clock generator (a) 4 kHz clock for chopping and (b) 8 kHz non-overlapping low duty cycle clock for SRF.
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Fig. 24. Induced interference voltage on the body (a) without DRLC, (b) with OTA based DRLC, (c) with op-amp based DRLC in unity gain configuration and (d) with op-amp based DRLC with gain of 20.
Table 4 Measurement results of operational amplifier. Specification
Measurement result
Open Loop Gain CMRR Unity gain bandwidth Output voltage swing Input common mode range Input referred offset (Across 19 chips)
102 dB 86 dB (100 Hz to 10 kHz) 400 kHz 1.78 Vpp 0.4–1.8 V 7 2.5 mV (max) 7 0.1 mV (min)
Table 5 Power performance of all the modules on the test chip. Fig. 25. Recorded ECG with the analog signal conditioning chip.
Table 3 Coupled differential voltage on the body by potential divider effect. Scenario
Vab (mV)
Without applying DRLC and SDA After applying DRLC After applying DRLC and SDA
500 5 0.5
INA, the best among ultra low-noise and ultra low-power INAs, reported till date, in 180 nm CMOS technology. Performance of the test chip is compared with earlier works in Table 6. As table shows combined superior performance parameters of the test chip, as compared to other works, are low supply voltage (1.8 V), high differential input voltage range 720 mV, low input-referred pffiffiffiffiffiffi ffi noise (28 nv= Hz) and high CMRR (at least 109 dB) and high linearity.
Module
Current consumption (mA)
Instrumentation amplifier SRF stage Active RC op-amp DRLC op-amp Shield drive op-amp DRLC OTA Clock generator Bias generator Low-noise buffer
5.9 4 52.5 52.5 90.8 12.2 5.7 3.7 28.6
Total
256
5. Conclusions A low-power, low-voltage and ultra low-noise signal conditioning circuit in 180 nm CMOS process is presented. The test chip is appropriate for conditioning of various biopotential signals. For the first time, an integrated reconfigurable driven-right-leg circuit (DRLC), working either with on-chip OTA or on-chip op-amp, is
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Table 6 Performance comparison of the presented test chip with earlier works. Parameters
This work
[3]
[4]
[13]
[12]
[1]
Technology (nm) Supply voltage (V) Input dynamic range (mV) Maximum channel gain Input CM range (V) High freq. cutoff (Hz) pffiffiffiffiffiffi Input-referred noise (nv= Hz) CMRR (dB)
180 1.8 7 20 (channel gain¼ 45) 5000 0.7–1.3 Adjustable 28
500 2 N/A 2500 N/A 0.34 60
90 3 N/A 2500 1.05–2.3 0.4 51.4
800 1.7–3.3 N/A N/A N/A Adjustable N/A
350 3.3 12 6 0.3–2.3 N/A N/A
500 3 N/A N/A N/A N/A 85
109 (CMRR ¼120 dB at 50 Hz) 0.016
120
140
80
100
105
N/A
0.1
0.52
N/A
N/A
THD (%)
implemented on the test chip. Measurement results of OTA-based DRLC show better attenuation of the interference signals on the body. DRLC using OTA has also advantage of significant reduction in area and external components. The proposed circuit eliminates 1/f noise effectively in its current feedback INA using chopper modulation. The INA achieves worst case CMRR of 109 dB atffi pffiffiffiffiffiffi 1.91 kHz and input referred voltage noise density of 28 nv= Hz. ECG has been also recorded with the test chip. The test chip has high measured input differential voltage range of 720 mV so that it can be used even for sensor applications like electronic nose or seismic activity detection by geo-phones.
Acknowledgement The authors would like to acknowledge TCS – India for financial support of chip fabrication, SMDP Government of India and VLSI lab IIT – Bombay for providing design tools. The 180 nm UMC model files have been provided by Europractice. References [1] R.F. Yazicioglu, P. Merken, R. Puers, S. Member, C.V. Hoof, A 60 mW pffiffiffiffiffiffi 60 nV= Hz readout front-end for portable biopotential acquisition systems, IEEE J. Solid State Circuits 42 (May (5)) (2007) 1100–1110. [2] R.F. Yazicioglu, T. Torfs, P. Merken, J. Penders, R.P. Vladimir Leonov, B. Gyselinckx, C.V. Hoof, Ultra-low-power biopotential interfaces and their applications in wearable and implantable systems, Microelectron. J. 40 (2009) 1313–1321. [3] R.F. Yazicioglu, S. Kim, T. Torfs, H. Kim, C.V. Hoof, A 30 mW analog signal processor ASIC for portable biopotential signal monitoring, IEEE J. Solid State Circuits 46 (January (1)) (2011) 209–223. [4] C.-T. Ma, P.-I. Mak, M.-I. Vai, P.-U. Mak, S.-H. Pun, W. Feng, R.P. Martins, A 90 nm CMOS bio-potential signal readout front-end with improved powerline interference rejection, in: Proceedings of the IEEE ISCAS, 2009.
[5] M. Shojaei-Baghini, R.K. Lal, D.K. Sharma, A low-power and compact analog cmos processing chip for portable ECG recorders, in: Proceedings of the IEEE A-SSCC, 2005, pp. 473–476. [6] J.G. Webster, Medical Instrumentation Application and Design, 4th ed., Wiley India Pvt. Ltd., New Delhi, 2007. [7] A. Nonclercq, P. Mathys, Reduction of power line interference using active electrodes and a driven-right-leg circuit in electroencephalographic recording with a minimum number of electrodes, in: Proceedings of the IEEE EMBS Conference, 2004. [8] J.C. Huhta, J.G. Webster, 60-Hz interference in electro-cardiography, IEEE Trans. Biomed. Eng. 20 (March (2)) (1973) 91–101. [9] A.C.M. van Rijn, A. Peper, C. Grimbergen, High-quality recording of bioelectric events, part 1: interference reduction, theory and practice, Med. Biol. Eng. Comput. 28 (September) (1990) 389–394. [10] A. Wong, K.-P. Pun, Y.-T. Zhang, C.-S. Choy, An ECG measurement IC using driven-right-leg circuit, in: Proceedings of the IEEE ISCAS, 2006. [11] B. Winter, J. Webster, Driven-right-leg circuit design, IEEE Trans. Biomed. Eng. 30 (January (1)) (1983) 62–66. [12] M.S. Baghini, R.K.L. Sudip Nag, D.K. Sharma, An ultra-low-power currentmode integrated CMOS instrumentation amplifier for personal ECG recorders, J. Circuits Syst. Comput. 17 (6) (2008) 1053–1067. [13] T. Denison, K. Consoer, W. Santa, A.-T. Avestruz, J. Cooley, A. Kelly, A 2 mW 100 nv/rtHz copper-stabilized instrumentation amplifier for chronic measurement of neural field potentials, IEEE J. Solid State Circuits 42 (December (12)) (2007) 2934–2945. [14] C. Menolfi, Q. Huang, A fully integrated, untrimmed CMOS instrumentation amplifier with submicrovolt offset, IEEE J. Solid State Circuits 34 (March (3)) (1999) 415–420. [15] R. Baker, H.W. Li, D.E. Boyce, CMOS Circuit Design, Layout and Simulation, Prentice Hall of India Private Limited, IEEE Press, New Delhi-110 001, 2005. [16] Stanford Research Systems, Manual of Model SR530 Lock-in Amplifier, 2001. [17] E.M. Spinelli, N.H.M. nez, M.A. Mayosky, A transconductance driven-right-leg circuit, IEEE Trans. Biomed. Eng. 46 (December (12)) (1999) 1466–1470. [18] R. Hogervorst, J.P. Tero, R.G.H. Eschauzier, J.H. Huijsing, A compact powerefficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries, IEEE J. Solid State Circuits 29 (December (12)) (1994) 1505–1513. [19] E.C. Bosch, ECG Front-End Design is Simplified with Micro-converter, online /http://www.analog.com/library/analogdialogue/archives/37-11/ecg.htmlS.
Contents lists available at SciVerse ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Low-power low-noise analog signal conditioning chip with on-chip drivers for healthcare applications Sanjay Joshi, Viral Thaker, Anvesha Amaravati, Maryam Shojaei-Baghini n Department of Electrical Engineering, Indian Institute of Technology (IIT) - Bombay, Powai, Mumbai, India - 400076
a r t i c l e i n f o
a b s t r a c t
Article history: Received 2 August 2011 Received in revised form 5 May 2012 Accepted 28 June 2012 Available online 26 July 2012
This paper presents an ultra low-noise, low-voltage complete analog signal conditioning chip, fabricated in 180 nm mixed-mode CMOS process. In contrast to many already-reported biomedical chips the test chip has been fabricated in a relatively scaled technology operating at low supply voltage of 1.8 V. This enables targeting energy-efficient hand-held biomedical devices where low-noise analog signal conditioning, preliminary processing and low-power wireless functionalities will be integrated on one chip. The test chip features instrumentation amplifier (INA) with chopper modulation at the first stage. The second stage is a novel area efficient spike removal filter (SRF) for attenuating coupled chopping spikes. The last stage is a differential active RC filter to adjust gain and bandwidth of the forward channel. On-chip non-overlapping clock generators with frequency of 4 kHz and 8 kHz for SRF stage are also implemented on the test. The chip also features a reconfigurable driven-right-leg circuit (DRLC) and shield drive amplifier (SDA) in the feedback path specifically for portable healthcare instruments. The DRLC provides the feedback either with operational amplifier (op-amp) or operational transconductance amplifier (OTA), configurable by the user. The presented test chip, for the first time, demonstrates an integrated OTA-based DRLC along with INA. INA and drivers have been designed and optimized for minimum power dissipation using a power-oriented design pffiffiffiffiffiffi flow. The measurement results show that the INA achieves input-referred noise density of 28 nv= Hz and DC current of 5:9 mA maintaining minimum of 109 dB at 1.91 kHz. Measurements also show that 34 dB interference reduction at 50 Hz is achieved with DRLC. Low operating voltage, wide range of specifications and reconfigurable modules and interconnections enable the chip to be used for broad range of signal conditioning applications. & 2012 Elsevier Ltd. All rights reserved.
Keywords: Chopper modulated instrumentation amplifier Driven right leg circuit Shield drive amplifier Spike removal filter
1. Introduction There is an enormous demand for reducing size and form factor of portable and personal devices, used for monitoring vital signals such as electrocardiogram (ECG), electroencephalogram (EEG) and electromyogram (EMG). Besides biomedical products, there are large number of emerging healthcare applications that involve network of sensors and their associated precise instrumentation and signal conditioning. Low power, miniaturized and low cost monitoring/sensing devices are the key components in such systems. The performance of these devices directly depends on analog signal conditioning, which must extract and amplify extremely small signals amidst a noisy environment. Moreover, to target single-chip solutions all additional functionalities such as shield drive, low-noise buffering and switching modules should n
Corresponding author. Tel.: þ91 22 25767425; fax: þ91 22 25723707. E-mail addresses: [email protected] (S. Joshi), [email protected] (V. Thaker), [email protected] (A. Amaravati), [email protected] (M. Shojaei-Baghini). 0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2012.06.008
be integrated along with the main signal conditioning circuit. This paper presents a complete low-area low-power, low-noise and low-cost general purpose analog signal conditioning chip as a core module for many personal healthcare applications. In contrast to many already-reported biomedical chips, the test chip, presented in this paper, has been fabricated in a relatively scaled technology with a low supply voltage of 1.8 V [1–5]. More features of the presented work, as compared to earlier works [1–4] are on-chip reconfigurable driven right leg circuit (DRLC) which places either the OTA or op-amp in the feedback loop plus ultra low-power and ultra low-noise instrumentation amplifier (INA) with chopper modulation followed by an area efficient chopping spike removal filter (SRF). The test chip features integrated OTA-based DRLC and INA for the first time. The test chip also includes non-overlapping on-chip clock generators for chopper and SRF stage. All required drivers such as shield drive amplifier (SDA) for further reduction of interferences (optional) and low-noise buffers are implemented on the chip. This enables it as a stand-alone general-purpose chip for various low-cost health care monitoring devices. The implemented INA
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exhibits at least 40% reduction in the current consumption, area and input referred noise while maintaining more than 105 dB CMRR (common-mode rejection ratio), as compared to reported INAs. INA works in DC coupled mode with internal high pass filtering capability and hence no AC coupling capacitor is required. Unlike most of the reported INAs we have used a scaled technology for implementation of the entire signal conditioning module. This enables integration of the entire circuit with wireless transceivers all in one single low-power chip. 1.1. Design considerations for extraction of biopotential signals Correct extraction of biopotential signals such as ECG, EMG and EEG with a limited power budget plays a vital role in personal miniaturized monitoring systems. Moreover, conditioning and acquisition of these signals have also extended their significance widely in other areas such as sports, gaming and human– computer interface. Table 1 shows the amplitude and frequency characteristics of biopotential signals [6]. 1.1.1. High CMRR and low-noise performance High CMRR, typically above 90 dB, is required to extract biopotential signals from common-mode noise. Finite transconductance of transistors and mismatch between them, appearing as input offset voltage degrade CMRR drastically. The presence of large 1/f noise at low frequencies in CMOS transistors considerably increases RMS value of the equivalent noise at the input of the conditioning system. Practically internal noise of instrumentation amplifier (INA) determines the minimum detectable signal, around 10 mV here, specifically at low frequencies below few hundred Hz. To reduce 1/f noise and achieve high CMRR and low offset, current feedback INA with chopper modulation technique is designed and used in this work. Various current-feedback INAs have been already reported [1–5,12]. However they have not been implemented for low-voltage technologies such as 180 nm CMOS process. In this paper we present a power-optimized low-noise high-CMRR INA with high input impedance, working with supply levels as low as 1.8 V. 1.1.2. Interference One of major sources of interference in conditioning of biopotential signals, even in battery operated instruments, is the capacitive coupling of measurement cables with the mains, in the surrounding area of the person, shown by C1 and C2 in Fig. 1. The induced currents i1 and i2, shown in Fig. 1, flow through the body via impedances Z1 and Z2 [9]. Other source of interference is capacitive coupling of the human body to the mains (50/60 Hz), shown by Cp in Fig. 1. This capacitive coupling results in a displacement current id and generates a common-mode voltage Vcm as large as few volts on human body [8,9]. In addition to the high common-mode voltage the displacement current may cause a differential input voltage at 50 Hz (or 60 Hz) due to mismatch between electrode impedances and/or single-ended input impedances seen at the input terminals of signal conditioning circuit. This mechanism is often called potential divider effect [6,9,10]. The common mode voltage can be reduced to few mV by employing driven right leg circuit (DRLC) [6,7,9-11]. Moreover,
Fig. 1. General interference model for portable biomedical acquisition system.
the induced differential voltage at the input can be attenuated by employing shield drive amplifier using guarding technique applying average of input signals to the shield [9]. 1.1.3. High pass filtering characteristics While extracting biopotential signals from the body, different skin conditions in the different parts of the body leads to mismatch between half cell voltage of two electrodes [2]. As a result an external DC offset voltage at the input of the analog signal conditioning module may be present of which the amplitude may reach 300 mV. Another low-frequency artifact is base line drift due to motions which should be compensated. Otherwise, the output stage of the device may get saturated and hence device starts malfunctioning. To remove such interference a Gm-C high pass filter (HPF) of selective f 3 dB is designed and used in the test chip, presented in this paper. Accordingly the test chip is used in DC-coupling mode without any series capacitance at the input terminals. We set the cut off frequency of HPF to 0.005 Hz during measurements on the test chip. In addition to all requirements related to signal quality, the entire signal conditioning circuit, integrated on the test chip, must consume minimal power to have long power autonomy. This paper is organized as follows. Section 2 presents architecture and internal modules of the test chip. Section 3 explains the design methodologies. Section 4 shows measurement results of the chip and test outputs. Finally Section 5 concludes the paper.
2. System and architecture of the signal conditioning chip Fig. 2 shows the architecture of a single-channel fully integrated analog conditioning module, implemented on the test chip. According to the requirements number of channels can be easily increased. The channel consists of the following modules.
INA with optional chopper modulation and two Gm-C feed-
Table 1 Biopotential signal characteristics. Parameters
ECG
EMG
EEG
Frequency Amplitude
0.05 Hz–500 Hz 500 mV25 mV
25 Hz–2 kHz 100 mV210 mV
0.1 Hz–100 Hz 1 mV2100 mV
back filters. SRF (spike removal filter). Rail-to-rail programmable differential active RC filter. Two ultra low-noise front end buffers. SDA (shield drive amplifiers) to attenuate effect of noise and interference from ambient.
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Fig. 4. Schematic of the implemented instrumentation amplifier. Fig. 2. Block diagram of the implemented analog signal conditioning chip.
sized transistors for the best operation under supply voltage design of 1.8 V, compared to earlier works at 3.3 V or 5 V supply. The second stage is a novel area efficient DC-coupled SRF to reduce spikes generated by choppers. Schematic of the implemented INA is shown in Fig. 4. As shown in the figure, compound transistors M1 and M4 are the input devices. M2 and M3 constitute voltage feedback transistors. I1–I6 are current sources to bias the circuit where I2 and I5 are also used in internal common-mode feedback loop. If1 and If2 are used for realizing current feedback. The ratio of RL2 and RL1 defines the gain of INA. The main features of the implemented INA are as follows.
Fig. 3. Block diagram of the implemented instrumentation amplifier.
On-chip reconfigurable DRLC which is reconfigurable to an OTA-based or op-amp based driver.
A compact non-overlapping two-phase clock generator of
frequency 4 kHz for chopping and another 8 kHz clock generator with controlled phase and duty cycle for the SRF stage. Bias generator.
The entire signal conditioning channel is able to drive up to 40 pF capacitive load for the case external ICs like data converter and micro-controller are connected to the output of signal conditioning chip.
3. Design of signal conditioning modules 3.1. Instrumentation amplifier A current-mode low-noise INA is designed for minimum power and is implemented on the chip. The current-mode INA is found to be an appropriate choice when power, noise and CMRR performance are of concern [1,5]. Implemented INA is mainly divided into two stages as shown in Fig. 3. First stage is a choppermodulated low-noise current-mode amplifier with gain of 10 V/V. This stage is inspired from INA reported in [1]. However it has been redesigned and power-optimized in 180 nm with carefully
3.1.1. Ultra low noise performance Chopper modulation is a well-known method to reduce the flicker noise [1–4,13,14]. Here chopper modulator can be activated/deactivated according to different requirements. Effectively two-chopper arrangement, shown in Fig. 3 and operating at 4 kHz, up converts the internal low-frequency noise of INA independent of input signal. The modulated noise is then filtered out from the base band signal. PMOS input transistors operating in weak inversion are used to reduce the inherent flicker noise of INA and to reduce thermal noise contribution from the other transistors of INA. 3.1.2. High-pass filter As shown in Fig. 3 high-pass filtering is established by using two Gm-C filters (OTA2 with C ext2 ¼ 2 mF and OTA1 with C ext1 ¼ 1:2 mF) and a Gm1 Gm2 module in the feedback loop. As a result INA is able to attenuate low frequencies, i.e. its transfer function will have bandpass characteristics instead of just low-pass characteristics. Cut-off frequency of the high-pass part of the transfer function is programmed using external capacitors (Cext1 and Cext2) which are a set of capacitors that can be selected using external switches. Gm1 Gm2 module, shown in Fig. 5, is used to produce a differential current from the output voltage and feed it back to the INA at low frequencies only, set by Cext1 and Cext2. One of the benefits of this high-pass filtering action is DC offset cancellation. This is because the current flowing through Gm1 Gm2 block is mirrored back to If1 and If2 (Fig. 4) which will cancel the offset across RL1 due to the negative feedback. In our design offset voltage values up to 740 mV are properly canceled. In Fig. 5 transistors M9 and M10 are used to mirror the current into the main INA module. Fig. 6 shows the simulated high-pass programmable behavior of the circuit. Cext2 and Cext1 have been changed
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from 0:5 mF to 2 mF. Capacitor value of 2 mF leads to high-pass cutoff frequency of 5 mHz. 3.1.3. High CMRR To achieve a high-performance we aimed for minimum CMRR of 100 dB for the INA. Chopper modulation and Gm-C feedback lead to high CMRR. Further improvement is achieved by the composite structure, shown in Fig. 4, for keeping Vds of the input transistors constant as suggested in [1]. All current source transistors have long channel lengths and input transistors are laid down in common centroid technique that reduces mismatch and hence improves CMRR. 3.1.4. Ultra low power dissipation We have developed a power-oriented design methodology for designing the INA. The flow chart shown in Fig. 7 explains the same. Accordingly optimal size of main transistors of INA (Fig. 4) are obtained, which are given in Table 2. Bias currents are already shown in Fig. 4.
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referred noise and area. However at the same time differential input voltage range of INA reduces. Therefore, Eq. (1) is used in an iterative manner in the design flow (Fig. 7) to minimize the power for the desired input referred noise level. 3.2. Common mode feedback circuit Since INA output is differential, it uses a common-mode feedback (CMFB) circuit to adjust a proper DC level at the output terminals. The CMFB circuit reported in [15] is designed and implemented on the chip. As CMFB circuit itself has a differential pair configuration at the input its input offset voltage should be low. So, large transistors are used at the input stage to reduce mismatch effects.
3.1.5. Optimal design for area, noise and power Input referred noise of INA, shown in Fig. 4, is given by v2n,in ¼ 2v2n1;4 þ v2RL1 þ
2g 2mI1 g 2L1
v2n,I1 þ
2g 2mI2 g 2L1
v2n,I2 þ
2g m
I32
g 2L1
v2n,I3
ð1Þ
where vn1;4 is the noise contributed by input transistors M1 and M4, vRL1 is noise contributed by resistor RL1, gL1 is 1/RL1 and g mI1 , g mI2 and g mI3 are transconductance of current sources I1 , I2 and I3, respectively. As Eq. (1) shows decreasing RL1 reduces the input
Fig. 7. Flow chart explaining power oriented design methodology of INA (Fig. 4).
Table 2 Size of main components of INA after optimization (Fig. 4).
Fig. 5. Schematic of the implemented Gm1 Gm2 module for high-pass filtering.
Transistor
W ðmmÞ=L ðmmÞ
M1 and M4 Lower transistors of CMRR improvement circuit M2 and M3 RL2 (on-chip) RL1 (on-chip)
72/1 3/2 and 10/2 15/1 200 KO 20 KO
Fig. 6. Simulated programmable high-pass behavior of INA.
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3.3. Spike removal filter
3.4. On-chip clock generator
The main problem of using chopping circuits in on-chip instrumentation amplifier is switching noise at the output of INA due to charge injection and clock feedthrough. To attenuate switching noise SRF stage is used after INA. Generally SRF is made up of PMOS buffer [1–4]. However it has drawback of shifting the DC level of the signal. This limits the voltage swing at the input of the following DC-coupled stage. Since our aim is to use scaled supply voltage levels effect of threshold voltage of the transistors on swing is not negligible. AC-coupled SRF, on the other hand, needs additional on-chip pair of capacitors which adds to the silicon area. To overcome this problem we propose a novel solution in the presented chip as shown in Fig. 8. Here SRF constitutes of PMOS switches connected to the output of differential buffers having high input capacitance and low output impedance. This configuration enables attenuating spikes while maintaining the DC level of the signal at the output. In Fig. 8 PMOS switch is ON when signal srf_clk is low and hence there is no overlapping with spikes at the output of INA and no ACcoupling capacitor is required. Another advantage of differential buffer with SRF is attenuation of charge injection effect of spike removal switch as the output impedance of the buffer used in SRF is small as compared to the RL2 . Fig. 9 shows simulated output of INA with chopper and SRF stage. Plot (d) shows the differential input signal with 20 mV amplitude. Plot (a) shows the chopped (or modulated) and amplified output with gain of 10 V/V. Plot (b) shows the down converted (demodulated) output before SRF stage, which contains coupled spikes due to chopping. Plot (c) presents output of the SRF stage, in which all the spikes have been removed.
For modulating input signals of INA and demodulating output signals of INA two non-overlapping 4 kHz clock phases are required. For controlling the SRF stage an 8 kHz clock having 10% duty cycle is required. A dual-phase and dual-frequency generator is designed and incorporated on the test chip, of which the schematic is shown in Fig. 10. First an 8 kHz clock is produced using a nine-stage ring oscillator made of current starved inverters (Fig. 10). The 4 kHz non-overlapping clock phases and 8 kHz clock with 10% duty cycle are generated from the main 8 kHz clock [15]. 3.5. Programmable gain and bandwidth stage To suit gain and bandwidth requirements of various signals, first order differential active RC filter is designed. The resistor to realize the variable gain and capacitor to adjust the cut off frequency are off-chip components. Minimum gain of 20 provides minimum total gain of 200 for the channel. 3.6. Configurable DRLC (driven right leg circuit) DRLC is a traditional method to reduce the common-mode noise (or interference) voltage on the body, Vcm. DRLC senses the common-mode (or average) voltage of sensed signals and feeds it back to the right leg using a shunt feedback amplifier. Hence the common-mode voltage is attenuated [6,11]. We have implemented a reconfigurable on-chip DRLC as shown in the Fig. 11. R2 and R3 are averaging resistors. As shown in the figure either op-amp or OTA can be selected to drive the right leg using a multiplexer. In the case of op-amp based DRLC increasing gain of feedback
Fig. 8. Schematic of SRF (spike removal filter).
Fig. 10. Schematic of clock generator circuit and current starved inverter.
Fig. 9. Performance of SRF stage.
Fig. 11. Reconfigurable DRLC and shield drive amplifier (both are on-chip).
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amplifier reduces Vcm as given by the following equation [6,10] (id is the induced displacement current on the body): i V cm ¼ Z 3 d R 1 þ R1f
ð2Þ
Since an on-chip DRLC is desired area and power dissipation of DRLC circuit should be minimized. In this regard using OTA to drive the body is far more advantages than using conventional opamp. These advantages are explained as follows. 1. Ease of loop stabilization. As explained in [17] the transfer function between common-mode voltage (Vcm) and power line voltage results into three poles. One pole is present at the input of the buffer due to electrode impedance (Z1, Z2) and parasitic capacitance (C1, C2) as shown in Fig. 1. The second pole is due to the impedance Z3 and equivalent parasitic capacitance of Cp and Cb (Fig. 1). Third pole is due to the impedance Z3 and parasitic capacitances at the op-amp output. However in the case of OTA the output stage is a current source with high output impedance. Therefore, the stability becomes independent of impedance Z3. As a result number of poles reduces to two poles. The detailed analysis is given in [17]. Moreover, due to high output impedance OTA is compensated easily, compared to an op-amp. As a result total area and power consumption of the on-chip DRLC reduces. 2. In case of OTA based DRLC external resistors Rf and R1 are not required, which is important for a fully on-chip DRLC. Folded cascode OTA is used for OTA-based DRLC. Schematic of the OTA is shown in Fig. 12 [15].
Fig. 13. Schematic of op-amp.
3.7. On-chip SDA (shield drive amplifier) Fig. 14. Schematic of on-chip ultra low-noise buffer.
The difference in electrode impedances induces unwanted differential input voltage Vab as shown in Fig. 1. Different shielding techniques have been discussed in [9]. We employ method of guarding with average of single-ended input signals on the test chip. In this method the shields are driven by the average of the input common-mode voltages. Therefore, there is no potential difference between the shield and inner wire which carries the signal. Hence, there is no sensitivity to the interference due to potential divider effect [9]. The SDA op-amp is a rail-to-rail cascode op-amp with 200 mA current drive capability. High current drive capability is needed in order to drive multiple shields depending upon length of the cable. Fig. 11 shows how SDA is deployed on the test chip. The SDA is unity gain amplifier with R2 and R3 as averaging resistors.
3.8. Op-amp Two-stage op-amp with rail to rail output voltage stage, 100 mA output current drive capability and low power dissipation is designed. The op-amp achieves rail to rail output voltage by using class-AB output stage with class-AB control circuit [18]. Fig. 13 shows schematic of the implemented op-amp. M1_op, M2_op, M7_op, M8_op, M9_op and M10_op form the folded cascode stage. M11_op and M16_op form the class AB control circuit. (M14_op, M16_op, I2) and (M17_op, M18_op, I3) bias M11_op and M16_op, respectively. M3_op and M4_op are output transistors, which source (or sink) the current to (or from) the output. They are kept in moderate inversion to reduce the quiescent current and hence, reduce the current consumption. M11_op and M16_op are common gate amplifiers. M3_op and M4_op have relatively large sizes to be able to drive 100 mA output current. The op-amp is frequency compensated using Miller compensation technique [18]. 3.9. Ultra low-noise buffer Two low-noise buffers are kept before instrumentation amplifier [19]. Low-noise buffers are designed by using two stage op-amp configuration [15], of which the schematic is shown in Fig. 14. PMOS transistors are used as input transistors to reduce the input noise level. Large W and L are used to reduce the flicker noise and offset. 4. Measurement results
Fig. 12. Schematic of OTA used in reconfigurable on-chip DRLC.
The entire signal conditioning circuit and drivers are fabricated on a multi-project test chip in 180 nm UMC mixed-mode CMOS
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Fig. 15. Micro-photograph of the chip.
process. Total area of all modules is quite low (only 655 mm 365 mm), as shown in the chip micro-photograph in Fig. 15. The chip is powered with supply voltage of 1.8 V by using two 1.5 V batteries and a DC–DC converter IC. Fig. 16 shows the designed test board with shield box to measure the specifications of the chip. Fig. 17 illustrates the measurement setup used for characterizing the test chip. Fig. 18 shows measured input-referred noise power spectral density (PSD) of the INA with chopper (specified with black color and corresponding to the values on left Y-axis) and without chopper (specified with red color and corresponding to the values on right Y-axis). SR 530 lock-in amplifier is used for precise noise measurement [16]. As shown in the figure there is a significant reduction in PSD of noise for frequencies below 1 kHz (for better clarity different scales are used on Y axes on the left and right pffiffiffiffiffiffiffi side). Measured noise density of INA with chopper is 28 nv= Hz with corner frequency of flicker noise around 4 Hz. Small component of 50 Hz interference and its harmonics which are not clear in chopper-less case due to higher noise level are observed when chopper is activated. Fig. 19(a) and (b) shows the common-mode gain measurement setup and CMRR of the INA, obtained from measurement when chopper is activated, respectively. SR 530 lock-in amplifier is used to measure common-mode gain accurately. CMRR is obtained as ratio of differential gain to common-mode gain. As the value of common-mode gain is below 90 dB it is impossible to measure the amplitude of the output signal due to common-mode input
Fig. 16. Test board.
Fig. 17. Setup for testing the chip.
Fig. 19. (a) CMRR measurement setup and (b) CMRR versus frequency plot.
Fig. 18. Measured input-referred noise density of INA with and without chopper (Y axes have different scales.) (For interpretation of the references to color in this figure caption, the reader is referred to the web version of this article.)
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Fig. 20. PSRR of INA.
Fig. 21. Percentage change in gain of INA as a function of input CM voltage.
Fig. 22. Percentage change in the INA gain as a function of differential input voltage.
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using DSO. Instead lock-in amplifier is used to precisely measure amplitude of signals in the range of micro-volts. A sync signal along with the signal that is being measured is given to the lockin amplifier as shown in Fig. 19(a). Lock-in amplifier displays the amplitude and phase of the output signal at reference input frequency. As Fig. 19(a) presents minimum achieved CMRR is 109 dB at 1.91 kHz which is quite high. Fig. 20 shows the measured PSRR of the INA. SR 530 lock-in amplifier is again used to accurately measure the output signal resulted from a signal imposed on the power supply. Minimum achieved PSRR is 104 dB at 50 Hz, which is due to common-mode interference at 50 Hz. However it is still more than 100 dB. Fig. 21 presents measured values of INA gain with respect to the input common-mode voltage. The INA gain varies maximum by 71.5% as input common-mode voltage changes from 0.7 V to 1.2 V. Fig. 22 shows that the INA gain changes up to only 71.5% in the wide 720 mV differential input voltage range. Fig. 23 shows the output waveform of 4 kHz non-overlapping clock generator (a) and 8 kHz SRF clock generator (b), respectively. They perfectly match the desired frequency and duty cycle. To compare impact of op-amp based and OTA-based DRLC measurements are performed in different cases. Fig. 24 shows the induced 50 Hz interference voltage on the body for these cases. Fig. 24(a) shows the interference voltage on the body without DRLC. The induced peak to peak voltage (Vpp) is 1.72 V which will saturate INA. Fig. 24(b) presents coupled noise to the body when OTA-based DRLC is activated. As shown in the figure Vpp of 50 Hz interference signal is reduced to 35 mV, which is a significant reduction of interference (34 dB). Fig. 24(c) and (d) shows reduced interference by using op-amp based DRLC in unity gain configuration and with gain of 20, respectively. Vpp is best reduced to 62 mV, as compared to 35 mV for OTA-based DRLC. Slight variation of frequency in Fig. 24 is due to variation of mains frequency during measurements. Fig. 25 shows acquired ECG of human body using the test chip. Table 3 shows the differential voltage generated on the body due to potential divider effect, Vab. Vab reduces by 100 times by applying only DRLC. In addition, it reduces 10 times more by applying both DRLC and SDA. As shown in Table 3, 5 mV differential voltage is generated on the body without SDA. This 5 mV might not be the problem in acquiring ECG but will be troublesome for EEG acquisition. Therefore, the differential voltage is further reduced up to 0:5 mV by SDA. Table 4 summarizes measurement results of the operational amplifier, used in DRLC. Table 5 shows measured power pffiffiffiffiffiffidissipaffi tion of every module on the chip. Considering 28 nv= Hz inputreferred noise density while consuming only 5:9 mA by INA and 5:7 mA by clock generator (for chopping) makes the presented
Fig. 23. Output of clock generator (a) 4 kHz clock for chopping and (b) 8 kHz non-overlapping low duty cycle clock for SRF.
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S. Joshi et al. / Microelectronics Journal 43 (2012) 828–837
Fig. 24. Induced interference voltage on the body (a) without DRLC, (b) with OTA based DRLC, (c) with op-amp based DRLC in unity gain configuration and (d) with op-amp based DRLC with gain of 20.
Table 4 Measurement results of operational amplifier. Specification
Measurement result
Open Loop Gain CMRR Unity gain bandwidth Output voltage swing Input common mode range Input referred offset (Across 19 chips)
102 dB 86 dB (100 Hz to 10 kHz) 400 kHz 1.78 Vpp 0.4–1.8 V 7 2.5 mV (max) 7 0.1 mV (min)
Table 5 Power performance of all the modules on the test chip. Fig. 25. Recorded ECG with the analog signal conditioning chip.
Table 3 Coupled differential voltage on the body by potential divider effect. Scenario
Vab (mV)
Without applying DRLC and SDA After applying DRLC After applying DRLC and SDA
500 5 0.5
INA, the best among ultra low-noise and ultra low-power INAs, reported till date, in 180 nm CMOS technology. Performance of the test chip is compared with earlier works in Table 6. As table shows combined superior performance parameters of the test chip, as compared to other works, are low supply voltage (1.8 V), high differential input voltage range 720 mV, low input-referred pffiffiffiffiffiffi ffi noise (28 nv= Hz) and high CMRR (at least 109 dB) and high linearity.
Module
Current consumption (mA)
Instrumentation amplifier SRF stage Active RC op-amp DRLC op-amp Shield drive op-amp DRLC OTA Clock generator Bias generator Low-noise buffer
5.9 4 52.5 52.5 90.8 12.2 5.7 3.7 28.6
Total
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5. Conclusions A low-power, low-voltage and ultra low-noise signal conditioning circuit in 180 nm CMOS process is presented. The test chip is appropriate for conditioning of various biopotential signals. For the first time, an integrated reconfigurable driven-right-leg circuit (DRLC), working either with on-chip OTA or on-chip op-amp, is
S. Joshi et al. / Microelectronics Journal 43 (2012) 828–837
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Table 6 Performance comparison of the presented test chip with earlier works. Parameters
This work
[3]
[4]
[13]
[12]
[1]
Technology (nm) Supply voltage (V) Input dynamic range (mV) Maximum channel gain Input CM range (V) High freq. cutoff (Hz) pffiffiffiffiffiffi Input-referred noise (nv= Hz) CMRR (dB)
180 1.8 7 20 (channel gain¼ 45) 5000 0.7–1.3 Adjustable 28
500 2 N/A 2500 N/A 0.34 60
90 3 N/A 2500 1.05–2.3 0.4 51.4
800 1.7–3.3 N/A N/A N/A Adjustable N/A
350 3.3 12 6 0.3–2.3 N/A N/A
500 3 N/A N/A N/A N/A 85
109 (CMRR ¼120 dB at 50 Hz) 0.016
120
140
80
100
105
N/A
0.1
0.52
N/A
N/A
THD (%)
implemented on the test chip. Measurement results of OTA-based DRLC show better attenuation of the interference signals on the body. DRLC using OTA has also advantage of significant reduction in area and external components. The proposed circuit eliminates 1/f noise effectively in its current feedback INA using chopper modulation. The INA achieves worst case CMRR of 109 dB atffi pffiffiffiffiffiffi 1.91 kHz and input referred voltage noise density of 28 nv= Hz. ECG has been also recorded with the test chip. The test chip has high measured input differential voltage range of 720 mV so that it can be used even for sensor applications like electronic nose or seismic activity detection by geo-phones.
Acknowledgement The authors would like to acknowledge TCS – India for financial support of chip fabrication, SMDP Government of India and VLSI lab IIT – Bombay for providing design tools. The 180 nm UMC model files have been provided by Europractice. References [1] R.F. Yazicioglu, P. Merken, R. Puers, S. Member, C.V. Hoof, A 60 mW pffiffiffiffiffiffi 60 nV= Hz readout front-end for portable biopotential acquisition systems, IEEE J. Solid State Circuits 42 (May (5)) (2007) 1100–1110. [2] R.F. Yazicioglu, T. Torfs, P. Merken, J. Penders, R.P. Vladimir Leonov, B. Gyselinckx, C.V. Hoof, Ultra-low-power biopotential interfaces and their applications in wearable and implantable systems, Microelectron. J. 40 (2009) 1313–1321. [3] R.F. Yazicioglu, S. Kim, T. Torfs, H. Kim, C.V. Hoof, A 30 mW analog signal processor ASIC for portable biopotential signal monitoring, IEEE J. Solid State Circuits 46 (January (1)) (2011) 209–223. [4] C.-T. Ma, P.-I. Mak, M.-I. Vai, P.-U. Mak, S.-H. Pun, W. Feng, R.P. Martins, A 90 nm CMOS bio-potential signal readout front-end with improved powerline interference rejection, in: Proceedings of the IEEE ISCAS, 2009.
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