- Email: [email protected]
SiGe substrates for CMOS and optical devices
Microelectronic Engineering 82 (2005) 215–220 www.elsevier.com/locate/mee
High quality strained Si/SiGe substrates for CMOS and optical devices J. Weber *, L. Nebrich, F. Bensch, K. Neumeier, G. Vogg, R. Wieland, D. Bonfert, P. Ramm Fraunhofer-Institute for Reliability and Microintegration, Munich Division, Hansastraße 27d, 80686 Munich, Germany Available online 15 August 2005
Abstract Using LPCVD epitaxy on 200 mm standard wafers high quality strained Si/SiGe substrates (sSi/SiGe) based on a graded buffer approach have been developed. Physical and chemical analysis of the substrates, show an efficient amount of relaxation of the SiGe buffer and a fully strained silicon cap. Process integration of test devices into the sSi/SiGe layers was performed using a simply modified CMOS process. NMOS and PMOS transistors were integrated together with PIN diodes in a single sSi/SiGe substrate using the same process flow. Electrical measurements showed the enhancement of charge carrier mobility of up to 80% for electrons and 37% for holes compared to epitaxially grown silicon for reference. Also an enhanced photo responsivity at a wavelength of 1310 nm for PIN diodes integrated into the SiGe buffers was demonstrated. Low leakage currents of the PIN diodes conclude good crystal quality of the SiGe buffer layer. 2005 Elsevier B.V. All rights reserved. Keywords: SiGe; Strained Silicon; CMOS; Enhanced mobility; PIN diode
1. Introduction Mismatched heteroepitaxy of semiconductor materials has been an active area of research for more than 30 years. The epitaxial growth of III– * Corresponding author. Tel.: +49 0 89 54759 621; fax: +49 0 89 54759 100. E-mail address: [email protected] (J. Weber).
V semiconductor alloys enables superior high speed performance and efficient optical devices based on the direct bandgap structure and the possibility of engineering the bandgap. Yet III–V semiconductor technology is very cost intensive and limited to smaller wafer diameters compared to standard silicon technology. Heteroepitaxy of SiGe alloys on standard silicon substrates with Ge contents of up to 30% will only cause small changes within established CMOS or bipolar
0167-9317/$ - see front matter 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2005.07.012
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J. Weber et al. / Microelectronic Engineering 82 (2005) 215–220
processes. Due to the lattice mismatch of about 4.17% between Si and Ge strain will be introduced into the sSi/SiGe layer systems. Thin SiGe layers can be grown pseudomorphically (lattice matched) on silicon. The SiGe layer will be strained and dislocation free. Strained SiGe layers selectively grown as the base electrode of HBT devices enhance the performance of transistors [1]. This technique is well established and used in many state-ofthe-art products. In this work, we want to focus on the epitaxial growth of high quality relaxed SiGe buffer layers with a thin strained silicon layer on top. A so called virtual substrate lattice-mismatched with respect to the silicon is grown. A thin silicon layer grown on top of this substrate is tensile strained. Material properties of the strained silicon enhance the performance of CMOS devices. The SiGe buffer layer can also be used for optical applications in the near infrared region [2]. Results of physical and chemical analysis show the relaxation degree of the SiGe buffer layer and the density of threading dislocations introduced by the relaxation process. Electro-optical test devices like NMOS and PMOS transistors as well as PIN diodes, which were integrated using a modified simple CMOS process, are suitable test vehicles for demonstrating increased performance and functionality of the strained silicon/SiGe substrates (sSi/SiGe).
boron implantation n
2. Epitaxial growth and analysis results of the sSi/ SiGe substrate Epitaxial growth of strained silicon and SiGe layers and processing of the test devices was done within the 200 mm CMOS Research and Development line of Fraunhofer IZM, Munich Division. In particular a low temperature CVD-reactor (ASM Epsilon 2000) equipped with different precursors (dichlorsilane, germane and silane) was used. At first relaxed Si1 xGex (x = 0.20, 0.24) buffers of approximately 2 lm thickness were grown with a step grading approach consisting of up to seven layers with successively increasing Ge concentration. Using this graded buffer approach dislocations were pinned at the boundaries of the SiGe layers with different Ge content. The epitaxial growth of the Si1 xGex (x = 0.20, 0.24) buffer was interrupted for building a buried p+ layer formed by a Boron implantation and a subsequent anneal at 900 C in nitrogen. The implanted surface was conditioned by an HF-last wet clean sequence. An additional 2 lm thick Si1 xGex buffer layer was added by carrying on the epitaxial growth. This second SiGe buffer was capped with an 14 nm thick strained Si-film using silane as precursor at 650 C (schematic of the process flow is shown in Fig. 1). Boron implantation and cleaning as described above were also done on prime-
inert anneal oxide etch and surface conditioning second SiGe/Si - epi
scattering oxide undoped relaxed Si1-xGex buffer
undoped SiGe step grading
strained Si
undoped relaxed Si1-xGex buffer p+ - doped undop. rel. Si1-xGex buffer
undoped SiGe step grading
Fig. 1. Schematic of process flow for manufacturing 200 mm sSi/Si1 xGex (x = 0.2; 0.24) substrates with buried p+-doped layer. SiGe and Si were grown by low temperature LPCVD epitaxy using an ASM Epsilon 2000 reactor.
J. Weber et al. / Microelectronic Engineering 82 (2005) 215–220
type Si wafers for reference. Instead of SiGe a 2 lm thick Si layer was epitaxially deposited to compare the electrical and optical device behavior of sSi/SiGe layers with respect to pure silicon. Thickness and Ge content of the SiGe- and strained silicon layers were measured by using UV-spectral ellipsometry (SE) and adapting existing programs to the optical properties of SiGe alloys. This in-line measurement method was cross checked with High Resolution X-ray Diffraction (XRD) measurements and was in good agreement. The relaxation of the Si1 xGex buffer layers and
217
the strain of the Si-cap were determined by use of XRD. Fig. 2 shows the reciprocal space map of the 224 reflection for a sSi/Si0.76Ge0.24 substrate. A 95% relaxation of the Si0.76Ge0.24 buffer layer was calculated from XRD measurement. The top 14 nm thick sSi layer is 100% strained with respect to the relaxed buffer. The quality of sSi/SiGe layers is usually examined using diluted Schimmel etch. This method visualizes the threading dislocations (TD), which are created during the relaxation of the SiGe buffer. Optical inspection with a light microscope of the Schimmel etched samples resulted in a density of TDs of 8 · 105 cm 2 for the sSi/Si0.76Ge0.24 layer and 3 · 105 cm 2 for sSi/Si0.80Ge0.20, respectively. Such values are usually accepted for good device quality substrates.
3. Process integration of test devices
Fig. 2. Reciprocal space map of 224 reflection of sSi/ Si0.76Ge0.24 substrate (result of XRD measurement).
CMOS transistors and PIN diodes on SiGe virtual substrates with strained Si cap and Si reference wafers were manufactured in the same lot. The MOS transistors and PIN diodes were integrated in the strained silicon/Si1 xGex (x = 0.20, 0.24) layers using a CMOS process simply modified for realizing the PIN diode. For connecting the buried p+-layer of the PIN diode a double trench etching process was chosen at the beginning of the standard CMOS flow (Fig. 3). The transistors were realized using a twin-well CMOS process and a low temperature gate stack. The maximum
Fig. 3. SEM micrographs of realized PIN diode: top view of 80 lm long diode structure (left), detailed view on the layer composition of the diode structure and the contact of the buried layer (right).
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J. Weber et al. / Microelectronic Engineering 82 (2005) 215–220
process temperature was 800 C to preserve the strain in the silicon cap. The well profiles were obtained by a fourfold implantation of B and P with different energies and subsequent annealing. For field isolation a low temperature oxide (PE-TEOS) with a thickness of 400 nm was deposited. The gate areas of the transistors were defined by structuring the oxide with a combined dry/wet etch process. Using a LPCVD-TEOS process 30 nm oxide was deposited for gate isolation. A subsequent dry thermal oxidation at 800 C improved the oxide quality. The gate oxide thickness increased to 33 nm due to this thermal oxidation. The strained Si cap thickness decreased from 14 nm to approx. 7 nm due to the process flow. After contact hole etching, a standard metallization Ti/TiN/AlSi1%Cu0.5%/TiN layer system was sputtered. This metallization was used for interconnection and as a gate electrode.
drain current of the transistors in sSi/Si0.76Ge0.24 substrates is distinctly higher than the corresponding drain current of the reference transistors in Si substrate. Transistor transfer characteristics were measured up to the gate oxide breakdown voltage. Regarding oxide thickness and threshold voltage the effective electron and hole mobility and the effective electrical field were calculated as denoted in [3]. Fig. 5 shows the effective mobilities of the charge carriers versus the effective electrical field for transistors with a channel width of 20 lm and channel length of 20 lm. Maximum mobility enhancements of 80% for electrons in NMOS transistors and 37% for holes in PMOS transistors integrated in sSi/ Si1 xGex (x = 0.20, x = 0.24) substrates were demonstrated. The mobility enhancements for both electrons and holes are in good accordance to the results published by Currie et al. [3] for comparable Ge contents of the SiGe layer. PIN diodes with an active area of 12 · 80 lm2 were integrated in the same substrate as the transistors. The reference diodes in epitaxially grown silicon showed a leakage current of some fA at a reverse bias of 1 V, which was within the noise of the measurement system. At this voltage, leakage currents for the measured SiGe PIN diodes amount to less than 0.2 pA. Even at a reverse bias of 15 V the leakage current is below 10 pA for these diodes (Fig. 6). In summary, this concludes a very good crystal quality of the SiGe buffer layers and low additional leakage due to process integration.
4. Electro-optical measurements The characterization of the transistors and PIN diodes was carried out at room temperature on wafer level (Su¨ssMicroTec PA300 waferprober, Agilent 4156B high precision parameter analyzer). Transfer and output characteristics for NMOS and PMOS transistors were measured for different geometries. In Fig. 4 output characteristics of a NMOS and a PMOS transistor are shown. The sSi/Si0.76Ge0.24 Si 450,0µ 400,0µ
Vgs = 5V
350,0µ 300,0µ 250,0µ 200,0µ
Vgs = 4V
150,0µ 100,0µ
-250,0µ
Drain Current Ids (A)
Drain Current Ids (A)
500,0µ
sSi/Si0.76Ge0.24 Si
-200,0µ
Vgs = -6V
-150,0µ
Vgs = -5V
-100,0µ -50,0µ
50,0µ 0,0 0
1
2
3
4
Drain Voltage Vds (V)
5
0,0 0
-1
-2
-3
-4
-5
Drain Voltage Vds (V)
Fig. 4. Output characteristics of NMOS (left) and PMOS (right) transistor (W = L = 20 lm) show enhanced drain current of transistor integrated on sSi/Si0.76Ge0.24 compared to Si reference.
J. Weber et al. / Microelectronic Engineering 82 (2005) 215–220
219
900
sSi/Si0.76Ge0.24
800
sSi/Si0.80Ge0.20 Si
700 600 500 400 300 200
250
µ p,eff (cm2 /(Vs))
µn,eff (cm2 /(Vs))
1000
sSi/Si0.76Ge0.24 sSi/Si0.80Ge0.20
200
Si 150 100 50
100
0 0,2
0 0,2
0,4
0,6
0,8
1,0
1,2
1,4
0,4
Eeff (MV/cm)
0,6
0,8
1,0
Eeff (MV/cm)
Fig. 5. Effective mobilities of electrons (ln, eff) and holes (lp eff) calculated from transfer characteristics of NMOS and PMOS tranistor (W = L = 20 lm) show enhancement of up to 80% for electrons and 37% for holes in sSi/Si1 xGex substrates compared to silicon reference.
1E-9
1E-6 sSi/Si0.76Ge0.24
1E-8
Reverse Current (A)
Reverse Current (A)
1E-7 sSi/Si0.80Ge0.20
1E-9
Si
1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 0
2
4
6
8
10
12
14
16
18
20
1E-10
1E-11 0,0
The PIN diode was illuminated via a multimode optical fiber on wafer level. As illumination source a diode laser with an output power of approx. 2 mW at a wavelength of 1310 nm was used. This wavelength was chosen because it is well established in telecommunication networks but beyond an efficient silicon absorption range. The IV-characteristics in reverse mode of the 80 lm long diode are shown in Fig. 7. Photo currents of Si0.80Ge0.20, Si0.76Ge0.24 and Si reference substrates were measured. Compared to the silicon reference photo diodes the SiGe diodes show almost two orders of magnitude higher photo responsivity.
0,2
0,4
0,6
0,8
1,0
Reverse Voltage (V)
Reverse Voltage (V) Fig. 6. Result of reverse breakdown measurement on PIN diodes (A = 12 · 80 lm2) on Si1 xGex (x = 0.2, 0.24) substrates and Si reference.
sSi/Si0.76Ge0.24 sSi/Si0.80Ge0.20 Si
Fig. 7. Reverse current of PIN diodes (A = 12 · 80 lm2) integrated on Si1 xGex substrates (x = 0.2, 0.24) and Si reference when illuminated with monochromatic laser source (wavelength = 1310 nm).
5. Conclusion We manufactured high quality strained silicon/ SiGe substrates, which were grown on silicon substrates by CVD-epitaxy. Using graded buffer layers for depositing a relaxed Si1 xGex buffer (x = 0.20, 0.24), low defect densities in the range of 105 cm 2 were achieved. Test devices integrated in the sSi/SiGe layers demonstrated an enhanced mobility of the charge carriers in NMOS and PMOS transistors as well as a significantly improved photo responsivity at 1310 nm wavelength compared to identically processed devices inte-
220
J. Weber et al. / Microelectronic Engineering 82 (2005) 215–220
grated in reference silicon material. The sSi/SiGe substrates described in this work can be used for monolithic device integration of improved infrared sensitive photodiodes and high mobility transistors on one substrate, based on standard silicon technology. The potential for low cost manufacturing of fiber optic network circuits and devices based on sSi/SiGe layers epitaxially grown on silicon substrate is given.
Acknowledgements Financial support by BMBF (Grant No. 01M3123) is gratefully acknowledged. We thank
the wafer technology group of Fraunhofer-IZM, Munich Division for manufacturing the electrooptical devices and preparing the samples.
References [1] E. Kasper, A. Gruhle, H. Kibbel, IEEE IEDM Technical Digest (1993) 79–82. [2] G. Wo¨hl, C. Parry, E. Kasper, M. Jutzi, M. Berroth, in: Proceedings of the Second Joint Symposium on Opto- and Microelectronic Devices and Circuits, Stuttgart, Germany, vol. 1, No. 1, 2002, pp. 78–83. [3] M.T. Currie, C.W. Leitz, T.A. Langdo, G. Taraschi, E.A. Fitzgerald, D.A. Antoniadis, J. Vacuum Sci. Technol. B 19 (6) (2001) 2268–2279.
High quality strained Si/SiGe substrates for CMOS and optical devices J. Weber *, L. Nebrich, F. Bensch, K. Neumeier, G. Vogg, R. Wieland, D. Bonfert, P. Ramm Fraunhofer-Institute for Reliability and Microintegration, Munich Division, Hansastraße 27d, 80686 Munich, Germany Available online 15 August 2005
Abstract Using LPCVD epitaxy on 200 mm standard wafers high quality strained Si/SiGe substrates (sSi/SiGe) based on a graded buffer approach have been developed. Physical and chemical analysis of the substrates, show an efficient amount of relaxation of the SiGe buffer and a fully strained silicon cap. Process integration of test devices into the sSi/SiGe layers was performed using a simply modified CMOS process. NMOS and PMOS transistors were integrated together with PIN diodes in a single sSi/SiGe substrate using the same process flow. Electrical measurements showed the enhancement of charge carrier mobility of up to 80% for electrons and 37% for holes compared to epitaxially grown silicon for reference. Also an enhanced photo responsivity at a wavelength of 1310 nm for PIN diodes integrated into the SiGe buffers was demonstrated. Low leakage currents of the PIN diodes conclude good crystal quality of the SiGe buffer layer. 2005 Elsevier B.V. All rights reserved. Keywords: SiGe; Strained Silicon; CMOS; Enhanced mobility; PIN diode
1. Introduction Mismatched heteroepitaxy of semiconductor materials has been an active area of research for more than 30 years. The epitaxial growth of III– * Corresponding author. Tel.: +49 0 89 54759 621; fax: +49 0 89 54759 100. E-mail address: [email protected] (J. Weber).
V semiconductor alloys enables superior high speed performance and efficient optical devices based on the direct bandgap structure and the possibility of engineering the bandgap. Yet III–V semiconductor technology is very cost intensive and limited to smaller wafer diameters compared to standard silicon technology. Heteroepitaxy of SiGe alloys on standard silicon substrates with Ge contents of up to 30% will only cause small changes within established CMOS or bipolar
0167-9317/$ - see front matter 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2005.07.012
216
J. Weber et al. / Microelectronic Engineering 82 (2005) 215–220
processes. Due to the lattice mismatch of about 4.17% between Si and Ge strain will be introduced into the sSi/SiGe layer systems. Thin SiGe layers can be grown pseudomorphically (lattice matched) on silicon. The SiGe layer will be strained and dislocation free. Strained SiGe layers selectively grown as the base electrode of HBT devices enhance the performance of transistors [1]. This technique is well established and used in many state-ofthe-art products. In this work, we want to focus on the epitaxial growth of high quality relaxed SiGe buffer layers with a thin strained silicon layer on top. A so called virtual substrate lattice-mismatched with respect to the silicon is grown. A thin silicon layer grown on top of this substrate is tensile strained. Material properties of the strained silicon enhance the performance of CMOS devices. The SiGe buffer layer can also be used for optical applications in the near infrared region [2]. Results of physical and chemical analysis show the relaxation degree of the SiGe buffer layer and the density of threading dislocations introduced by the relaxation process. Electro-optical test devices like NMOS and PMOS transistors as well as PIN diodes, which were integrated using a modified simple CMOS process, are suitable test vehicles for demonstrating increased performance and functionality of the strained silicon/SiGe substrates (sSi/SiGe).
boron implantation n
2. Epitaxial growth and analysis results of the sSi/ SiGe substrate Epitaxial growth of strained silicon and SiGe layers and processing of the test devices was done within the 200 mm CMOS Research and Development line of Fraunhofer IZM, Munich Division. In particular a low temperature CVD-reactor (ASM Epsilon 2000) equipped with different precursors (dichlorsilane, germane and silane) was used. At first relaxed Si1 xGex (x = 0.20, 0.24) buffers of approximately 2 lm thickness were grown with a step grading approach consisting of up to seven layers with successively increasing Ge concentration. Using this graded buffer approach dislocations were pinned at the boundaries of the SiGe layers with different Ge content. The epitaxial growth of the Si1 xGex (x = 0.20, 0.24) buffer was interrupted for building a buried p+ layer formed by a Boron implantation and a subsequent anneal at 900 C in nitrogen. The implanted surface was conditioned by an HF-last wet clean sequence. An additional 2 lm thick Si1 xGex buffer layer was added by carrying on the epitaxial growth. This second SiGe buffer was capped with an 14 nm thick strained Si-film using silane as precursor at 650 C (schematic of the process flow is shown in Fig. 1). Boron implantation and cleaning as described above were also done on prime-
inert anneal oxide etch and surface conditioning second SiGe/Si - epi
scattering oxide undoped relaxed Si1-xGex buffer
undoped SiGe step grading
strained Si
undoped relaxed Si1-xGex buffer p+ - doped undop. rel. Si1-xGex buffer
undoped SiGe step grading
Fig. 1. Schematic of process flow for manufacturing 200 mm sSi/Si1 xGex (x = 0.2; 0.24) substrates with buried p+-doped layer. SiGe and Si were grown by low temperature LPCVD epitaxy using an ASM Epsilon 2000 reactor.
J. Weber et al. / Microelectronic Engineering 82 (2005) 215–220
type Si wafers for reference. Instead of SiGe a 2 lm thick Si layer was epitaxially deposited to compare the electrical and optical device behavior of sSi/SiGe layers with respect to pure silicon. Thickness and Ge content of the SiGe- and strained silicon layers were measured by using UV-spectral ellipsometry (SE) and adapting existing programs to the optical properties of SiGe alloys. This in-line measurement method was cross checked with High Resolution X-ray Diffraction (XRD) measurements and was in good agreement. The relaxation of the Si1 xGex buffer layers and
217
the strain of the Si-cap were determined by use of XRD. Fig. 2 shows the reciprocal space map of the 224 reflection for a sSi/Si0.76Ge0.24 substrate. A 95% relaxation of the Si0.76Ge0.24 buffer layer was calculated from XRD measurement. The top 14 nm thick sSi layer is 100% strained with respect to the relaxed buffer. The quality of sSi/SiGe layers is usually examined using diluted Schimmel etch. This method visualizes the threading dislocations (TD), which are created during the relaxation of the SiGe buffer. Optical inspection with a light microscope of the Schimmel etched samples resulted in a density of TDs of 8 · 105 cm 2 for the sSi/Si0.76Ge0.24 layer and 3 · 105 cm 2 for sSi/Si0.80Ge0.20, respectively. Such values are usually accepted for good device quality substrates.
3. Process integration of test devices
Fig. 2. Reciprocal space map of 224 reflection of sSi/ Si0.76Ge0.24 substrate (result of XRD measurement).
CMOS transistors and PIN diodes on SiGe virtual substrates with strained Si cap and Si reference wafers were manufactured in the same lot. The MOS transistors and PIN diodes were integrated in the strained silicon/Si1 xGex (x = 0.20, 0.24) layers using a CMOS process simply modified for realizing the PIN diode. For connecting the buried p+-layer of the PIN diode a double trench etching process was chosen at the beginning of the standard CMOS flow (Fig. 3). The transistors were realized using a twin-well CMOS process and a low temperature gate stack. The maximum
Fig. 3. SEM micrographs of realized PIN diode: top view of 80 lm long diode structure (left), detailed view on the layer composition of the diode structure and the contact of the buried layer (right).
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J. Weber et al. / Microelectronic Engineering 82 (2005) 215–220
process temperature was 800 C to preserve the strain in the silicon cap. The well profiles were obtained by a fourfold implantation of B and P with different energies and subsequent annealing. For field isolation a low temperature oxide (PE-TEOS) with a thickness of 400 nm was deposited. The gate areas of the transistors were defined by structuring the oxide with a combined dry/wet etch process. Using a LPCVD-TEOS process 30 nm oxide was deposited for gate isolation. A subsequent dry thermal oxidation at 800 C improved the oxide quality. The gate oxide thickness increased to 33 nm due to this thermal oxidation. The strained Si cap thickness decreased from 14 nm to approx. 7 nm due to the process flow. After contact hole etching, a standard metallization Ti/TiN/AlSi1%Cu0.5%/TiN layer system was sputtered. This metallization was used for interconnection and as a gate electrode.
drain current of the transistors in sSi/Si0.76Ge0.24 substrates is distinctly higher than the corresponding drain current of the reference transistors in Si substrate. Transistor transfer characteristics were measured up to the gate oxide breakdown voltage. Regarding oxide thickness and threshold voltage the effective electron and hole mobility and the effective electrical field were calculated as denoted in [3]. Fig. 5 shows the effective mobilities of the charge carriers versus the effective electrical field for transistors with a channel width of 20 lm and channel length of 20 lm. Maximum mobility enhancements of 80% for electrons in NMOS transistors and 37% for holes in PMOS transistors integrated in sSi/ Si1 xGex (x = 0.20, x = 0.24) substrates were demonstrated. The mobility enhancements for both electrons and holes are in good accordance to the results published by Currie et al. [3] for comparable Ge contents of the SiGe layer. PIN diodes with an active area of 12 · 80 lm2 were integrated in the same substrate as the transistors. The reference diodes in epitaxially grown silicon showed a leakage current of some fA at a reverse bias of 1 V, which was within the noise of the measurement system. At this voltage, leakage currents for the measured SiGe PIN diodes amount to less than 0.2 pA. Even at a reverse bias of 15 V the leakage current is below 10 pA for these diodes (Fig. 6). In summary, this concludes a very good crystal quality of the SiGe buffer layers and low additional leakage due to process integration.
4. Electro-optical measurements The characterization of the transistors and PIN diodes was carried out at room temperature on wafer level (Su¨ssMicroTec PA300 waferprober, Agilent 4156B high precision parameter analyzer). Transfer and output characteristics for NMOS and PMOS transistors were measured for different geometries. In Fig. 4 output characteristics of a NMOS and a PMOS transistor are shown. The sSi/Si0.76Ge0.24 Si 450,0µ 400,0µ
Vgs = 5V
350,0µ 300,0µ 250,0µ 200,0µ
Vgs = 4V
150,0µ 100,0µ
-250,0µ
Drain Current Ids (A)
Drain Current Ids (A)
500,0µ
sSi/Si0.76Ge0.24 Si
-200,0µ
Vgs = -6V
-150,0µ
Vgs = -5V
-100,0µ -50,0µ
50,0µ 0,0 0
1
2
3
4
Drain Voltage Vds (V)
5
0,0 0
-1
-2
-3
-4
-5
Drain Voltage Vds (V)
Fig. 4. Output characteristics of NMOS (left) and PMOS (right) transistor (W = L = 20 lm) show enhanced drain current of transistor integrated on sSi/Si0.76Ge0.24 compared to Si reference.
J. Weber et al. / Microelectronic Engineering 82 (2005) 215–220
219
900
sSi/Si0.76Ge0.24
800
sSi/Si0.80Ge0.20 Si
700 600 500 400 300 200
250
µ p,eff (cm2 /(Vs))
µn,eff (cm2 /(Vs))
1000
sSi/Si0.76Ge0.24 sSi/Si0.80Ge0.20
200
Si 150 100 50
100
0 0,2
0 0,2
0,4
0,6
0,8
1,0
1,2
1,4
0,4
Eeff (MV/cm)
0,6
0,8
1,0
Eeff (MV/cm)
Fig. 5. Effective mobilities of electrons (ln, eff) and holes (lp eff) calculated from transfer characteristics of NMOS and PMOS tranistor (W = L = 20 lm) show enhancement of up to 80% for electrons and 37% for holes in sSi/Si1 xGex substrates compared to silicon reference.
1E-9
1E-6 sSi/Si0.76Ge0.24
1E-8
Reverse Current (A)
Reverse Current (A)
1E-7 sSi/Si0.80Ge0.20
1E-9
Si
1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 0
2
4
6
8
10
12
14
16
18
20
1E-10
1E-11 0,0
The PIN diode was illuminated via a multimode optical fiber on wafer level. As illumination source a diode laser with an output power of approx. 2 mW at a wavelength of 1310 nm was used. This wavelength was chosen because it is well established in telecommunication networks but beyond an efficient silicon absorption range. The IV-characteristics in reverse mode of the 80 lm long diode are shown in Fig. 7. Photo currents of Si0.80Ge0.20, Si0.76Ge0.24 and Si reference substrates were measured. Compared to the silicon reference photo diodes the SiGe diodes show almost two orders of magnitude higher photo responsivity.
0,2
0,4
0,6
0,8
1,0
Reverse Voltage (V)
Reverse Voltage (V) Fig. 6. Result of reverse breakdown measurement on PIN diodes (A = 12 · 80 lm2) on Si1 xGex (x = 0.2, 0.24) substrates and Si reference.
sSi/Si0.76Ge0.24 sSi/Si0.80Ge0.20 Si
Fig. 7. Reverse current of PIN diodes (A = 12 · 80 lm2) integrated on Si1 xGex substrates (x = 0.2, 0.24) and Si reference when illuminated with monochromatic laser source (wavelength = 1310 nm).
5. Conclusion We manufactured high quality strained silicon/ SiGe substrates, which were grown on silicon substrates by CVD-epitaxy. Using graded buffer layers for depositing a relaxed Si1 xGex buffer (x = 0.20, 0.24), low defect densities in the range of 105 cm 2 were achieved. Test devices integrated in the sSi/SiGe layers demonstrated an enhanced mobility of the charge carriers in NMOS and PMOS transistors as well as a significantly improved photo responsivity at 1310 nm wavelength compared to identically processed devices inte-
220
J. Weber et al. / Microelectronic Engineering 82 (2005) 215–220
grated in reference silicon material. The sSi/SiGe substrates described in this work can be used for monolithic device integration of improved infrared sensitive photodiodes and high mobility transistors on one substrate, based on standard silicon technology. The potential for low cost manufacturing of fiber optic network circuits and devices based on sSi/SiGe layers epitaxially grown on silicon substrate is given.
Acknowledgements Financial support by BMBF (Grant No. 01M3123) is gratefully acknowledged. We thank
the wafer technology group of Fraunhofer-IZM, Munich Division for manufacturing the electrooptical devices and preparing the samples.
References [1] E. Kasper, A. Gruhle, H. Kibbel, IEEE IEDM Technical Digest (1993) 79–82. [2] G. Wo¨hl, C. Parry, E. Kasper, M. Jutzi, M. Berroth, in: Proceedings of the Second Joint Symposium on Opto- and Microelectronic Devices and Circuits, Stuttgart, Germany, vol. 1, No. 1, 2002, pp. 78–83. [3] M.T. Currie, C.W. Leitz, T.A. Langdo, G. Taraschi, E.A. Fitzgerald, D.A. Antoniadis, J. Vacuum Sci. Technol. B 19 (6) (2001) 2268–2279.