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Implementation and low speed test of ultra-fast interface circuits for Josephson-CMOS hybrid memories
Physica C 392–396 (2003) 1467–1471 www.elsevier.com/locate/physc
Implementation and low speed test of ultra-fast interface circuits for Josephson-CMOS hybrid memories K. Fujiwara a, H. Miyakawa a, N. Yoshikawa a,*, Y. Feng b, S.R. Whiteley b, T. Van Duzer b a
b
Department of Electrical and Computer Engineering, Yokohama National University, Tokiwadai 79-5, Hodogaya-ku, Yokohama 240-8501, Japan Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720-1770, USA Received 13 November 2002; accepted 31 January 2003
Abstract We have been developing Josephson-CMOS hybrid memories where high-density CMOS devices are used as storage cells. One of the key components in the system is the interface circuit, which amplifies the signal from the SFQ circuits into voltage level processible in the CMOS circuits at high-speed. In this paper, we have implemented the ultra-fast interface circuit, which is composed of a Josephson driver and a Josephson-CMOS hybrid amplifier. The propagation delay of the ultra-fast interface circuit is estimated to be about 60 ps assuming a 2.5 kA/cm2 Nb process and a 0.6 lm CMOS process. A low speed test results of the interface circuit shows that it amplifies the input voltage of 80 lV to 0.9 V. We have also investigated their propagation delay and output voltage swing assuming the spread of the critical current in the Josephson stack. Ó 2003 Elsevier B.V. All rights reserved. PACS: 85.25.Hv; 85.25.Na; 85.40.Bh Keywords: SFQ; Hybrid; Interface; Memory
1. Introduction Recently RSFQ circuits have been developed widely because of their clear advantage over CMOS circuits in terms of speed and power dissipation [1]. However, the lack of a high-density and high-speed memory is a serious problem for
*
Corresponding author. Tel.: +81-45-339-4259; fax: +81-45338-1157. E-mail address: [email protected] (N. Yoshikawa).
realization of large-scale digital systems such as the high-end SFQ server. A Josephson-CMOS hybrid memory is one candidate to overcome this drawback [2,3]. In this system, a memory cell array and address decoders are made of high-density CMOS devices and superconducting gates are used as sense amplifiers to reduce the access time and power dissipation. Our previous study has shown that the access time of a 64 kB memory system is estimated to be less than 1 ns [3]. JosephsonCMOS interface circuits are one of the key components in this system. In this paper, we will show
0921-4534/$ - see front matter Ó 2003 Elsevier B.V. All rights reserved. doi:10.1016/S0921-4534(03)00746-9
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K. Fujiwara et al. / Physica C 392–396 (2003) 1467–1471
the design details of the ultra-fast interface circuits and their test results at low speed. We will also show influence of the spread of critical current on their performance.
2. Ultra-fast interface circuit In the Josephson-CMOS hybrid memory system, the performance of the interface circuit considerably affects the whole system performance. The interface circuits have to amplify the small signals from the SFQ circuits to the voltage level processible in the CMOS circuits at high speed. In order to achieve the data rate of several gigahertz in the interface circuits, we have been developing the ultra-fast interface circuit composed of a Josephson driver and a Josephson-CMOS hybrid amplifier [3,4]. Fig. 1 shows a circuit diagram of the ultra-fast interface circuit. The Josephson driver is a parallel circuit of two 10-Josephson junction stacks [5,6]. The Josephson-CMOS hybrid amplifier is composed of three MOS devices and a 400-Josephson junction stack. In operation, first, SFQ signals are amplified to mV level DC voltage by a Josephson gate, such as a 4JL gate, which is not shown in the figure. Next, the Josephson driver increases the input signal into VJdout of about 30 mV. Then the
Josephson-CMOS hybrid amplifier generates 1 V level output voltage swing DVout . Operation of the Josephson-CMOS hybrid amplifier is as follows: By applying Vphi into M2 and M3 at first, M2 and M3 goes to on and off states, respectively. M1 is set to the operating point near the threshold by adjusting Vbias so as to get the high-voltage gain. Then, when Vin is applied by the Josephson driver, current Id of M1 increases by gm DVin , where gm is the transconductance of M1. If Id exceeds the critical current of the Josephson junctions, the Josephson stack rapidly goes to the voltage state, resulting in the sudden drop of the output voltage. As the Josephson stack behaves as an ideal current-source load for the MOS device M1, high-speed circuit operation is possible. When Vphi goes to zero, M3 turns on and resets the Josephson stack into the zero-voltage state. We have simulated the transient response of the Josephson-CMOS hybrid amplifier using HSPICE, where we assumed the NEC standard 2.5 kA/cm2 Nb process and the ROHM 0.25 lm CMOS process. The following circuit parameters were used in the calculation: M1 width ¼ 58 lm, M2 width ¼ 20 lm, M3 width ¼ 5:4 lm, critical current Ic ¼ 550 lA, and load capacitance C0 ¼ 10 fF. Fig. 2 shows a simulation result of the Josephson-CMOS hybrid amplifier. One can see that output voltage swing of 1.2 V is obtained when Vin ¼ 30 mV, which is sufficient to drive
Vdd N junction stack
1.6
M3
Id
1.2
VJDdd Ib C0
Vout
M2 R Vbias
Voltage (V)
Vphi
VJDout Vin
Vout
1.4
Vphi
1 0.8 0.6 0.4
M1 Josephson-CMOS Hybrid Amp
0.2
Vin
0
VJDin
2200
R Josephson Driver Fig. 1. A circuit schematic of the ultra-fast interface circuit.
2250
2300
2350
2400
2450
2500
2550
2600
Time (ps) Fig. 2. A simulated transient response of the Josephson-CMOS hybrid amplifier.
K. Fujiwara et al. / Physica C 392–396 (2003) 1467–1471
3. Test results 3.1. Josephson-CMOS hybrid amplifier Fig. 3 shows a low speed test result of the Josephson-CMOS hybrid amplifier at 4.2 K. The circuit parameters used in this test are as follows: M1 width ¼ 100 lm, M2 width ¼ 20 lm, M3 width ¼ 10 lm, and critical current Ic ¼ 400 lA. In the test, two separate chips, an NEC 2.5 kA/cm2 SFQ chip and a ROHM 0.6 lm CMOS chip are mounted on the same chip holder and connected each other by using bonding wires. In Fig. 3, one can see that 1.2 V voltage drop in Vout is obtained by applying small input voltage Vin . It can be also seen that Vout is reset when Vphi is turned off. Fig. 4 is the dependence of the output voltage swing DVout on the input voltage Vin for the various source voltages Vdd . The figure shows that the output voltage swing of 1.0 V is obtained when Vin ¼ 30 mV.
Fig. 3. Low speed test results of the Josephson-CMOS hybrid amplifier.
2000
1500
∆Vout (mV)
CMOS devices of next stage. The propagation delay, the time Vout requires to fall from 1.5 to 1.0 V, is around 45 ps. It should be noted here that if a P-MOS device is used as a load register instead of the Josephson stack, three times larger input voltage (90 mV) is necessary to obtain the same output voltage swing. In this case, the propagation delay is estimated to be about 150 ps. This shows that the Josephson stack is effective to increase the circuit performance.
1469
Vdd=3.0(V) Vdd=2.5(V) Vdd=1.6(V)
Sample #2
1000
500
0 0
50
100
150
200
Vin (mV) Fig. 4. Dependence of the output voltage of the JosephsonCMOS hybrid amplifier on the input voltages.
3.2. Ultra-fast interface circuit We have also tested, at low speed, the operation of the whole ultra-fast interface circuit in which the output of the Josephson dual-stack driver is directly connected to the Josephson-CMOS hybrid amplifier. Fig. 5 shows test results of the ultra-fast interface circuit. The circuit parameters of the Josephson driver is as follows: R ¼ 1 X and Ic ¼ 250 lA. The DC bias voltage Vbias was added between the Josephson driver and the JosephsonCMOS hybrid amplifier by using the battery to reduce input noise. One can see from the figure that the voltage drop in Vout of about 0.9 V is
Fig. 5. Low speed test results of the ultra-fast interface circuit composed of the Josephson driver and the Josephson-CMOS hybrid amplifier.
K. Fujiwara et al. / Physica C 392–396 (2003) 1467–1471
obtained by applying the input voltage VJDin ¼ 4 mV. Since 50-X series resistor is connected to the input of the Josephson driver, the actual input voltage is 80 lV. It should be noted that a small voltage drop appears in Vout when Vphi is applied. This is due to the unexpected switching of several Josephson junctions by Vphi .
200
Propagation Delay (ps)
1470
160
3σ = 0.25 120
3σ = 0.05
80
3σ = 0
4. Influence of parameter variations and parasitic terms
40 0.78
0.77
0.79
0.8
0.81
Since the variation of Ic in the 400-Josephson stack junctions seems to strongly affect the performance of the Josephson-CMOS hybrid amplifier, we have investigated the influence of the Ic spread on the propagation delay and the output voltage. In calculation, Ic values in the Josephson stack are randomly varied according to the Gaussian distribution function. Fig. 6(a) shows dependences of the propagation delay of the Josephson-CMOS hybrid amplifier on the bias voltage Vbias for various 3r Ic spreads. Fig. 6(b) shows the dependence of the output voltage swing on the 3r Ic spread. It can be seen that the propagation delay and the output voltage swing tend to get worse with increase of the 3r Ic spread. Therefore, the 3r Ic spread should be less than 5% to maintain the circuit performance. We have also investigated the influence of parasitic inductance and capacitance on the circuit performance. If we assume that the total parasitic inductance of the Josephson stack, which is connected serialy with the Josephson stack, is about 2 nH (1 nH from bonding wires and 1 nH from the 400-Josephson junction array) and the parasitic capacitance, which is added to C0 , is about 50 fF, the propagation delay of the hybrid amplifier is estimated to be 113 ps. In the calculation of the parasitic terms we assumed that the ground plane under the Josephson stack is removed to reduce the parasitic capacitance.
memory system, which is composed of the Josephson driver and the Josephson-CMOS hybrid amplifier. Low speed test results showed that it amplifies the input voltage of 80 lV to 0.9 V. The simulation results indicated that the 3r Ic spread should be less than 5% and small parasitic terms are important to achieve the high circuit performance.
5. Conclusion
Acknowledgements
We have implemented and tested the ultra-fast interface circuit for the Josephson-CMOS hybrid
A part of this work was performed through Special Coordination Funds for promoting Sci-
Bias Voltage Vbias (V)
(a) 1.2
∆Vout (V)
1 0.8 0.6 0.4 0.2 0 -0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
(b) Fig. 6. (a) Dependence of the propagation delay of the Josephson-CMOS hybrid amplifier on bias voltage for various 3r Ic spreads. (b) Dependence of the maximum output voltage swing of the Josephson-CMOS hybrid amplifier on the 3r of Ic spread.
K. Fujiwara et al. / Physica C 392–396 (2003) 1467–1471
ence and Technology of the MEXT. The CMOS chip is made cooperated with RHOM Co., Ltd. through the intermediary of Tokyo University Large Scale Integrated System Design Education Research Center. References [1] K.K. Likharev, V.K. Semenov, IEEE Trans. Appl. Supercond. 1 (1991) 1.
1471
[2] U. Ghoshal, D. Hebert, T. Van Duzer, 1993 ISSCC Digest of Technical Papers, vol. 33, February 1993, p. 54. [3] Y.J. Feng, X. Meng, S.R. Whiteley, T. Van Duzer, H. Miyakawa, K. Fujiwara, N.Yoshikawa, IEEE Trans. Appl. Supercond., to be published. [4] U. Ghoshal, S.V. Kishore, A.R. Feldman, L. Huynh, T. Van Duzer, IEEE Trans. Appl. Supercond. 5 (1995) 2640. [5] H. Suzuki, T. Imamura, S. Hasuo, IEEE Trans. Electron Dev. 37 (1990) 2399. [6] N. Harada, A. Yoshida, N. Yokoyama, IEEE Trans. Appl. Supercond. 12 (2002) 1852.
Implementation and low speed test of ultra-fast interface circuits for Josephson-CMOS hybrid memories K. Fujiwara a, H. Miyakawa a, N. Yoshikawa a,*, Y. Feng b, S.R. Whiteley b, T. Van Duzer b a
b
Department of Electrical and Computer Engineering, Yokohama National University, Tokiwadai 79-5, Hodogaya-ku, Yokohama 240-8501, Japan Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720-1770, USA Received 13 November 2002; accepted 31 January 2003
Abstract We have been developing Josephson-CMOS hybrid memories where high-density CMOS devices are used as storage cells. One of the key components in the system is the interface circuit, which amplifies the signal from the SFQ circuits into voltage level processible in the CMOS circuits at high-speed. In this paper, we have implemented the ultra-fast interface circuit, which is composed of a Josephson driver and a Josephson-CMOS hybrid amplifier. The propagation delay of the ultra-fast interface circuit is estimated to be about 60 ps assuming a 2.5 kA/cm2 Nb process and a 0.6 lm CMOS process. A low speed test results of the interface circuit shows that it amplifies the input voltage of 80 lV to 0.9 V. We have also investigated their propagation delay and output voltage swing assuming the spread of the critical current in the Josephson stack. Ó 2003 Elsevier B.V. All rights reserved. PACS: 85.25.Hv; 85.25.Na; 85.40.Bh Keywords: SFQ; Hybrid; Interface; Memory
1. Introduction Recently RSFQ circuits have been developed widely because of their clear advantage over CMOS circuits in terms of speed and power dissipation [1]. However, the lack of a high-density and high-speed memory is a serious problem for
*
Corresponding author. Tel.: +81-45-339-4259; fax: +81-45338-1157. E-mail address: [email protected] (N. Yoshikawa).
realization of large-scale digital systems such as the high-end SFQ server. A Josephson-CMOS hybrid memory is one candidate to overcome this drawback [2,3]. In this system, a memory cell array and address decoders are made of high-density CMOS devices and superconducting gates are used as sense amplifiers to reduce the access time and power dissipation. Our previous study has shown that the access time of a 64 kB memory system is estimated to be less than 1 ns [3]. JosephsonCMOS interface circuits are one of the key components in this system. In this paper, we will show
0921-4534/$ - see front matter Ó 2003 Elsevier B.V. All rights reserved. doi:10.1016/S0921-4534(03)00746-9
1468
K. Fujiwara et al. / Physica C 392–396 (2003) 1467–1471
the design details of the ultra-fast interface circuits and their test results at low speed. We will also show influence of the spread of critical current on their performance.
2. Ultra-fast interface circuit In the Josephson-CMOS hybrid memory system, the performance of the interface circuit considerably affects the whole system performance. The interface circuits have to amplify the small signals from the SFQ circuits to the voltage level processible in the CMOS circuits at high speed. In order to achieve the data rate of several gigahertz in the interface circuits, we have been developing the ultra-fast interface circuit composed of a Josephson driver and a Josephson-CMOS hybrid amplifier [3,4]. Fig. 1 shows a circuit diagram of the ultra-fast interface circuit. The Josephson driver is a parallel circuit of two 10-Josephson junction stacks [5,6]. The Josephson-CMOS hybrid amplifier is composed of three MOS devices and a 400-Josephson junction stack. In operation, first, SFQ signals are amplified to mV level DC voltage by a Josephson gate, such as a 4JL gate, which is not shown in the figure. Next, the Josephson driver increases the input signal into VJdout of about 30 mV. Then the
Josephson-CMOS hybrid amplifier generates 1 V level output voltage swing DVout . Operation of the Josephson-CMOS hybrid amplifier is as follows: By applying Vphi into M2 and M3 at first, M2 and M3 goes to on and off states, respectively. M1 is set to the operating point near the threshold by adjusting Vbias so as to get the high-voltage gain. Then, when Vin is applied by the Josephson driver, current Id of M1 increases by gm DVin , where gm is the transconductance of M1. If Id exceeds the critical current of the Josephson junctions, the Josephson stack rapidly goes to the voltage state, resulting in the sudden drop of the output voltage. As the Josephson stack behaves as an ideal current-source load for the MOS device M1, high-speed circuit operation is possible. When Vphi goes to zero, M3 turns on and resets the Josephson stack into the zero-voltage state. We have simulated the transient response of the Josephson-CMOS hybrid amplifier using HSPICE, where we assumed the NEC standard 2.5 kA/cm2 Nb process and the ROHM 0.25 lm CMOS process. The following circuit parameters were used in the calculation: M1 width ¼ 58 lm, M2 width ¼ 20 lm, M3 width ¼ 5:4 lm, critical current Ic ¼ 550 lA, and load capacitance C0 ¼ 10 fF. Fig. 2 shows a simulation result of the Josephson-CMOS hybrid amplifier. One can see that output voltage swing of 1.2 V is obtained when Vin ¼ 30 mV, which is sufficient to drive
Vdd N junction stack
1.6
M3
Id
1.2
VJDdd Ib C0
Vout
M2 R Vbias
Voltage (V)
Vphi
VJDout Vin
Vout
1.4
Vphi
1 0.8 0.6 0.4
M1 Josephson-CMOS Hybrid Amp
0.2
Vin
0
VJDin
2200
R Josephson Driver Fig. 1. A circuit schematic of the ultra-fast interface circuit.
2250
2300
2350
2400
2450
2500
2550
2600
Time (ps) Fig. 2. A simulated transient response of the Josephson-CMOS hybrid amplifier.
K. Fujiwara et al. / Physica C 392–396 (2003) 1467–1471
3. Test results 3.1. Josephson-CMOS hybrid amplifier Fig. 3 shows a low speed test result of the Josephson-CMOS hybrid amplifier at 4.2 K. The circuit parameters used in this test are as follows: M1 width ¼ 100 lm, M2 width ¼ 20 lm, M3 width ¼ 10 lm, and critical current Ic ¼ 400 lA. In the test, two separate chips, an NEC 2.5 kA/cm2 SFQ chip and a ROHM 0.6 lm CMOS chip are mounted on the same chip holder and connected each other by using bonding wires. In Fig. 3, one can see that 1.2 V voltage drop in Vout is obtained by applying small input voltage Vin . It can be also seen that Vout is reset when Vphi is turned off. Fig. 4 is the dependence of the output voltage swing DVout on the input voltage Vin for the various source voltages Vdd . The figure shows that the output voltage swing of 1.0 V is obtained when Vin ¼ 30 mV.
Fig. 3. Low speed test results of the Josephson-CMOS hybrid amplifier.
2000
1500
∆Vout (mV)
CMOS devices of next stage. The propagation delay, the time Vout requires to fall from 1.5 to 1.0 V, is around 45 ps. It should be noted here that if a P-MOS device is used as a load register instead of the Josephson stack, three times larger input voltage (90 mV) is necessary to obtain the same output voltage swing. In this case, the propagation delay is estimated to be about 150 ps. This shows that the Josephson stack is effective to increase the circuit performance.
1469
Vdd=3.0(V) Vdd=2.5(V) Vdd=1.6(V)
Sample #2
1000
500
0 0
50
100
150
200
Vin (mV) Fig. 4. Dependence of the output voltage of the JosephsonCMOS hybrid amplifier on the input voltages.
3.2. Ultra-fast interface circuit We have also tested, at low speed, the operation of the whole ultra-fast interface circuit in which the output of the Josephson dual-stack driver is directly connected to the Josephson-CMOS hybrid amplifier. Fig. 5 shows test results of the ultra-fast interface circuit. The circuit parameters of the Josephson driver is as follows: R ¼ 1 X and Ic ¼ 250 lA. The DC bias voltage Vbias was added between the Josephson driver and the JosephsonCMOS hybrid amplifier by using the battery to reduce input noise. One can see from the figure that the voltage drop in Vout of about 0.9 V is
Fig. 5. Low speed test results of the ultra-fast interface circuit composed of the Josephson driver and the Josephson-CMOS hybrid amplifier.
K. Fujiwara et al. / Physica C 392–396 (2003) 1467–1471
obtained by applying the input voltage VJDin ¼ 4 mV. Since 50-X series resistor is connected to the input of the Josephson driver, the actual input voltage is 80 lV. It should be noted that a small voltage drop appears in Vout when Vphi is applied. This is due to the unexpected switching of several Josephson junctions by Vphi .
200
Propagation Delay (ps)
1470
160
3σ = 0.25 120
3σ = 0.05
80
3σ = 0
4. Influence of parameter variations and parasitic terms
40 0.78
0.77
0.79
0.8
0.81
Since the variation of Ic in the 400-Josephson stack junctions seems to strongly affect the performance of the Josephson-CMOS hybrid amplifier, we have investigated the influence of the Ic spread on the propagation delay and the output voltage. In calculation, Ic values in the Josephson stack are randomly varied according to the Gaussian distribution function. Fig. 6(a) shows dependences of the propagation delay of the Josephson-CMOS hybrid amplifier on the bias voltage Vbias for various 3r Ic spreads. Fig. 6(b) shows the dependence of the output voltage swing on the 3r Ic spread. It can be seen that the propagation delay and the output voltage swing tend to get worse with increase of the 3r Ic spread. Therefore, the 3r Ic spread should be less than 5% to maintain the circuit performance. We have also investigated the influence of parasitic inductance and capacitance on the circuit performance. If we assume that the total parasitic inductance of the Josephson stack, which is connected serialy with the Josephson stack, is about 2 nH (1 nH from bonding wires and 1 nH from the 400-Josephson junction array) and the parasitic capacitance, which is added to C0 , is about 50 fF, the propagation delay of the hybrid amplifier is estimated to be 113 ps. In the calculation of the parasitic terms we assumed that the ground plane under the Josephson stack is removed to reduce the parasitic capacitance.
memory system, which is composed of the Josephson driver and the Josephson-CMOS hybrid amplifier. Low speed test results showed that it amplifies the input voltage of 80 lV to 0.9 V. The simulation results indicated that the 3r Ic spread should be less than 5% and small parasitic terms are important to achieve the high circuit performance.
5. Conclusion
Acknowledgements
We have implemented and tested the ultra-fast interface circuit for the Josephson-CMOS hybrid
A part of this work was performed through Special Coordination Funds for promoting Sci-
Bias Voltage Vbias (V)
(a) 1.2
∆Vout (V)
1 0.8 0.6 0.4 0.2 0 -0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
(b) Fig. 6. (a) Dependence of the propagation delay of the Josephson-CMOS hybrid amplifier on bias voltage for various 3r Ic spreads. (b) Dependence of the maximum output voltage swing of the Josephson-CMOS hybrid amplifier on the 3r of Ic spread.
K. Fujiwara et al. / Physica C 392–396 (2003) 1467–1471
ence and Technology of the MEXT. The CMOS chip is made cooperated with RHOM Co., Ltd. through the intermediary of Tokyo University Large Scale Integrated System Design Education Research Center. References [1] K.K. Likharev, V.K. Semenov, IEEE Trans. Appl. Supercond. 1 (1991) 1.
1471
[2] U. Ghoshal, D. Hebert, T. Van Duzer, 1993 ISSCC Digest of Technical Papers, vol. 33, February 1993, p. 54. [3] Y.J. Feng, X. Meng, S.R. Whiteley, T. Van Duzer, H. Miyakawa, K. Fujiwara, N.Yoshikawa, IEEE Trans. Appl. Supercond., to be published. [4] U. Ghoshal, S.V. Kishore, A.R. Feldman, L. Huynh, T. Van Duzer, IEEE Trans. Appl. Supercond. 5 (1995) 2640. [5] H. Suzuki, T. Imamura, S. Hasuo, IEEE Trans. Electron Dev. 37 (1990) 2399. [6] N. Harada, A. Yoshida, N. Yokoyama, IEEE Trans. Appl. Supercond. 12 (2002) 1852.