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Improvement of the multi-level cell performance by a soft program method in flash memory devices
Solid-State Electronics 94 (2014) 86–90
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Improvement of the multi-level cell performance by a soft program method in flash memory devices Jong Kyung Park a, Ki-Hong Lee b, Seung Ho Pyi b, Seok-Hee Lee a,b, Byung Jin Cho a,⇑ a b
Dept. of Electrical Engineering, KAIST, 335 Gwahak-ro, Yuseong-gu, Daejeon 305-701, Republic of Korea SK Hynix Semiconductor Incorporated, Bubal-eup, Icheon-si, Gyeonggi-do 467-701, Republic of Korea
a r t i c l e
i n f o
Article history: Received 13 August 2013 Received in revised form 4 February 2014 Accepted 26 February 2014 Available online 19 March 2014 The review of this paper was arranged by Prof. A. Zaslavsky
a b s t r a c t A soft program method is proposed for charge-trap flash (CTF) memory devices. By adding a subsequent small positive gate pulse after main Fowler–Nordheim (FN) injection programming, early charge loss is greatly reduced. The multi-level cell performance as well as the initial flat-band voltage (VFB) instability can thereby be improved by removing the trapped electrons at the shallow traps in the blocking oxide layer. The proposed soft program method is a simple but very effective way to improve the fast retention property without changing the memory structure, especially for cases where the j-value of the blocking oxide is high. Ó 2014 Elsevier Ltd. All rights reserved.
Keywords: Reliability Soft program TANOS Blocking oxide
1. Introduction As a means of overcoming the severe scaling limitations of floating gate (FG) type Flash memory devices, the development of charge trap type Flash (CTF) devices has been accelerated due to their better scalability [1–3]. However, the inferior data retention property caused by the complex nature of charge trapping has been one of the main obstacles blocking the entry of CTF devices into the mainstream of Flash memory mass production [4–6]. Recently, as alternative approaches to overcome this challenge, new programming methods have been suggested for improving the retention property in CTF devices. Lue et al. proposed the so-called ‘refill method’ in nonvolatile read only memory (NROM) devices [7,10]. For program operation of the NROM device, the channel hot electron (CHE) method is usually used to locally inject electrons from the channel near the source or drain junction for 2bit/cell operation. However, since the electrons injected by the CHE method mainly occupy shallow trap levels in the nitride trapping layer, the charge loss becomes severe, especially at high temperatures [8]. To overcome this problem, Lue et al. suggested the ‘refill method’, which repeats the sequence of the CHE program followed by short negative pulses for Fowler–Nordheim (FN) tunneling several times to eject electrons from the shallow traps in nitride ⇑ Corresponding author. Tel.: +82 42 350 3485; fax: +82 42 350 8565. E-mail address: [email protected] (B.J. Cho). http://dx.doi.org/10.1016/j.sse.2014.02.012 0038-1101/Ó 2014 Elsevier Ltd. All rights reserved.
[9,10]. The refill method can modify the electron trap energy spectrum into deeper energy levels and thereby improve the retention property. However, this method is not very effective for devices using FN tunneling injection programming, which is the main programming mechanism in modern CTF devices such as TANOS (TaN/ Al2O3/Si3N4/SiO2/Si) devices [10]. This is because the electrons from FN programming initially fill the relatively deep energy levels in the nitride trapping layer. On the other hand, in TANOS devices, the high-j blocking layer has been identified to be the one which causes early stage threshold voltage (VT) instability and retention degradation due to charge trapping/detrapping and carrier leakage [11,12]. Moreover, the fast detrapping of bulk trapped charges during program operation in the high-j blocking oxide can contribute to early stage charge loss by the internal electric field and thereby threatens the multi-level cell (MLC) performance [13]. In this work, we propose a new program method, referred to as the soft program method, which can reduce the fast charge loss of TANOS devices under the retention state, and thereby improve the early stage VT instability and the MLC performance. 2. Experimental Typical TANOS devices were fabricated on a p-type Si substrate. After standard gate pre-cleaning, a 4.5 nm thick thermal SiO2 tunnel oxide was grown on the substrate, and a 6 nm thick Si3N4 charge-trapping layer was deposited by low-pressure chemical
J.K. Park et al. / Solid-State Electronics 94 (2014) 86–90
vapor deposition (LPCVD) on the SiO2 layer. For the blocking oxide, the experimental splits were designed for evaluating the soft program method systematically. Two different kinds of materials, Al2O3 and LaAlOx (with 2% La), were prepared for the blocking oxide by an atomic layer deposition (ALD) process. The 2% LaLaAlOx has a dielectric constant of 13 [14]. The thickness of the LaAlOx and Al2O3 layers was 14 and 12 nm, respectively, so that the equivalent oxide thickness (EOT) of the entire gate stack is similar (11.9 and 11.7 nm). The process conditions for the sample preparation and memory performance of the two devices are described in detail in Ref. [14]. In TANOS devices, the device performance is reported to be significantly affected by the postdeposition annealing (PDA) process conditions [14,15]. In this experiment, all the samples were annealed in a N2 ambient at 1000 °C for 30 s for fair comparison. After post-deposition annealing, a TaN metal layer was deposited by reactive sputtering and then patterned to form gate electrodes. Post-implantation annealing was conducted at 900 °C for 30 s. Forming gas annealing was performed at 420 °C for 30 min in a N2/H2 ambient. CTF memory cell capacitors were patterned with a gate length/width of 100 lm/100 lm for evaluating the memory performance. The FN tunneling method was used to program or erase the Flash memory cells.
3. Results and discussion Fig. 1(a and b) shows the conventional programming method and the new soft programming method proposed in this work, respectively. In the conventional programming method, incremental step pulse programming (ISPP) is the most widely used method to maintain a tight cell VT distribution for high reliability and multi-level cell (MLC) applications [16,17]. The ISPP method consists of several program and verification steps, and gradually increases the
(a)
(b) Fig. 1. (a) Conventional programming scheme based on the incremental step pulse programming method. (b) Soft-programming scheme proposed in this work: a relatively small gate pulse is applied immediately after the main program pulse. The subsequent small program pulse removes electrons trapped in high-j blocking oxide and thus reduces the fast charge loss under a retention state.
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program voltage (Vp0) to reach the targeted threshold voltage of memory cells. During each program and verification cycle, the threshold voltage is stepped up and then verified to ensure that the cells are precisely programmed, as illustrated in Fig. 1(a). This iteration of the program and verification steps is maintained until the threshold voltage of the memory cell reaches the targeted verification level from the initial state. On the other hand, in the proposed soft programming method, a relatively small positive gate pulse (Vsoft-prog) is added immediately after the main program pulse (Vpf), followed by the program verification pulse (Vverification), as shown in Fig. 1(b). By adding a consecutive small positive gate pulse after main FN injection programming, we can beforehand remove electrons in shallow traps of the high-j blocking oxide. These electrons in shallow traps are detrapped easily and cause early charge loss in the retention state. Because the detrapping speed of electrons in shallow traps is faster than that of electrons in deep traps under a given electric field, the small positive pulse can effectively reduce early charge loss from the high-j blocking oxides, leading to improvement of the retention property as well as the initial VT instability. In the implementation of the soft programming method, it is not necessary to apply the small positive gate pulse at every program and verification step, as shown in Fig. 1(b). Instead, it can be more appropriate to insert the soft program pulse only after VT reaches the critical target voltage (e.g., ‘‘target VT minus 1 V’’). This is because it is quite difficult to apply the soft-program pulse only once, since there is no certainty that ISPP and just one soft-program pulse will be enough to complete the program operation. Then, we can effectively reduce the total programming time to minimize the number of the soft-program pulse to be applied. Fig. 2(a) and (b) shows the change of the flat band voltage (VFB) after program operation for different soft program voltage (Vsoft-prog) and time duration, respectively. The devices were first programmed to VFB = 4 V using a main program pulse of +18 V. The pulse duration of Vsoft-prog is fixed at 100 ms in Fig. 2(a) and the magnitude of the pulse is 8 V or 13 V in Fig 2(b). An interesting observation is the decrease of the programmed VFB by applying the soft program pulse, because the positive gate pulse commonly increases VFB. A more interesting phenomenon is that by adding a soft program pulse, the programmed VFB decreases first and then bounces back to increase as the soft program voltage or time increases. This phenomenon can be understood by considering the different tunneling current components of the gate dielectric stack. Fig. 3 depicts energy band diagrams for three possible scenarios when the soft program pulse is applied. Here, JD indicates the discharge current by electron detrapping from the shallow traps in the high-j blocking oxide. JN and JT indicate the tunneling current from the nitride to the gate electrode and the tunneling current from the Si substrate to the nitride, respectively. When the soft program voltage is small, the electrons at the shallow traps in the high-j blocking oxide are detrapped, whereas the electrons at deep level traps in nitride are not easily detrapped (JD >> JN). In this situation, the small change of VFB can be attributed to the discharge current JD rather than to the tunneling current JN, since the detrapping speed of electrons at the shallow energy level in the high-j blocking oxide is faster than that of electrons at deep level traps in the nitride by the given gate voltage. Therefore, initially trapped electrons in the blocking oxide during program operation are selectively detrapped by applying the subsequent small positive program pulse. This corresponds to region r in Fig. 2(a), where Vsoft-prog is smaller than 8 V. As the soft program voltage further increases, the programmed VFB starts to decrease abruptly (region s in Fig. 2(a)). In this bias condition, electron detrapping from the nitride (JN) dominates JD because of the much higher density of trapped electrons in the nitride. On the other hand, in the blocking oxide, trapping and detrapping of electrons occur concurrently,
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(c) Fig. 3. Energy band diagrams for the different soft program voltages. (a) corresponds to Region r, (b) Region s, and (c) Region t, shown in Fig. 2(a). JD: discharge current by traps in the blocking oxide, JN: the tunneling current from the nitride to the metal gate, and JT: the tunneling current from the Si substrate to the nitride. The soft program voltage to create a condition of JN < JD can help detrap electrons at shallow traps and thus improves the retention property.
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and thus the removing the electrons from the shallow traps in the blocking oxide is not effectively done. When the soft program voltage becomes too high (region t in Fig. 2(a), where Vsoft-prog > 12 V), the programmed VFB turns back to increase. In this situation, the tunneling current from the silicon channel through the tunnel oxide (JT) is larger than JN + JD, as depicted in Fig. 3(c). Therefore, in order to effectively remove electrons from the shallow traps in the blocking oxide, the soft program voltage must be selected to be in a condition of JD > JB, as shown in Fig. 3(a). On the other hand, the change of the programmed VFB as a function of the soft program time in Fig. 2(b) also can be explained in the same way. The continuous decrease of VFB when the soft program voltage = 8 V is attributed to the increased JN without inflow of the tunneling current JT. Fig. 4 shows the retention properties of devices with three different programming schemes – the conventional single pulse program method, the program pulse + refill method, and the program pulse + soft program pulse method. As expected, when the soft program method is employed, early charge loss is significantly reduced. This result also is clear evidence that the initial decrease of VFB during the retention measurement (t < 100 s) is mainly due to charge loss through the blocking layer. Therefore, we can ensure good VT stability and a tight VT distribution by using the soft program method. The refill method, which uses a short negative erase pulse [9,10], does not improve the retention, as seen in Fig. 4. The conflict between our results and those in the literature is due to the
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ΔVFB(V)=VFB(prog+soft prog)-VFB(prog)
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difference in the programming scheme. The refill method is effective when programming is done by channel hot electrons. However, the refill method does not seem to be valid for devices using the FN programming scheme, because the electrons programmed by FN injection mostly occupy deep energy levels [10], which corresponds to the situation in this study. For a further detailed study, the relationship between the soft program voltage and VFB shift is examined, with variation of the soft program pulse duration. Regardless of the soft program time, the programmed VFB decreases and then increases again as the program voltage rises, as shown in Fig. 5(a). However, different soft program time requires different soft program voltage to cause the same amount of VFB change (e.g., condition ‘‘A’’ and condition ‘‘B’’ in the figure). This indicates that it is first necessary to determine the optimum conditions for soft program time and voltage. Conditions ‘‘A’’ and ‘‘B’’ were evaluated and the corresponding retention property is shown in Fig. 5(b). The results show that a soft program pulse with a lower voltage and longer time is more effective in terms of improving the programmed state VT instability and MLC performance compared to the pulse with a higher voltage and shorter time. This is because, at high voltage, while detrapping of electrons occurs in the blocking oxide, trapping of electrons newly injected from the nitride layer takes place concurrently. In contrast, a soft program pulse with a low voltage and long time
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will increase the total programming time. Therefore, the tradeoff between total programming time and reliability improvement should be carefully considered for optimal programming operation. In general, the time required to accomplish the soft-program operation in this paper is slightly lengthy. However, a soft program time can become shorter by increasing the soft program voltage, as shown in Fig. 5(a). This is because the initial charge loss retention transients caused by high-j dielectric mostly occurs in the range of ls–ms [11,13] and thereby the detrapping of electrons in the blocking oxide can be further promoted by the soft program pulse. Lastly, the soft program method was applied to two different blocking oxide materials, Al2O3 and the 2% La-LaAlOx. The devices have the same tunnel oxide and charge-trapping layer thickness for a fair comparison. Fig. 6 reveals that the device with 2% LaLaAlOx shows more distinct improvement with application of the soft-program method compared to the device with Al2O3. This is due to the greater physical thickness of 2% La-LaAlOx, as there are consequently more traps in total and thus there is substantial room for improvement of the retention property. This is clearly confirmed by the change in the gate voltage during a constant current stress test performed on TANOS devices, as presented in the inset of Fig. 6. The soft program method can be widely applicable to CTF memory devices, as well as conventional floating gate type Flash memory devices, for improving the retention property without modification of the device structure and process. Furthermore, it is more effective for cases where the j-value of the blocking oxide or inter-poly dielectric (IPD) is high [18–21], since high-j dielectrics are reported to have substantially higher trap densities than conventional oxide materials.
4. Conclusions It is demonstrated that the soft program method can greatly suppress the initial charge loss and thereby improve the programmed state reliability of charge-trap type Flash memory devices by removing the shallowly trapped electrons in blocking layers. The experimental results strongly suggest that electron trapping at shallow traps in the high-j blocking layer is the main reason for the fast charge loss, and this can be effectively suppressed by a suitable program method, even without changing the device structure or process. For achieving the best trade-off
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between the programming speed and reliability enhancement, soft-program method should be carefully implemented. Acknowledgments This work was financially supported by SK Hynix Semiconductor Inc. The authors would like to thank the National Nanofab Center for device fabrication support. The authors would also like to thank Jusung Engineering Inc. and UP Chemical for ALD equipment and precursor support, respectively. References [1] Kim K. Technology for sub-50nm DRAM and NAND flash manufacturing. In: Electron devices meeting, IEDM ‘05 technical digest, international; 2005. p. 323–6. [2] Lee CH, Choi J, Kang C, Shin Y, Lee JS, Sel J, et al. Multi-level NAND flash memory with 63 nm-node TANOS (Si–Oxide–SiN–Al2O3–TaN) cell structure. In: Electron devices meeting, IEDM ‘06 technical digest, international; 2006. p. 21–2. [3] Park Y, Choi J, Kang C, Lee C, Shin Y, Choi B, et al. Highly manufacturable 32Gb multi-Level NAND flash memory with 0.0098 lm2 cell size using TANOS (Si– Oxide–Al2O3–TaN) cell technology. In: Electron devices meeting, IEDM ‘06 technical digest, international; 2006. 346900. [4] Choi S, Baik SJ, and Moon J.T., Band engineered charge trap NAND flash with sub-40 nm process technologies (Invited). In: Electron devices meeting, IEDM ‘06 technical digest, international; 2006. p. 925. [5] Gilmer DC, Goel N, Park H, Park C, Verma S, Bersuker G, et al. Engineering the complete MANOS-type NVM stack for best in class retention performance. In: Electron devices meeting, IEDM ‘09 technical digest, international; 2009. p. 17.5.1–17.5.4. [6] Lee CH, Choi KI, Cho MK, Song YH, Park KC, Kim K. A Novel SONOS Structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit flash memories. In: Electron devices meeting, IEDM ‘03 technical digest, international; 2003. p. 613–6. [7] Eitan B, Pavan P, Bloom I, Aloni E, Frommer A, Finzi D. NROM: A novel localized trapping, 2-bit nonvolatile memory cell. IEEE Electron Dev Lett 2000;21: 543–5. [8] Yang Y, White MH. Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures. Solid-State Electron 2000;44:949–58.
[9] Hsiao YH, Lue HT, Shih YH, Lai EK, Hsieh KY, Liu R, et al. Improved reliability performances of SONOS-type devices using hot-hole erase method by novel negative FN operations. IEEE Trans Dev Mater Reliability 2008;8:344–51. [10] Lue HT, Shih YH, Hsieh KY, Liu R, Lu CY. Novel soft erase and re-fill methods for a P+-poly gate nitride-trapping non-volatile memory device with excellent endurance and retention properties. In Proc Int. Rel Phys Symp. 2005. p. 168– 74. [11] Kim B, Baik S, Kim S, Lee JG, Koo B, Choi S, et al. Characterization of threshold voltage instability after program in charge trap flash memory. In Proc Int. Rel Phys Symp. 2009. p. 284–7. [12] Amoroso SM, Mauri A, Galbiati N, Scozzari C, Mascellino E, Camozzi E, et al. Reliability constraints for TANOS memories due to alumina trapping and leakage. In Proc Int. Rel Phys Symp 2010. p. 966–9. [13] Chen CP, Lue HT, Hsieh CC, Chang KP, Hsieh KY, Lu CY. Study of fast initial charge loss and it’s impact on the programmed states Vt distribution of charge-trapping NAND flash. In: Electron devices meeting, IEDM ‘10 technical digest, international; 2010. p. 5.6.1–4. [14] Park JK, Lee SH, Oh JS, Lee KH, Pyi SH, Cho BJ. Improvement of charge retention in flash memory devices by very light doping of lanthanum into an aluminumoxide blocking layer. Appl Phys Exp 2012;5:081102-1–2-3. [15] Park JK, Park Y, Lim SK, Oh JS, Joo MS, Hong K, et al. Improvement of memory performance by high temperature annealing of the Al2O3 blocking layer in a charge-trap type flash memory device. Appl Phys Lett 2010;96. 222902-1– 222902-3. [16] Suh K-D, Suh B-H, Lim Y-H, Kim J-K, Choi Y-J, Koh Y-N, et al. 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme. IEEE J SolidState Circ 1995;30:1149–56. [17] Lue HT, Hsu TH, Wang SY, Lai EK, Hsieh KY, Liu R, et al. Study of incremental step pulse programming (ISPP) and STI edge effect of BE-SONOS nand flash. In Proc Int. Rel Phys Symp 2008; p. 693–4. [18] Pu J, Chan DSH, Kim SJ, Cho BJ. Aluminum-doped gadolinium oxides as blocking layer for improved charge retention in charge-trap-type nonvolatile memory devices. IEEE Trans Electron Dev 2009;56:2739–45. [19] He W, Pu J, Chan DSH, Cho BJ. Performance improvement in charge-trap flash memory using lanthanum-based high-j blocking oxide. IEEE Trans Electron Dev 2009;56:2746–51. [20] Park JK, Park Y, Song MH, Lim SK, Oh JS, Joo MS, et al. Cubic-structured HfLaO for the blocking layer of a charge-trap type flash memory device. Appl Phys Exp 2010;3. 091501-1–091501-3. [21] Zhang L, He W, Chan DSH, Cho BJ. Multi-layer high-j interpoly dielectric for floating gate flash memory devices. Solid-State Electron 2008;52:564–70.
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Improvement of the multi-level cell performance by a soft program method in flash memory devices Jong Kyung Park a, Ki-Hong Lee b, Seung Ho Pyi b, Seok-Hee Lee a,b, Byung Jin Cho a,⇑ a b
Dept. of Electrical Engineering, KAIST, 335 Gwahak-ro, Yuseong-gu, Daejeon 305-701, Republic of Korea SK Hynix Semiconductor Incorporated, Bubal-eup, Icheon-si, Gyeonggi-do 467-701, Republic of Korea
a r t i c l e
i n f o
Article history: Received 13 August 2013 Received in revised form 4 February 2014 Accepted 26 February 2014 Available online 19 March 2014 The review of this paper was arranged by Prof. A. Zaslavsky
a b s t r a c t A soft program method is proposed for charge-trap flash (CTF) memory devices. By adding a subsequent small positive gate pulse after main Fowler–Nordheim (FN) injection programming, early charge loss is greatly reduced. The multi-level cell performance as well as the initial flat-band voltage (VFB) instability can thereby be improved by removing the trapped electrons at the shallow traps in the blocking oxide layer. The proposed soft program method is a simple but very effective way to improve the fast retention property without changing the memory structure, especially for cases where the j-value of the blocking oxide is high. Ó 2014 Elsevier Ltd. All rights reserved.
Keywords: Reliability Soft program TANOS Blocking oxide
1. Introduction As a means of overcoming the severe scaling limitations of floating gate (FG) type Flash memory devices, the development of charge trap type Flash (CTF) devices has been accelerated due to their better scalability [1–3]. However, the inferior data retention property caused by the complex nature of charge trapping has been one of the main obstacles blocking the entry of CTF devices into the mainstream of Flash memory mass production [4–6]. Recently, as alternative approaches to overcome this challenge, new programming methods have been suggested for improving the retention property in CTF devices. Lue et al. proposed the so-called ‘refill method’ in nonvolatile read only memory (NROM) devices [7,10]. For program operation of the NROM device, the channel hot electron (CHE) method is usually used to locally inject electrons from the channel near the source or drain junction for 2bit/cell operation. However, since the electrons injected by the CHE method mainly occupy shallow trap levels in the nitride trapping layer, the charge loss becomes severe, especially at high temperatures [8]. To overcome this problem, Lue et al. suggested the ‘refill method’, which repeats the sequence of the CHE program followed by short negative pulses for Fowler–Nordheim (FN) tunneling several times to eject electrons from the shallow traps in nitride ⇑ Corresponding author. Tel.: +82 42 350 3485; fax: +82 42 350 8565. E-mail address: [email protected] (B.J. Cho). http://dx.doi.org/10.1016/j.sse.2014.02.012 0038-1101/Ó 2014 Elsevier Ltd. All rights reserved.
[9,10]. The refill method can modify the electron trap energy spectrum into deeper energy levels and thereby improve the retention property. However, this method is not very effective for devices using FN tunneling injection programming, which is the main programming mechanism in modern CTF devices such as TANOS (TaN/ Al2O3/Si3N4/SiO2/Si) devices [10]. This is because the electrons from FN programming initially fill the relatively deep energy levels in the nitride trapping layer. On the other hand, in TANOS devices, the high-j blocking layer has been identified to be the one which causes early stage threshold voltage (VT) instability and retention degradation due to charge trapping/detrapping and carrier leakage [11,12]. Moreover, the fast detrapping of bulk trapped charges during program operation in the high-j blocking oxide can contribute to early stage charge loss by the internal electric field and thereby threatens the multi-level cell (MLC) performance [13]. In this work, we propose a new program method, referred to as the soft program method, which can reduce the fast charge loss of TANOS devices under the retention state, and thereby improve the early stage VT instability and the MLC performance. 2. Experimental Typical TANOS devices were fabricated on a p-type Si substrate. After standard gate pre-cleaning, a 4.5 nm thick thermal SiO2 tunnel oxide was grown on the substrate, and a 6 nm thick Si3N4 charge-trapping layer was deposited by low-pressure chemical
J.K. Park et al. / Solid-State Electronics 94 (2014) 86–90
vapor deposition (LPCVD) on the SiO2 layer. For the blocking oxide, the experimental splits were designed for evaluating the soft program method systematically. Two different kinds of materials, Al2O3 and LaAlOx (with 2% La), were prepared for the blocking oxide by an atomic layer deposition (ALD) process. The 2% LaLaAlOx has a dielectric constant of 13 [14]. The thickness of the LaAlOx and Al2O3 layers was 14 and 12 nm, respectively, so that the equivalent oxide thickness (EOT) of the entire gate stack is similar (11.9 and 11.7 nm). The process conditions for the sample preparation and memory performance of the two devices are described in detail in Ref. [14]. In TANOS devices, the device performance is reported to be significantly affected by the postdeposition annealing (PDA) process conditions [14,15]. In this experiment, all the samples were annealed in a N2 ambient at 1000 °C for 30 s for fair comparison. After post-deposition annealing, a TaN metal layer was deposited by reactive sputtering and then patterned to form gate electrodes. Post-implantation annealing was conducted at 900 °C for 30 s. Forming gas annealing was performed at 420 °C for 30 min in a N2/H2 ambient. CTF memory cell capacitors were patterned with a gate length/width of 100 lm/100 lm for evaluating the memory performance. The FN tunneling method was used to program or erase the Flash memory cells.
3. Results and discussion Fig. 1(a and b) shows the conventional programming method and the new soft programming method proposed in this work, respectively. In the conventional programming method, incremental step pulse programming (ISPP) is the most widely used method to maintain a tight cell VT distribution for high reliability and multi-level cell (MLC) applications [16,17]. The ISPP method consists of several program and verification steps, and gradually increases the
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(b) Fig. 1. (a) Conventional programming scheme based on the incremental step pulse programming method. (b) Soft-programming scheme proposed in this work: a relatively small gate pulse is applied immediately after the main program pulse. The subsequent small program pulse removes electrons trapped in high-j blocking oxide and thus reduces the fast charge loss under a retention state.
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program voltage (Vp0) to reach the targeted threshold voltage of memory cells. During each program and verification cycle, the threshold voltage is stepped up and then verified to ensure that the cells are precisely programmed, as illustrated in Fig. 1(a). This iteration of the program and verification steps is maintained until the threshold voltage of the memory cell reaches the targeted verification level from the initial state. On the other hand, in the proposed soft programming method, a relatively small positive gate pulse (Vsoft-prog) is added immediately after the main program pulse (Vpf), followed by the program verification pulse (Vverification), as shown in Fig. 1(b). By adding a consecutive small positive gate pulse after main FN injection programming, we can beforehand remove electrons in shallow traps of the high-j blocking oxide. These electrons in shallow traps are detrapped easily and cause early charge loss in the retention state. Because the detrapping speed of electrons in shallow traps is faster than that of electrons in deep traps under a given electric field, the small positive pulse can effectively reduce early charge loss from the high-j blocking oxides, leading to improvement of the retention property as well as the initial VT instability. In the implementation of the soft programming method, it is not necessary to apply the small positive gate pulse at every program and verification step, as shown in Fig. 1(b). Instead, it can be more appropriate to insert the soft program pulse only after VT reaches the critical target voltage (e.g., ‘‘target VT minus 1 V’’). This is because it is quite difficult to apply the soft-program pulse only once, since there is no certainty that ISPP and just one soft-program pulse will be enough to complete the program operation. Then, we can effectively reduce the total programming time to minimize the number of the soft-program pulse to be applied. Fig. 2(a) and (b) shows the change of the flat band voltage (VFB) after program operation for different soft program voltage (Vsoft-prog) and time duration, respectively. The devices were first programmed to VFB = 4 V using a main program pulse of +18 V. The pulse duration of Vsoft-prog is fixed at 100 ms in Fig. 2(a) and the magnitude of the pulse is 8 V or 13 V in Fig 2(b). An interesting observation is the decrease of the programmed VFB by applying the soft program pulse, because the positive gate pulse commonly increases VFB. A more interesting phenomenon is that by adding a soft program pulse, the programmed VFB decreases first and then bounces back to increase as the soft program voltage or time increases. This phenomenon can be understood by considering the different tunneling current components of the gate dielectric stack. Fig. 3 depicts energy band diagrams for three possible scenarios when the soft program pulse is applied. Here, JD indicates the discharge current by electron detrapping from the shallow traps in the high-j blocking oxide. JN and JT indicate the tunneling current from the nitride to the gate electrode and the tunneling current from the Si substrate to the nitride, respectively. When the soft program voltage is small, the electrons at the shallow traps in the high-j blocking oxide are detrapped, whereas the electrons at deep level traps in nitride are not easily detrapped (JD >> JN). In this situation, the small change of VFB can be attributed to the discharge current JD rather than to the tunneling current JN, since the detrapping speed of electrons at the shallow energy level in the high-j blocking oxide is faster than that of electrons at deep level traps in the nitride by the given gate voltage. Therefore, initially trapped electrons in the blocking oxide during program operation are selectively detrapped by applying the subsequent small positive program pulse. This corresponds to region r in Fig. 2(a), where Vsoft-prog is smaller than 8 V. As the soft program voltage further increases, the programmed VFB starts to decrease abruptly (region s in Fig. 2(a)). In this bias condition, electron detrapping from the nitride (JN) dominates JD because of the much higher density of trapped electrons in the nitride. On the other hand, in the blocking oxide, trapping and detrapping of electrons occur concurrently,
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(c) Fig. 3. Energy band diagrams for the different soft program voltages. (a) corresponds to Region r, (b) Region s, and (c) Region t, shown in Fig. 2(a). JD: discharge current by traps in the blocking oxide, JN: the tunneling current from the nitride to the metal gate, and JT: the tunneling current from the Si substrate to the nitride. The soft program voltage to create a condition of JN < JD can help detrap electrons at shallow traps and thus improves the retention property.
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and thus the removing the electrons from the shallow traps in the blocking oxide is not effectively done. When the soft program voltage becomes too high (region t in Fig. 2(a), where Vsoft-prog > 12 V), the programmed VFB turns back to increase. In this situation, the tunneling current from the silicon channel through the tunnel oxide (JT) is larger than JN + JD, as depicted in Fig. 3(c). Therefore, in order to effectively remove electrons from the shallow traps in the blocking oxide, the soft program voltage must be selected to be in a condition of JD > JB, as shown in Fig. 3(a). On the other hand, the change of the programmed VFB as a function of the soft program time in Fig. 2(b) also can be explained in the same way. The continuous decrease of VFB when the soft program voltage = 8 V is attributed to the increased JN without inflow of the tunneling current JT. Fig. 4 shows the retention properties of devices with three different programming schemes – the conventional single pulse program method, the program pulse + refill method, and the program pulse + soft program pulse method. As expected, when the soft program method is employed, early charge loss is significantly reduced. This result also is clear evidence that the initial decrease of VFB during the retention measurement (t < 100 s) is mainly due to charge loss through the blocking layer. Therefore, we can ensure good VT stability and a tight VT distribution by using the soft program method. The refill method, which uses a short negative erase pulse [9,10], does not improve the retention, as seen in Fig. 4. The conflict between our results and those in the literature is due to the
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difference in the programming scheme. The refill method is effective when programming is done by channel hot electrons. However, the refill method does not seem to be valid for devices using the FN programming scheme, because the electrons programmed by FN injection mostly occupy deep energy levels [10], which corresponds to the situation in this study. For a further detailed study, the relationship between the soft program voltage and VFB shift is examined, with variation of the soft program pulse duration. Regardless of the soft program time, the programmed VFB decreases and then increases again as the program voltage rises, as shown in Fig. 5(a). However, different soft program time requires different soft program voltage to cause the same amount of VFB change (e.g., condition ‘‘A’’ and condition ‘‘B’’ in the figure). This indicates that it is first necessary to determine the optimum conditions for soft program time and voltage. Conditions ‘‘A’’ and ‘‘B’’ were evaluated and the corresponding retention property is shown in Fig. 5(b). The results show that a soft program pulse with a lower voltage and longer time is more effective in terms of improving the programmed state VT instability and MLC performance compared to the pulse with a higher voltage and shorter time. This is because, at high voltage, while detrapping of electrons occurs in the blocking oxide, trapping of electrons newly injected from the nitride layer takes place concurrently. In contrast, a soft program pulse with a low voltage and long time
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will increase the total programming time. Therefore, the tradeoff between total programming time and reliability improvement should be carefully considered for optimal programming operation. In general, the time required to accomplish the soft-program operation in this paper is slightly lengthy. However, a soft program time can become shorter by increasing the soft program voltage, as shown in Fig. 5(a). This is because the initial charge loss retention transients caused by high-j dielectric mostly occurs in the range of ls–ms [11,13] and thereby the detrapping of electrons in the blocking oxide can be further promoted by the soft program pulse. Lastly, the soft program method was applied to two different blocking oxide materials, Al2O3 and the 2% La-LaAlOx. The devices have the same tunnel oxide and charge-trapping layer thickness for a fair comparison. Fig. 6 reveals that the device with 2% LaLaAlOx shows more distinct improvement with application of the soft-program method compared to the device with Al2O3. This is due to the greater physical thickness of 2% La-LaAlOx, as there are consequently more traps in total and thus there is substantial room for improvement of the retention property. This is clearly confirmed by the change in the gate voltage during a constant current stress test performed on TANOS devices, as presented in the inset of Fig. 6. The soft program method can be widely applicable to CTF memory devices, as well as conventional floating gate type Flash memory devices, for improving the retention property without modification of the device structure and process. Furthermore, it is more effective for cases where the j-value of the blocking oxide or inter-poly dielectric (IPD) is high [18–21], since high-j dielectrics are reported to have substantially higher trap densities than conventional oxide materials.
4. Conclusions It is demonstrated that the soft program method can greatly suppress the initial charge loss and thereby improve the programmed state reliability of charge-trap type Flash memory devices by removing the shallowly trapped electrons in blocking layers. The experimental results strongly suggest that electron trapping at shallow traps in the high-j blocking layer is the main reason for the fast charge loss, and this can be effectively suppressed by a suitable program method, even without changing the device structure or process. For achieving the best trade-off
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between the programming speed and reliability enhancement, soft-program method should be carefully implemented. Acknowledgments This work was financially supported by SK Hynix Semiconductor Inc. The authors would like to thank the National Nanofab Center for device fabrication support. The authors would also like to thank Jusung Engineering Inc. and UP Chemical for ALD equipment and precursor support, respectively. References [1] Kim K. Technology for sub-50nm DRAM and NAND flash manufacturing. In: Electron devices meeting, IEDM ‘05 technical digest, international; 2005. p. 323–6. [2] Lee CH, Choi J, Kang C, Shin Y, Lee JS, Sel J, et al. Multi-level NAND flash memory with 63 nm-node TANOS (Si–Oxide–SiN–Al2O3–TaN) cell structure. In: Electron devices meeting, IEDM ‘06 technical digest, international; 2006. p. 21–2. [3] Park Y, Choi J, Kang C, Lee C, Shin Y, Choi B, et al. Highly manufacturable 32Gb multi-Level NAND flash memory with 0.0098 lm2 cell size using TANOS (Si– Oxide–Al2O3–TaN) cell technology. In: Electron devices meeting, IEDM ‘06 technical digest, international; 2006. 346900. [4] Choi S, Baik SJ, and Moon J.T., Band engineered charge trap NAND flash with sub-40 nm process technologies (Invited). In: Electron devices meeting, IEDM ‘06 technical digest, international; 2006. p. 925. [5] Gilmer DC, Goel N, Park H, Park C, Verma S, Bersuker G, et al. Engineering the complete MANOS-type NVM stack for best in class retention performance. In: Electron devices meeting, IEDM ‘09 technical digest, international; 2009. p. 17.5.1–17.5.4. [6] Lee CH, Choi KI, Cho MK, Song YH, Park KC, Kim K. A Novel SONOS Structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit flash memories. In: Electron devices meeting, IEDM ‘03 technical digest, international; 2003. p. 613–6. [7] Eitan B, Pavan P, Bloom I, Aloni E, Frommer A, Finzi D. NROM: A novel localized trapping, 2-bit nonvolatile memory cell. IEEE Electron Dev Lett 2000;21: 543–5. [8] Yang Y, White MH. Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures. Solid-State Electron 2000;44:949–58.
[9] Hsiao YH, Lue HT, Shih YH, Lai EK, Hsieh KY, Liu R, et al. Improved reliability performances of SONOS-type devices using hot-hole erase method by novel negative FN operations. IEEE Trans Dev Mater Reliability 2008;8:344–51. [10] Lue HT, Shih YH, Hsieh KY, Liu R, Lu CY. Novel soft erase and re-fill methods for a P+-poly gate nitride-trapping non-volatile memory device with excellent endurance and retention properties. In Proc Int. Rel Phys Symp. 2005. p. 168– 74. [11] Kim B, Baik S, Kim S, Lee JG, Koo B, Choi S, et al. Characterization of threshold voltage instability after program in charge trap flash memory. In Proc Int. Rel Phys Symp. 2009. p. 284–7. [12] Amoroso SM, Mauri A, Galbiati N, Scozzari C, Mascellino E, Camozzi E, et al. Reliability constraints for TANOS memories due to alumina trapping and leakage. In Proc Int. Rel Phys Symp 2010. p. 966–9. [13] Chen CP, Lue HT, Hsieh CC, Chang KP, Hsieh KY, Lu CY. Study of fast initial charge loss and it’s impact on the programmed states Vt distribution of charge-trapping NAND flash. In: Electron devices meeting, IEDM ‘10 technical digest, international; 2010. p. 5.6.1–4. [14] Park JK, Lee SH, Oh JS, Lee KH, Pyi SH, Cho BJ. Improvement of charge retention in flash memory devices by very light doping of lanthanum into an aluminumoxide blocking layer. Appl Phys Exp 2012;5:081102-1–2-3. [15] Park JK, Park Y, Lim SK, Oh JS, Joo MS, Hong K, et al. Improvement of memory performance by high temperature annealing of the Al2O3 blocking layer in a charge-trap type flash memory device. Appl Phys Lett 2010;96. 222902-1– 222902-3. [16] Suh K-D, Suh B-H, Lim Y-H, Kim J-K, Choi Y-J, Koh Y-N, et al. 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme. IEEE J SolidState Circ 1995;30:1149–56. [17] Lue HT, Hsu TH, Wang SY, Lai EK, Hsieh KY, Liu R, et al. Study of incremental step pulse programming (ISPP) and STI edge effect of BE-SONOS nand flash. In Proc Int. Rel Phys Symp 2008; p. 693–4. [18] Pu J, Chan DSH, Kim SJ, Cho BJ. Aluminum-doped gadolinium oxides as blocking layer for improved charge retention in charge-trap-type nonvolatile memory devices. IEEE Trans Electron Dev 2009;56:2739–45. [19] He W, Pu J, Chan DSH, Cho BJ. Performance improvement in charge-trap flash memory using lanthanum-based high-j blocking oxide. IEEE Trans Electron Dev 2009;56:2746–51. [20] Park JK, Park Y, Song MH, Lim SK, Oh JS, Joo MS, et al. Cubic-structured HfLaO for the blocking layer of a charge-trap type flash memory device. Appl Phys Exp 2010;3. 091501-1–091501-3. [21] Zhang L, He W, Chan DSH, Cho BJ. Multi-layer high-j interpoly dielectric for floating gate flash memory devices. Solid-State Electron 2008;52:564–70.