- Email: [email protected]
Employing vertical dielectric layers to improve the operation performance of flash memory devices
Microelectronics Reliability 49 (2009) 371–376
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Employing vertical dielectric layers to improve the operation performance of flash memory devices Chia-Huai Ho, Kuei-Shu Chang-Liao *, Chun-Yuan Lu, Chun-Chang Lu, Tien-Ko Wang Department of Engineering and System Science, National Tsing Hua University, 101, Sec. 2, Kuang-Fu Rd., Hsinchu 30013, Taiwan, ROC
a r t i c l e
i n f o
Article history: Received 12 July 2008 Received in revised form 30 November 2008 Available online 1 February 2009
a b s t r a c t A number of new device structures have been reported recently to improve the operation performance of flash memory. In this work, a novel flash device with a vertical dielectric layer in the depletion region is proposed through simulation approach. The simulation results show that the employment of a vertical dielectric layer in the depletion region can improve the operation performance of flash memory. The improvement can be attributed to a lower potential in the central region of device channel and the increase of the potential drop in the channel direction near drain junction. Thus, this proposed vertical dielectric layer increases the electrical field of the channel and thus the probability and the momentum of electron injection. The operation characteristics of the flash device with a vertical dielectric layer in the depletion region of source and drain are superior to those without. In addition, it is found that a vertical dielectric layer with lower dielectric constant can enhance the operation performance of flash device even more. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction Compared with other memory products, flash memories possess some advantageous characteristics such as high capacity, non-volatility and low power-consumption, which are also imperative to portable electronics. Thus, flash-memory products have been widely used in digital cameras, personal digital assistants (PDAs), mobile phones and flash disks. Relevant researches primarily focus on the improvement of programming/erasing speed and reliability to enhance their competitive ability. Currently, new programming and erasing methods and device structures are proposed to improve its performance. For example, the channel hot electron initiated by secondary electron (CHISEL) is a novel programming method [1,2], which applies a negative voltage on the substrate. It causes a secondary-electron injection which increases the current injection efficiency and reduces the programming time. The opposite side floating gate is a novel flash-memory structure design [3], which adds a read gate structure at the bottom of the device and applies the capacitance coupling effect of read gate and floating gate to adjust the potential of device channel. Thus, it could control the conductibility of device channel and improve the operation performance of a flash device. According to the concept of potential adjustment mentioned above, a novel flash memory structure with a vertical dielectric layer in its depletion regions of source/drain junction is proposed
* Corresponding author. E-mail address: [email protected] (K.-S. Chang-Liao). 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.12.004
in this work to demonstrate ‘through simulation’ the improvement of operation performance. 2. Simulation The MEDICI software was used to simulate the device structure and its electrical characteristic in this work [4]. Several physical models are used to simulate, including Concentration Dependent Mobility Model (CONMOB), Perpendicular Electric Field Mobility Model (PRPMOB), Field-Dependent Mobility Model (FLDMOB), Shockley-Read-Hall Recombination Model (CONSRH), Auger Recombination Model (AUGER) and Band-Gap Narrowing Model (BGN). The devices simulated are n-type flash memories with gate Nsub = 6 1016 cm 3, Nsource = 2 1020 cm 3, length = 0.9 lm, Ndrain = 2 1020 cm 3 and Wchannel = 0.13 lm. The thicknesses of the gate stack layers in this devices are: control gate = 50 nm, top oxide = 40 nm, floating gate = 25 nm, and bottom oxide = 10 nm. The vertical dielectric layers added in the depletion regions of source and drain are oxides with a width of 0.06 lm and lengths of 0.562 lm and 0.262 lm at source and drain, respectively. Their depth from the surface of silicon is 0.07 lm. The vertical dielectric layers are located in the channel, measured from source to drain, ranging from 0.82 to 0.88 lm and/or 1.24–1.30 lm. The operation conditions are fixed for all situations, including a programming bias of Vd = 5.5 V, Vcg = 20 V (gate coupling ratio assumed to be 1/ 5), Vs = 0 V, Vsub = 0 V, and a erasing bias of Vd = 0 V, Vcg = 20 V, Vs = 8 V, Vsub = 0 V. A sketch of flash structure simulated in this work is shown in Fig. 1.
372
C.-H. Ho et al. / Microelectronics Reliability 49 (2009) 371–376
depletion region of source, and (d) the new structure 3 with a vertical dielectric layer in both the depletion region of source and drain. The threshold voltage shifts after programming and erasing for the four device structures were first simulated and compared. The vertical electrical field, vertical potential, electron injection probability, injected current density and programming/erasing current were then analyzed to study the influence of the vertical dielectric layer on the operation performance of flash memory devices. Finally, the dielectric constant of the vertical dielectric layer in new structure 3 was charged and the threshold voltage shifts of flash device after programming and erasing were simulated to study its effect on the operation performance. 3. Results and discussion
Fig. 1. Sketch of flash structure simulated in this work.
Fig. 2 shows the four flash structures studied in this work: (a) a conventional structure without vertical dielectric layer, (b) the new structure 1 with a vertical dielectric layer in the depletion region of drain, (c) the new structure 2 with a vertical dielectric layer in the
Fig. 3 shows the comparison of threshold voltage shifts after: (a) programming and (b) erasing operation for the four different flash device structures. It is found in Fig. 3(a) that the new structures 1 and 3 (both have a vertical dielectric layer in the depletion region of drain) demonstrate better programming operation performance. Fig. 3(b) shows the new structure 3 possesses the best erasing performance. Thus, a flash device with a vertical dielectric layer in both the depletion regions of source and drain exhibit the best pro-
Fig. 2. Four simulated flash structures studied in this work: (a) conventional structure, (b) new structure 1 with vertical dielectric layer in the depletion region of drain, (c) new structure 2 with vertical dielectric layer in the depletion region of source, and (d) new structure 3 with vertical dielectric layers in the depletion region of both source and drain.
C.-H. Ho et al. / Microelectronics Reliability 49 (2009) 371–376
373
Fig. 3. Comparison of threshold voltage shifts after (a) programming and (b)erasing operation of four different flash device structures.
Fig. 4. Comparison of one-dimensional vertical electrical field during programming, in the channel region, at positions measured from the source of (a) 1.23 lm, (b) 1.26 lm, and (c) 1.31 lm, which are near the drain end. Values of vertical electric field were measured starting from the channel upper surface and down to a depth of 0.5 lm.
gramming and erasing operation performance. Since the difference in erasing performances among various device structures is relatively insignificant, the following analysis is mainly focused on their programming characteristics.
Fig. 4 shows the comparison of one-dimensional vertical electrical field during programming, in the channel region, at positions measured from the source of: (a) 1.23 lm, (b) 1.26 lm, and, (c) 1.31 lm, which are near the drain end. Values of vertical electric
374
C.-H. Ho et al. / Microelectronics Reliability 49 (2009) 371–376
Fig. 5. Comparison of one-dimensional vertical electron injection probability among the four different structures of flash device during programming. Data were taken at the same positions as described in Fig. 4.
field were measured starting from the channel upper surface and down to a depth of 0.5 lm. Fig. 4(a) and (c) show that the electrical fields around the vertical dielectric layer of the device with such layer in the depletion region of drain are lower than those without it. On the other hand, Fig. 4(b) shows that the electrical fields at the vertical dielectric layer are higher. Moreover, the electrical fields near the substrate surface region (depth < 0.07 lm) for the devices with a vertical dielectric layer in the depletion region of drain are higher than those without it. Thus, the simulation results indicate that the vertical dielectric layer in the depletion region results in a significant change of internal electrical field of flash device. In addition, the increase in the electrical field strength in substrate surface region is responsible for the improvement of programming performance. Fig. 5 shows the comparison of one-dimensional vertical electron injection probability among the four different structures of flash device during programming. Data were taken at the same positions as described in Fig. 4. Results indicate that the electron injection probability of flash device with a vertical dielectric layer in the depletion region of drain is significantly larger than those without it. Thus, the vertical dielectric layer in the depletion region can increase electron injection probability. It can be found from comparing Figs. 4 and 5 that a higher electron injection probability is resulted from a higher regional electrical field.
Fig. 6 shows the one-dimensional horizontal channel potential, at the depth of 0.07 lm under the surface of channel, during
Fig. 6. Comparison of one-dimensional horizontal channel potential at the depth of 0.07 lm under the surface among four different structures of flash device during programming.
C.-H. Ho et al. / Microelectronics Reliability 49 (2009) 371–376
375
Fig. 7. Comparison of (a) injection current density at the interface between oxide and substrate for drain end and (b) the variation of programming current versus time among four different structures of flash device.
Fig. 8. Variation of erasing current versus time for four flash devices with different structures.
programming. The potential drop in the horizontal direction of channel is larger for devices with a vertical dielectric layer in the depletion region of drain because the potential in the channel is less affected by the drain bias, which thus reduces the potential in the central region of channel. Therefore, the electrical fields in the channel region and the probability and the momentum of electron injection for device with a vertical dielectric layer are increased. This also explains the findings of Figs. 4 and 5. Fig. 7 shows (a) the injection current density at the interface between the oxide and the substrate of drain end and (b) the variation of programming current versus time. These results are in consistent with those of Figs. 4–6. The increase of electrical field strength at the surface of channel near the drain end can enhance the injection-current density of programming operation. The devices with a vertical dielectric layer in the depletion region of drain show an improvement in programming performance by 2–3 times. As to the erasing characteristics, Fig. 8 shows the variation of erasing current versus time for the four different flash devices. Results indicate that devices with a vertical dielectric layer in the depletion region of drain possess better erasing characteristics than those without it. The device with a vertical dielectric layer in both source and drain shows the best erasing performance. By a similar physical mechanism, adding a vertical dielectric layer in
Fig. 9. Comparison of threshold voltage shifts of (a) programming, and (b) erasing for new structure 3 devices with different dielectric constants.
376
C.-H. Ho et al. / Microelectronics Reliability 49 (2009) 371–376
the depletion region of source can reduce the influence of source bias on the channel and cause lower channel potential. Thus, vertical dielectric layer increases the potential drop in the horizontal direction of the channel, the electrical field strength of channel surface at the source end, the momentum of electron from floating gate to source, and enhances erasing operation performance. Finally, to investigate the effects of the dielectric constant of the vertical dielectric layer, Fig. 9 shows the comparison of threshold voltage shifts of programming and erasing for structure 3 devices with different dielectric constants. The device with lower dielectric constant demonstrates better programming and erasing operation performances. It is because a vertical dielectric layer with lower dielectric constant reduces the potential at the central region of channel coupled by drain bias. Thus, it effectively reduces the channel potential and increases the potential drop in the horizontal direction of the channel, the electrical field strength of channel surface at drain end, and the probability and the number of electron injection.
source and at drain demonstrates the best programming and erasing operation performances among the four different structures of flash device. It is because the existence of vertical dielectric layer reduces the potential at the central region of channel, increases the potential drop in the horizontal direction of the channel and produces larger channel electrical field and probability of electron/hole injection. Moreover, the vertical dielectric layer with a lower dielectric constant further improves the operation performance of flash device.
4. Conclusions
[1] Mahapatra S, Shukuri S, Jeff Bude. CHISEL flash EEPROM-part I: performance and scaling. IEEE Trans Electron Dev 2002;49:1296–301. July. [2] Mahapatra S, Shukuri S, Jeff Bude. CHISEL flash EEPROM-part II: reliability. IEEE Trans Electron Dev 2002;49:1302–7. July. [3] Lin Xinnan, Chan Mansun, Wang Hongmei. Opposite side floating gate SOI flash memory cell. IEDM Tech Dig 2000:12–5. [4] Medici User’s Manual, Verion 2000.2, Avant! Corporation, July 2000.
Simulation results of programming and erasing show that adding a vertical dielectric layer in the depletion region is promising in improving the operation performance of flash device. The flash device with a vertical dielectric layers in both the depletion regions at
Acknowledgements The authors would like to thank the financial support of National Science Council, Taiwan, ROC. The simulation program MEDICI from the National Center for High-Performance Computing, Taiwan, ROC is also acknowledged. References
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Employing vertical dielectric layers to improve the operation performance of flash memory devices Chia-Huai Ho, Kuei-Shu Chang-Liao *, Chun-Yuan Lu, Chun-Chang Lu, Tien-Ko Wang Department of Engineering and System Science, National Tsing Hua University, 101, Sec. 2, Kuang-Fu Rd., Hsinchu 30013, Taiwan, ROC
a r t i c l e
i n f o
Article history: Received 12 July 2008 Received in revised form 30 November 2008 Available online 1 February 2009
a b s t r a c t A number of new device structures have been reported recently to improve the operation performance of flash memory. In this work, a novel flash device with a vertical dielectric layer in the depletion region is proposed through simulation approach. The simulation results show that the employment of a vertical dielectric layer in the depletion region can improve the operation performance of flash memory. The improvement can be attributed to a lower potential in the central region of device channel and the increase of the potential drop in the channel direction near drain junction. Thus, this proposed vertical dielectric layer increases the electrical field of the channel and thus the probability and the momentum of electron injection. The operation characteristics of the flash device with a vertical dielectric layer in the depletion region of source and drain are superior to those without. In addition, it is found that a vertical dielectric layer with lower dielectric constant can enhance the operation performance of flash device even more. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction Compared with other memory products, flash memories possess some advantageous characteristics such as high capacity, non-volatility and low power-consumption, which are also imperative to portable electronics. Thus, flash-memory products have been widely used in digital cameras, personal digital assistants (PDAs), mobile phones and flash disks. Relevant researches primarily focus on the improvement of programming/erasing speed and reliability to enhance their competitive ability. Currently, new programming and erasing methods and device structures are proposed to improve its performance. For example, the channel hot electron initiated by secondary electron (CHISEL) is a novel programming method [1,2], which applies a negative voltage on the substrate. It causes a secondary-electron injection which increases the current injection efficiency and reduces the programming time. The opposite side floating gate is a novel flash-memory structure design [3], which adds a read gate structure at the bottom of the device and applies the capacitance coupling effect of read gate and floating gate to adjust the potential of device channel. Thus, it could control the conductibility of device channel and improve the operation performance of a flash device. According to the concept of potential adjustment mentioned above, a novel flash memory structure with a vertical dielectric layer in its depletion regions of source/drain junction is proposed
* Corresponding author. E-mail address: [email protected] (K.-S. Chang-Liao). 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.12.004
in this work to demonstrate ‘through simulation’ the improvement of operation performance. 2. Simulation The MEDICI software was used to simulate the device structure and its electrical characteristic in this work [4]. Several physical models are used to simulate, including Concentration Dependent Mobility Model (CONMOB), Perpendicular Electric Field Mobility Model (PRPMOB), Field-Dependent Mobility Model (FLDMOB), Shockley-Read-Hall Recombination Model (CONSRH), Auger Recombination Model (AUGER) and Band-Gap Narrowing Model (BGN). The devices simulated are n-type flash memories with gate Nsub = 6 1016 cm 3, Nsource = 2 1020 cm 3, length = 0.9 lm, Ndrain = 2 1020 cm 3 and Wchannel = 0.13 lm. The thicknesses of the gate stack layers in this devices are: control gate = 50 nm, top oxide = 40 nm, floating gate = 25 nm, and bottom oxide = 10 nm. The vertical dielectric layers added in the depletion regions of source and drain are oxides with a width of 0.06 lm and lengths of 0.562 lm and 0.262 lm at source and drain, respectively. Their depth from the surface of silicon is 0.07 lm. The vertical dielectric layers are located in the channel, measured from source to drain, ranging from 0.82 to 0.88 lm and/or 1.24–1.30 lm. The operation conditions are fixed for all situations, including a programming bias of Vd = 5.5 V, Vcg = 20 V (gate coupling ratio assumed to be 1/ 5), Vs = 0 V, Vsub = 0 V, and a erasing bias of Vd = 0 V, Vcg = 20 V, Vs = 8 V, Vsub = 0 V. A sketch of flash structure simulated in this work is shown in Fig. 1.
372
C.-H. Ho et al. / Microelectronics Reliability 49 (2009) 371–376
depletion region of source, and (d) the new structure 3 with a vertical dielectric layer in both the depletion region of source and drain. The threshold voltage shifts after programming and erasing for the four device structures were first simulated and compared. The vertical electrical field, vertical potential, electron injection probability, injected current density and programming/erasing current were then analyzed to study the influence of the vertical dielectric layer on the operation performance of flash memory devices. Finally, the dielectric constant of the vertical dielectric layer in new structure 3 was charged and the threshold voltage shifts of flash device after programming and erasing were simulated to study its effect on the operation performance. 3. Results and discussion
Fig. 1. Sketch of flash structure simulated in this work.
Fig. 2 shows the four flash structures studied in this work: (a) a conventional structure without vertical dielectric layer, (b) the new structure 1 with a vertical dielectric layer in the depletion region of drain, (c) the new structure 2 with a vertical dielectric layer in the
Fig. 3 shows the comparison of threshold voltage shifts after: (a) programming and (b) erasing operation for the four different flash device structures. It is found in Fig. 3(a) that the new structures 1 and 3 (both have a vertical dielectric layer in the depletion region of drain) demonstrate better programming operation performance. Fig. 3(b) shows the new structure 3 possesses the best erasing performance. Thus, a flash device with a vertical dielectric layer in both the depletion regions of source and drain exhibit the best pro-
Fig. 2. Four simulated flash structures studied in this work: (a) conventional structure, (b) new structure 1 with vertical dielectric layer in the depletion region of drain, (c) new structure 2 with vertical dielectric layer in the depletion region of source, and (d) new structure 3 with vertical dielectric layers in the depletion region of both source and drain.
C.-H. Ho et al. / Microelectronics Reliability 49 (2009) 371–376
373
Fig. 3. Comparison of threshold voltage shifts after (a) programming and (b)erasing operation of four different flash device structures.
Fig. 4. Comparison of one-dimensional vertical electrical field during programming, in the channel region, at positions measured from the source of (a) 1.23 lm, (b) 1.26 lm, and (c) 1.31 lm, which are near the drain end. Values of vertical electric field were measured starting from the channel upper surface and down to a depth of 0.5 lm.
gramming and erasing operation performance. Since the difference in erasing performances among various device structures is relatively insignificant, the following analysis is mainly focused on their programming characteristics.
Fig. 4 shows the comparison of one-dimensional vertical electrical field during programming, in the channel region, at positions measured from the source of: (a) 1.23 lm, (b) 1.26 lm, and, (c) 1.31 lm, which are near the drain end. Values of vertical electric
374
C.-H. Ho et al. / Microelectronics Reliability 49 (2009) 371–376
Fig. 5. Comparison of one-dimensional vertical electron injection probability among the four different structures of flash device during programming. Data were taken at the same positions as described in Fig. 4.
field were measured starting from the channel upper surface and down to a depth of 0.5 lm. Fig. 4(a) and (c) show that the electrical fields around the vertical dielectric layer of the device with such layer in the depletion region of drain are lower than those without it. On the other hand, Fig. 4(b) shows that the electrical fields at the vertical dielectric layer are higher. Moreover, the electrical fields near the substrate surface region (depth < 0.07 lm) for the devices with a vertical dielectric layer in the depletion region of drain are higher than those without it. Thus, the simulation results indicate that the vertical dielectric layer in the depletion region results in a significant change of internal electrical field of flash device. In addition, the increase in the electrical field strength in substrate surface region is responsible for the improvement of programming performance. Fig. 5 shows the comparison of one-dimensional vertical electron injection probability among the four different structures of flash device during programming. Data were taken at the same positions as described in Fig. 4. Results indicate that the electron injection probability of flash device with a vertical dielectric layer in the depletion region of drain is significantly larger than those without it. Thus, the vertical dielectric layer in the depletion region can increase electron injection probability. It can be found from comparing Figs. 4 and 5 that a higher electron injection probability is resulted from a higher regional electrical field.
Fig. 6 shows the one-dimensional horizontal channel potential, at the depth of 0.07 lm under the surface of channel, during
Fig. 6. Comparison of one-dimensional horizontal channel potential at the depth of 0.07 lm under the surface among four different structures of flash device during programming.
C.-H. Ho et al. / Microelectronics Reliability 49 (2009) 371–376
375
Fig. 7. Comparison of (a) injection current density at the interface between oxide and substrate for drain end and (b) the variation of programming current versus time among four different structures of flash device.
Fig. 8. Variation of erasing current versus time for four flash devices with different structures.
programming. The potential drop in the horizontal direction of channel is larger for devices with a vertical dielectric layer in the depletion region of drain because the potential in the channel is less affected by the drain bias, which thus reduces the potential in the central region of channel. Therefore, the electrical fields in the channel region and the probability and the momentum of electron injection for device with a vertical dielectric layer are increased. This also explains the findings of Figs. 4 and 5. Fig. 7 shows (a) the injection current density at the interface between the oxide and the substrate of drain end and (b) the variation of programming current versus time. These results are in consistent with those of Figs. 4–6. The increase of electrical field strength at the surface of channel near the drain end can enhance the injection-current density of programming operation. The devices with a vertical dielectric layer in the depletion region of drain show an improvement in programming performance by 2–3 times. As to the erasing characteristics, Fig. 8 shows the variation of erasing current versus time for the four different flash devices. Results indicate that devices with a vertical dielectric layer in the depletion region of drain possess better erasing characteristics than those without it. The device with a vertical dielectric layer in both source and drain shows the best erasing performance. By a similar physical mechanism, adding a vertical dielectric layer in
Fig. 9. Comparison of threshold voltage shifts of (a) programming, and (b) erasing for new structure 3 devices with different dielectric constants.
376
C.-H. Ho et al. / Microelectronics Reliability 49 (2009) 371–376
the depletion region of source can reduce the influence of source bias on the channel and cause lower channel potential. Thus, vertical dielectric layer increases the potential drop in the horizontal direction of the channel, the electrical field strength of channel surface at the source end, the momentum of electron from floating gate to source, and enhances erasing operation performance. Finally, to investigate the effects of the dielectric constant of the vertical dielectric layer, Fig. 9 shows the comparison of threshold voltage shifts of programming and erasing for structure 3 devices with different dielectric constants. The device with lower dielectric constant demonstrates better programming and erasing operation performances. It is because a vertical dielectric layer with lower dielectric constant reduces the potential at the central region of channel coupled by drain bias. Thus, it effectively reduces the channel potential and increases the potential drop in the horizontal direction of the channel, the electrical field strength of channel surface at drain end, and the probability and the number of electron injection.
source and at drain demonstrates the best programming and erasing operation performances among the four different structures of flash device. It is because the existence of vertical dielectric layer reduces the potential at the central region of channel, increases the potential drop in the horizontal direction of the channel and produces larger channel electrical field and probability of electron/hole injection. Moreover, the vertical dielectric layer with a lower dielectric constant further improves the operation performance of flash device.
4. Conclusions
[1] Mahapatra S, Shukuri S, Jeff Bude. CHISEL flash EEPROM-part I: performance and scaling. IEEE Trans Electron Dev 2002;49:1296–301. July. [2] Mahapatra S, Shukuri S, Jeff Bude. CHISEL flash EEPROM-part II: reliability. IEEE Trans Electron Dev 2002;49:1302–7. July. [3] Lin Xinnan, Chan Mansun, Wang Hongmei. Opposite side floating gate SOI flash memory cell. IEDM Tech Dig 2000:12–5. [4] Medici User’s Manual, Verion 2000.2, Avant! Corporation, July 2000.
Simulation results of programming and erasing show that adding a vertical dielectric layer in the depletion region is promising in improving the operation performance of flash device. The flash device with a vertical dielectric layers in both the depletion regions at
Acknowledgements The authors would like to thank the financial support of National Science Council, Taiwan, ROC. The simulation program MEDICI from the National Center for High-Performance Computing, Taiwan, ROC is also acknowledged. References