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SiN stacked trapping layer on operation characteristics of poly-Si flash memory devices
Microelectronic Engineering 138 (2015) 107–110
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Effects of HfO2/SiON/SiN stacked trapping layer on operation characteristics of poly-Si flash memory devices Hsin-Kai Fang, Kuei-Shu Chang-Liao ⇑, Chun-Yuan Chen, Hao-Wei Ho Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan, ROC
a r t i c l e
i n f o
Article history: Received 1 August 2014 Received in revised form 30 January 2015 Accepted 21 February 2015 Available online 11 March 2015 Keywords: Poly-Si Junctionless Charge-trapping HfO2 Si3N4 Flash memory
a b s t r a c t A HfO2/SiON/SiN (HON) bandgap-engineered trapping layer (BETL) on inversion-mode (IM) and junctionless (JL) polycrystalline-Si flash memory devices is investigated in this work. The HON layer is formed by performing a rapid thermal oxidation process between the depositions of SiN and HfO2. For IM device, the programming speed, retention and endurance characteristics are improved by the HON BETL while without degrading its erasing speed when compared to that with HfO2/SiN (HN) BETL. As to the JL device, improved erasing speed and retention characteristics are obtained with HON BETL; high programming speed and good endurance performances of the JL device are also observed. HON BETL is promising to improve retention characteristics of poly-Si flash memory devices since the conduction band level of SiON is higher and the trap density of SiON is lower as compared to those of SiN. Ó 2015 Elsevier B.V. All rights reserved.
1. Introduction For the increasing demand of NAND flash memory cells, polycrystalline channel material is becoming attractive for three-dimensional (3-D) integration [1–3]. An advanced junction engineering is necessary since source/drain (S/D) definition and implantation are hardly achieved for 3-D architecture. A ‘‘junctionless (JL)’’ concept is reported to replace the conventional junction formation process by homogeneously doping source, drain and channel [4]; no junction is formed and the fabrication process is simplified. The operation speeds of JL flash memory devices are greatly affected by the channel doping conditions. For n-channel JL flash device with SiN trapping layer, heavier channel doping results in faster programming speed but it sacrifices erasing speed due to its lower hole concentration [5,6]. Bandgap-engineered trapping layer (BETL) is very promising to replace single SiN trapping layer since better operation speeds and reliability characteristics can be achieved by well stacking trapping layer materials with different bandgaps [7–9]. SiN/SiON/SiN BETL and those others with similar band structure are reported to demonstrate improved operation characteristics since the trapped charges are well distributed by a larger bandgap of their middle trapping layer [7–9]. However, most of the BETL studies are based on bulk planar devices. The study of BETL on polycrystalline-Si (poly-Si) channel ⇑ Corresponding author. E-mail address: [email protected] (K.-S. Chang-Liao). http://dx.doi.org/10.1016/j.mee.2015.02.044 0167-9317/Ó 2015 Elsevier B.V. All rights reserved.
device is rarely seen and its effects on junctionless device are not yet reported. In this work, effects of HfO2/SiON/SiN (HON) BETL on the operation characteristics of both inversion-mode (IM) and JL poly-Si flash device are investigated for the first time. Operation characteristics of HON and HfO2/SiN (HN) BETL on IM and JL poly-Si device are compared as well.
2. Device fabrication IM and JL flash memory devices are both fabricated on 6-inch Si wafers. The fabrication process of IM and JL nanowire devices is shown in Fig. 1. A 200-nm thick SiO2 is firstly grown by a lowpressure chemical vapor deposition (LPCVD) system. A 50-nm thick Si3N4 buried layer is deposited, followed by an 100-nm thick SiO2 by LPCVD systems. Four SiO2 dummy fins with a height of 100 nm are formed by I-line lithography and reactive ion etching (RIE) processes as shown in Fig. 1(a). An 100-nm thick amorphous-Si is then deposited and transferred into poly-Si by solid-phase crystallization (SPC) process at 600 °C for 24 h. Phosphorous implantation (at 30 keV to a dose of 1 1013 cm 2) and activation (900 °C for 30 s) are performed on JL samples without any lithography definition. After that, S/D region is defined on two ends of dummy fins for all samples. Eight spacer nanowire (NW) channels are consistently formed by precise RIE process control and connected with naturally raised S/D as shown in Fig. 1(b). SiO2 dummy fins are removed by diluted HF to complete active region. After a 4.5-nm thick tunneling SiO2 is grown by a rapid
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for each sample is little, the uniformity of NW geometry and dielectric thicknesses are quite good.
3. Results and discussion
Fig. 1. Schematic fabrication process of IM and JL devices.
thermal oxidation (RTO) process and a 3-nm thick SiN is deposited by a LPCVD system for all samples, some samples are sent to simply deposit a 7-nm thick HfO2 to form HN BETL by a metal–organic chemical vapor deposition (MOCVD) system. Other samples are sent to perform RTO process at 1000 °C for 30 s for an ultra-thin SiON layer and deposit a 7-nm thick HfO2 to complete HON BETL. The SiON layer is thermally grown since it is reported to have better interface with SiN when compared to a deposited one [10]. An 18-nm thick Al2O3 is then deposited as blocking layer by a MOCVD system; a 300-nm thick TiN is deposited as metal gate by a physical vapor deposition. All samples are defined and etched to form gate region as shown in Fig. 1(c). Phosphorous implantation (at 30 keV to a dose of 5 1015 cm 2) and activation (900 °C for 30 s) are performed on IM samples for N+ doped S/D. Passivation and metallization processes are performed on all samples, followed by sintering at 400 °C for 30 min to complete the device fabrication. The channel width and length of devices used for characteristic measurements are 1.1 and 1.0 lm, respectively. About eight devices of each sample are tested in every measurement. The measured data are shown in average values. Since the data deviation
Fig. 2 shows the cross-sectional transmission electron microscopy (TEM) image of the JL device with HON BETL (JL-HON). An NW width of 25 nm is clearly observed, which is small enough for JL devices to be turned off. Although the thermally formed SiON is not clear on the TEM image due to the smooth interface of SiON/SiN [10], the effects of HON BETL can still be observed by the electrical characteristics shown later. The total EOT of IM and JL devices are about 15.5 nm, since the k value of Al2O3 is 9, Si3N4 is about 7.5 and HfO2 is 18 [11,12]. The transfer characteristics of IM and JL devices at drain voltage (VDS) = 0.5 V are shown in Fig. 3. The JL devices show clear transfer characteristics, which indicates that their doped channels with the NW width of 25 nm can be effectively depleted. The on-currents of the JL devices are lower than that of the IM ones mainly due to the lower implantation dose of doped channel formation. The oncurrent of the JL-HON device is a little smaller than that of the JL one with HN BETL (JL-HN). It is because the process temperature during SiON formation leads to dopant segregation and decreases the effective channel doping of the JL-HON device. The erasing speed of JL flash memory device can be enhanced by a lower n-type channel doping [5]. Fig. 4(a) shows the programming speeds of IM and JL devices at gate voltage (VGS) = 15 V. The programming and erasing (P/E) operations in this work are all performed by the Fowler– Nordheim tunneling mechanism. The threshold voltage (Vth) shift in Fig. 4(a) refers to the Vth of erase state. The programming speed of the IM device with HON BETL (IM-HON) is faster than that with HN BETL (IM-HN), since the SiON energy barrier of HON BETL increases the electron scattering as the band diagram shown in Fig. 4(b). Thus, the programing capture efficiency is improved [8,9]. As for the JL devices, the programming speed of the JL-HON device is similar to that of JL-HN one. Because a very thin SiON in HON CTL is formed from HN by a RTO on Si3N4 (N) and then a HfO2 (H) deposition, the channel doping of HON device is lower than that of HN one due to dopant segregation. Hence, the lower effective channel doping of JL-HON device results in less electron injection as compared to JL-HN one. Although the lower effective channel doping of JL-HON device results in less electron injection [5], the better capture of injected carriers by HON BETL compensates this disadvantage. Fig. 5(a) shows the erasing speeds at VGS = 15 V. Devices are programmed for 1 s before erasing speed measurement. The Vth
Fig. 2. Cross-sectional TEM image of JL poly-Si flash device with HON BETL.
H.-K. Fang et al. / Microelectronic Engineering 138 (2015) 107–110
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Fig. 3. Transfer characteristics of IM and JL devices at VDS = 0.5 V.
shift refers to the Vth of program state. The erasing speed of the IMHON device is similar to that of the IM-HN one, since the valence band level of SiN is higher than that of both HfO2 and SiON as shown in Fig. 5(b). The valence band barriers of HfO2 and SiON result in similar hole trappings during erasing operation [9]. The JL-HON device shows slightly faster erasing speed than the JL-HN one because the majority carriers in n-type doped channel are slightly decreased and the minority carriers are increased by the dopant segregation during SiON formation [5]. More holes are injected to improve the erasing efficiency. Fig. 6(a) shows retention characteristics of IM and JL devices tested at 85 °C with an initial window of 2.5 V. Both IM and JL devices perform improved retention characteristics when HON BETL is introduced. It is because the conduction band level of SiON is higher and the trap density of SiON is lower when compared to those of SiN [10]. Trapped charges in HfO2 are better kept by SiON [9]. It is also worthwhile to mention that no improvement is observed when the RTO process for SiON formation is replaced simply by a rapid thermal annealing process in N2 gas at the same
Fig. 4. (a) Programming speed of IM and JL devices at VGS = 15 V. (b) Band diagram at the beginning of programing operation.
Fig. 5. (a) Erasing speed of IM and JL devices at VGS = beginning of erasing operation.
15 V. (b) Band diagram at the
Fig. 6. (a) Retention characteristics of IM and JL devices measured at 85 °C. (b) Endurance characteristics of IM and JL devices with an initial window of 2 V.
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temperature for the same time (not shown). Therefore, it can be believed that the retention performances are improved by the SiON formation. The retention of JL devices is better than IM ones due to less electron detrapping from CTL since the channel doping of the JL device is higher than that of IM one [5]. The endurance characteristics of IM and JL devices are shown in Fig. 6(b). The P/E cycling conditions are chosen for an initial window of 2 V and the conditions are fixed during endurance test. The IM-HON device performs better endurance characteristics than the IM-HN one since the programming time of the former is shorter, leading to the less interface state (Dit) generation. The endurance characteristics of JL-HON and JL-HN device are similar and the Vth roll-ups of both devices are minor. It is because the JL device is less sensitive to Dit generation due to its bulk conduction mechanism. 4. Conclusions Effects of HON BETL on operation characteristics of IM and JL poly-Si flash memory devices are studied for the first time. For IM devices, better programming speed, retention and endurance characteristics are obtained with HON BETL while without degrading the erasing speed when compared to HN BETL. On the other hand, the JL device with HON BETL shows clearly improved retention characteristics and slightly faster erasing speed without sacrificing its programming speed. A 2 V memory window is maintained after 104 P/E cycles and the window closure is minor.
Therefore, reliability characteristics of poly-Si flash memory devices can be clearly improved by a HON BETL. References [1] H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, A. Nitayama, V.L.S.I. Symp, Tech. Dig. (2007) 14–15. [2] J. Jang, H.S. Kim, W. Cho, H. Cho, J. Kim, S.I. Shim, Y. Jang, J.H. Jeong, B.K. Son, D.W. Kim Kihyun, J.J. Shim, J.S. Lim, K.H. Kim, S.Y. Yi, J.Y. Lim, D. Chung, H.C. Moon, S. Hwang, J.W. Lee, Y.H. Son, U.I. Chung, W.S. Lee, VLSI Symp. Tech. Dig. (2009) 192–193. [3] H.T. Lue, T.H. Hsu, Y.H. Hsiao, S. Hong, M. Wu, F. Hsu, N. Lien, S.Y. Wang, J.Y. Hsieh, L.W. Yang, T. Yang, K.C. Chen, K.Y. Hsieh, C.Y. Lu, V.L.S.I. Symp, Tech. Dig. (2010) 131–132. [4] J.P. Colinge, C.W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy, R. Murphy, Nat. Nanotechnol. 5 (2010) 225–229. [5] Y. Sun, H.Y. Yu, N. Singh, K.C. Leong, E. Gnani, G. Baccarani, G.Q. Lo, D.L. Kwong, I.E.E.E. Trans, Electron Devices 58 (2011) 1329–1335. [6] C.J. Su, T.K. Su, T.I. Tsai, H.C. Lin, T.Y. Huang, Nanoscale Res. Lett. 7 (2012) 1–6. [7] C. Sandhya, U. Ganguly, K.K. Singh, P.K. Singh, C. Olsen, S.M. Seutter, R. Hung, G. Conti, K. Ahmed, N. Krishna, J. Vasi, S. Mahapatra, IRPS (2008) 406–411. [8] Z.L. Huo, J.K. Yang, S.H. Lim, S.J. Baik, J.L. Lee, J.H. Han, I.S. Yeo, U.I. Chung, J.T. Moon, B.L. Ryu, VLSI Symp. Tech. Dig. (2007) 138–139. [9] Z.H. Ye, K.S. Chang-Liao, C.Y. Tsai, T.T. Tsai, T.K. Wang, IEEE Electron Device Lett. 33 (10) (2012) 1351–1353. [10] H. Wong, M.C. Poon, Y. Gao, T.C.W. Kok, J. Electrochem. Soc. 148 (2001) 275– 278. [11] X. Guo, T.P. Ma, IEEE Electron Device Lett. 19(6) (1998) 207–209. [12] F. Chung-Hao, K.-S. Chang-Liao, C.-C. Li, Z.-H. Ye, F.-M. Hsu, T.-K. Wang, Y.-J. Lee, M.-J. Tsai, Appl. Phys. Lett. 101 (2012) 032105.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Effects of HfO2/SiON/SiN stacked trapping layer on operation characteristics of poly-Si flash memory devices Hsin-Kai Fang, Kuei-Shu Chang-Liao ⇑, Chun-Yuan Chen, Hao-Wei Ho Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan, ROC
a r t i c l e
i n f o
Article history: Received 1 August 2014 Received in revised form 30 January 2015 Accepted 21 February 2015 Available online 11 March 2015 Keywords: Poly-Si Junctionless Charge-trapping HfO2 Si3N4 Flash memory
a b s t r a c t A HfO2/SiON/SiN (HON) bandgap-engineered trapping layer (BETL) on inversion-mode (IM) and junctionless (JL) polycrystalline-Si flash memory devices is investigated in this work. The HON layer is formed by performing a rapid thermal oxidation process between the depositions of SiN and HfO2. For IM device, the programming speed, retention and endurance characteristics are improved by the HON BETL while without degrading its erasing speed when compared to that with HfO2/SiN (HN) BETL. As to the JL device, improved erasing speed and retention characteristics are obtained with HON BETL; high programming speed and good endurance performances of the JL device are also observed. HON BETL is promising to improve retention characteristics of poly-Si flash memory devices since the conduction band level of SiON is higher and the trap density of SiON is lower as compared to those of SiN. Ó 2015 Elsevier B.V. All rights reserved.
1. Introduction For the increasing demand of NAND flash memory cells, polycrystalline channel material is becoming attractive for three-dimensional (3-D) integration [1–3]. An advanced junction engineering is necessary since source/drain (S/D) definition and implantation are hardly achieved for 3-D architecture. A ‘‘junctionless (JL)’’ concept is reported to replace the conventional junction formation process by homogeneously doping source, drain and channel [4]; no junction is formed and the fabrication process is simplified. The operation speeds of JL flash memory devices are greatly affected by the channel doping conditions. For n-channel JL flash device with SiN trapping layer, heavier channel doping results in faster programming speed but it sacrifices erasing speed due to its lower hole concentration [5,6]. Bandgap-engineered trapping layer (BETL) is very promising to replace single SiN trapping layer since better operation speeds and reliability characteristics can be achieved by well stacking trapping layer materials with different bandgaps [7–9]. SiN/SiON/SiN BETL and those others with similar band structure are reported to demonstrate improved operation characteristics since the trapped charges are well distributed by a larger bandgap of their middle trapping layer [7–9]. However, most of the BETL studies are based on bulk planar devices. The study of BETL on polycrystalline-Si (poly-Si) channel ⇑ Corresponding author. E-mail address: [email protected] (K.-S. Chang-Liao). http://dx.doi.org/10.1016/j.mee.2015.02.044 0167-9317/Ó 2015 Elsevier B.V. All rights reserved.
device is rarely seen and its effects on junctionless device are not yet reported. In this work, effects of HfO2/SiON/SiN (HON) BETL on the operation characteristics of both inversion-mode (IM) and JL poly-Si flash device are investigated for the first time. Operation characteristics of HON and HfO2/SiN (HN) BETL on IM and JL poly-Si device are compared as well.
2. Device fabrication IM and JL flash memory devices are both fabricated on 6-inch Si wafers. The fabrication process of IM and JL nanowire devices is shown in Fig. 1. A 200-nm thick SiO2 is firstly grown by a lowpressure chemical vapor deposition (LPCVD) system. A 50-nm thick Si3N4 buried layer is deposited, followed by an 100-nm thick SiO2 by LPCVD systems. Four SiO2 dummy fins with a height of 100 nm are formed by I-line lithography and reactive ion etching (RIE) processes as shown in Fig. 1(a). An 100-nm thick amorphous-Si is then deposited and transferred into poly-Si by solid-phase crystallization (SPC) process at 600 °C for 24 h. Phosphorous implantation (at 30 keV to a dose of 1 1013 cm 2) and activation (900 °C for 30 s) are performed on JL samples without any lithography definition. After that, S/D region is defined on two ends of dummy fins for all samples. Eight spacer nanowire (NW) channels are consistently formed by precise RIE process control and connected with naturally raised S/D as shown in Fig. 1(b). SiO2 dummy fins are removed by diluted HF to complete active region. After a 4.5-nm thick tunneling SiO2 is grown by a rapid
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for each sample is little, the uniformity of NW geometry and dielectric thicknesses are quite good.
3. Results and discussion
Fig. 1. Schematic fabrication process of IM and JL devices.
thermal oxidation (RTO) process and a 3-nm thick SiN is deposited by a LPCVD system for all samples, some samples are sent to simply deposit a 7-nm thick HfO2 to form HN BETL by a metal–organic chemical vapor deposition (MOCVD) system. Other samples are sent to perform RTO process at 1000 °C for 30 s for an ultra-thin SiON layer and deposit a 7-nm thick HfO2 to complete HON BETL. The SiON layer is thermally grown since it is reported to have better interface with SiN when compared to a deposited one [10]. An 18-nm thick Al2O3 is then deposited as blocking layer by a MOCVD system; a 300-nm thick TiN is deposited as metal gate by a physical vapor deposition. All samples are defined and etched to form gate region as shown in Fig. 1(c). Phosphorous implantation (at 30 keV to a dose of 5 1015 cm 2) and activation (900 °C for 30 s) are performed on IM samples for N+ doped S/D. Passivation and metallization processes are performed on all samples, followed by sintering at 400 °C for 30 min to complete the device fabrication. The channel width and length of devices used for characteristic measurements are 1.1 and 1.0 lm, respectively. About eight devices of each sample are tested in every measurement. The measured data are shown in average values. Since the data deviation
Fig. 2 shows the cross-sectional transmission electron microscopy (TEM) image of the JL device with HON BETL (JL-HON). An NW width of 25 nm is clearly observed, which is small enough for JL devices to be turned off. Although the thermally formed SiON is not clear on the TEM image due to the smooth interface of SiON/SiN [10], the effects of HON BETL can still be observed by the electrical characteristics shown later. The total EOT of IM and JL devices are about 15.5 nm, since the k value of Al2O3 is 9, Si3N4 is about 7.5 and HfO2 is 18 [11,12]. The transfer characteristics of IM and JL devices at drain voltage (VDS) = 0.5 V are shown in Fig. 3. The JL devices show clear transfer characteristics, which indicates that their doped channels with the NW width of 25 nm can be effectively depleted. The on-currents of the JL devices are lower than that of the IM ones mainly due to the lower implantation dose of doped channel formation. The oncurrent of the JL-HON device is a little smaller than that of the JL one with HN BETL (JL-HN). It is because the process temperature during SiON formation leads to dopant segregation and decreases the effective channel doping of the JL-HON device. The erasing speed of JL flash memory device can be enhanced by a lower n-type channel doping [5]. Fig. 4(a) shows the programming speeds of IM and JL devices at gate voltage (VGS) = 15 V. The programming and erasing (P/E) operations in this work are all performed by the Fowler– Nordheim tunneling mechanism. The threshold voltage (Vth) shift in Fig. 4(a) refers to the Vth of erase state. The programming speed of the IM device with HON BETL (IM-HON) is faster than that with HN BETL (IM-HN), since the SiON energy barrier of HON BETL increases the electron scattering as the band diagram shown in Fig. 4(b). Thus, the programing capture efficiency is improved [8,9]. As for the JL devices, the programming speed of the JL-HON device is similar to that of JL-HN one. Because a very thin SiON in HON CTL is formed from HN by a RTO on Si3N4 (N) and then a HfO2 (H) deposition, the channel doping of HON device is lower than that of HN one due to dopant segregation. Hence, the lower effective channel doping of JL-HON device results in less electron injection as compared to JL-HN one. Although the lower effective channel doping of JL-HON device results in less electron injection [5], the better capture of injected carriers by HON BETL compensates this disadvantage. Fig. 5(a) shows the erasing speeds at VGS = 15 V. Devices are programmed for 1 s before erasing speed measurement. The Vth
Fig. 2. Cross-sectional TEM image of JL poly-Si flash device with HON BETL.
H.-K. Fang et al. / Microelectronic Engineering 138 (2015) 107–110
109
Fig. 3. Transfer characteristics of IM and JL devices at VDS = 0.5 V.
shift refers to the Vth of program state. The erasing speed of the IMHON device is similar to that of the IM-HN one, since the valence band level of SiN is higher than that of both HfO2 and SiON as shown in Fig. 5(b). The valence band barriers of HfO2 and SiON result in similar hole trappings during erasing operation [9]. The JL-HON device shows slightly faster erasing speed than the JL-HN one because the majority carriers in n-type doped channel are slightly decreased and the minority carriers are increased by the dopant segregation during SiON formation [5]. More holes are injected to improve the erasing efficiency. Fig. 6(a) shows retention characteristics of IM and JL devices tested at 85 °C with an initial window of 2.5 V. Both IM and JL devices perform improved retention characteristics when HON BETL is introduced. It is because the conduction band level of SiON is higher and the trap density of SiON is lower when compared to those of SiN [10]. Trapped charges in HfO2 are better kept by SiON [9]. It is also worthwhile to mention that no improvement is observed when the RTO process for SiON formation is replaced simply by a rapid thermal annealing process in N2 gas at the same
Fig. 4. (a) Programming speed of IM and JL devices at VGS = 15 V. (b) Band diagram at the beginning of programing operation.
Fig. 5. (a) Erasing speed of IM and JL devices at VGS = beginning of erasing operation.
15 V. (b) Band diagram at the
Fig. 6. (a) Retention characteristics of IM and JL devices measured at 85 °C. (b) Endurance characteristics of IM and JL devices with an initial window of 2 V.
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temperature for the same time (not shown). Therefore, it can be believed that the retention performances are improved by the SiON formation. The retention of JL devices is better than IM ones due to less electron detrapping from CTL since the channel doping of the JL device is higher than that of IM one [5]. The endurance characteristics of IM and JL devices are shown in Fig. 6(b). The P/E cycling conditions are chosen for an initial window of 2 V and the conditions are fixed during endurance test. The IM-HON device performs better endurance characteristics than the IM-HN one since the programming time of the former is shorter, leading to the less interface state (Dit) generation. The endurance characteristics of JL-HON and JL-HN device are similar and the Vth roll-ups of both devices are minor. It is because the JL device is less sensitive to Dit generation due to its bulk conduction mechanism. 4. Conclusions Effects of HON BETL on operation characteristics of IM and JL poly-Si flash memory devices are studied for the first time. For IM devices, better programming speed, retention and endurance characteristics are obtained with HON BETL while without degrading the erasing speed when compared to HN BETL. On the other hand, the JL device with HON BETL shows clearly improved retention characteristics and slightly faster erasing speed without sacrificing its programming speed. A 2 V memory window is maintained after 104 P/E cycles and the window closure is minor.
Therefore, reliability characteristics of poly-Si flash memory devices can be clearly improved by a HON BETL. References [1] H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, A. Nitayama, V.L.S.I. Symp, Tech. Dig. (2007) 14–15. [2] J. Jang, H.S. Kim, W. Cho, H. Cho, J. Kim, S.I. Shim, Y. Jang, J.H. Jeong, B.K. Son, D.W. Kim Kihyun, J.J. Shim, J.S. Lim, K.H. Kim, S.Y. Yi, J.Y. Lim, D. Chung, H.C. Moon, S. Hwang, J.W. Lee, Y.H. Son, U.I. Chung, W.S. Lee, VLSI Symp. Tech. Dig. (2009) 192–193. [3] H.T. Lue, T.H. Hsu, Y.H. Hsiao, S. Hong, M. Wu, F. Hsu, N. Lien, S.Y. Wang, J.Y. Hsieh, L.W. Yang, T. Yang, K.C. Chen, K.Y. Hsieh, C.Y. Lu, V.L.S.I. Symp, Tech. Dig. (2010) 131–132. [4] J.P. Colinge, C.W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy, R. Murphy, Nat. Nanotechnol. 5 (2010) 225–229. [5] Y. Sun, H.Y. Yu, N. Singh, K.C. Leong, E. Gnani, G. Baccarani, G.Q. Lo, D.L. Kwong, I.E.E.E. Trans, Electron Devices 58 (2011) 1329–1335. [6] C.J. Su, T.K. Su, T.I. Tsai, H.C. Lin, T.Y. Huang, Nanoscale Res. Lett. 7 (2012) 1–6. [7] C. Sandhya, U. Ganguly, K.K. Singh, P.K. Singh, C. Olsen, S.M. Seutter, R. Hung, G. Conti, K. Ahmed, N. Krishna, J. Vasi, S. Mahapatra, IRPS (2008) 406–411. [8] Z.L. Huo, J.K. Yang, S.H. Lim, S.J. Baik, J.L. Lee, J.H. Han, I.S. Yeo, U.I. Chung, J.T. Moon, B.L. Ryu, VLSI Symp. Tech. Dig. (2007) 138–139. [9] Z.H. Ye, K.S. Chang-Liao, C.Y. Tsai, T.T. Tsai, T.K. Wang, IEEE Electron Device Lett. 33 (10) (2012) 1351–1353. [10] H. Wong, M.C. Poon, Y. Gao, T.C.W. Kok, J. Electrochem. Soc. 148 (2001) 275– 278. [11] X. Guo, T.P. Ma, IEEE Electron Device Lett. 19(6) (1998) 207–209. [12] F. Chung-Hao, K.-S. Chang-Liao, C.-C. Li, Z.-H. Ye, F.-M. Hsu, T.-K. Wang, Y.-J. Lee, M.-J. Tsai, Appl. Phys. Lett. 101 (2012) 032105.