- Email: [email protected]
Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory
Solid-State Electronics xxx (2015) xxx–xxx
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory Sangyong Park a, Seongwook Choi b,⇑, Kwang Sun Jun b, HuiJung Kim b, SungMan Rhee b, Young June Park b a b
Flash TD Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., Seoul, Republic of Korea Department of Electrical and Computer Engineering, Seoul National University, Seoul, Republic of Korea
a r t i c l e
i n f o
Article history: Available online xxxx Keywords: Charge trap memory SONOS Data retention Lifetime estimation Non-Arrhenius behavior Multiple activation energy
a b s t r a c t Non-Arrhenius behavior has been reported in a various temperature range for the retention time of CT Flash memories. In order to understand the physical origin of the multiple activation energy due to the non-Arrhenius behavior, we conduct a simulation study using a 3D self-consistent numerical simulator developed in-house. As a result, it is found that both vertical and lateral charge transport in the conduction band of nitride layer are responsible for the non-Arrhenius retention characteristic. Also, the tunneling current through the bottom oxide and a lifetime criteria are turned out to be the key parameters which determine the multiple activation energy. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction The Charge Trap (CT) Flash memory, based on the nitride trap layer, is one of the most promising candidates for next Flash memory generation due to its ability to be scaled down [1]. Especially, for the 3D vertical NAND (VNAND) flash structure, the CT type cell is an inevitable choice considering the ease of processing the 3D structures [2,3]. For actual production of flash cells, it is important to understand and properly model the data retention characteristics to guarantee the desired lifetime of the device. The widely used method predicting the data lifetime is an extrapolation using the activation energy, which is represented by the slope of the Arrhenius plot, as used in the conventional Floating Gate (FG) cell [4]. Usually, this method is used under the assumption that the activation energy is constant (satisfying Arrhenius equation) within the temperature of interest. However, it has been continuously reported that the Arrhenius plot shows not a straight line but shows the multiple activation energies [5,6]. Several experimental data showing the non-Arrhenius relation is summarized in Fig. 1(a) for FG cells and Fig. 1(b) for CT memory cells [5–11]. This characteristics give rise to the problem that the expected lifetime varies according to the choice of the activation energy depending on the stress temperatures.
⇑ Corresponding author. E-mail address: [email protected] (S. Choi).
It is more interesting that there are different kind of non-Arrhenius behavior in Fig. 1: A decrease of activation energy ((ii)–(iii) in Fig. 1(a), (iii) in Fig. 1(b)), an increase of activation energy ((iv) in Fig. 1(b)) and recovery after the decrease of activation energy ((iv) in Fig. 1(a)). Therefore, for more accurate prediction of the device lifetime, a physical mechanism of the retention phase related to the non-Arrhenius behavior should be understood. Some authors have been reported about the origin of the multiple activation energy in the CT memory but limited to the decreasing activation energy only [12]. Also, their theoretical model is based on the 1D model which cannot consider the lateral charge redistribution [12]. This may be problematic because, until recently, it has been continually reported that the lateral charge transport gives a significant effect to the charge retention [13,14]. The lateral migration was proved in many different ways, for example, the direct probing method (AFM) [15,16], electrical measurement [13,17] and theoretical simulation [13]. This lateral leakage cannot be eliminated by separating the nitride region for each cells because of the reliability degradation due to the cutting of the nitride layer [17]. Moreover, the nitride layer cannot be separated at all for 3D VNAND structure. Hence, it is crucial to consider the comprehensive models including the lateral transport for modeling the retention phase. However, to the authors best knowledge, most of previous retention modeling and simulation works do not comprehensively considers the structural and physical effects; Some model does not consider the electron transport in the nitride region [12]. Others tried to include all the physical equations, yet they are limited in
http://dx.doi.org/10.1016/j.sse.2015.05.026 0038-1101/Ó 2015 Elsevier Ltd. All rights reserved.
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026
2
S. Park et al. / Solid-State Electronics xxx (2015) xxx–xxx
Fig. 2. Simulated structures of the SA-STI SANOS device with continuous nitride (Si3N4). The electron transport in the whole nitride region is calculated. We use Gate 1 for the program and retention while other cells are biased with 0 V.
the adjacent cells by the lateral charge spreading can be found in elsewhere [21]. 2.2. Simulation models
Fig. 1. Arrhenius plot for the retention time extracted from experimental data of (a) Floating Gate (FG) cells and (b) Charge Trapping memories. The percentage represents the criteria for the retention time.
the 1 dimensional simulation [17]. There is a report considering the 2D lateral transport [18]but it does not calculate the tunneling component and the channel region. Only recently, one can find some efforts to include 3D comprehensive model to the retention phase simulation [19,20] including author’s previous work [21]. In this context, it is worthwhile to study the retention characteristics with 3D comprehensive physical models including the lateral/vertical transport, trapping/de-trapping and tunneling in a self-consistent manner. Hence, in this paper, we used the self-consistent 3D CT memory simulator [21–23] for investigating the non-Arrhenius behavior to explain all the trends in Fig. 1. In this way, the relationship between the multiple activation energies according to the temperature range and the stored charge transport in lateral as well as vertical direction could be understood. The P/E cycling also play a central role for the retention as well as the lateral diffusion [14]. But, please note that it is beyond the scope of this paper to consider the new trap generation during the P/E cycling. Here, the pre-stress characteristic condition is only considered here because the pre-stress measurement data in Fig. 1 indicates the non-Arrhenius behavior. Based on the work on the pre-stress condition, we expect that the acceleration of retention due to the P/E cycling also could be accurately modeled.
2. Simulation structure and physics 2.1. Simulation structure The simulation structures are based on SA-STI (Self-Aligned STI) SANOS (Si/Al2O3/Si3N4/SiO2/Si) device with 4 nm tunneling oxide, 8 nm Si3N4, 14 nm Al2O3, and 30 nm channel length. In order to include the actual CT memory structure, the trap layer (Si3N4) is continuous along the active line as shown in Fig. 2. Because of the continuous trap layer, there is a leakage current in the lateral direction through this continuous layer. In this study, three adjacent cells are simulated and the device at the center (Gate 1 in Fig. 2) are programmed only while the adjacent cells (Gate 0 and Gate 2 in Fig. 2) are biased with 0 V. More study of the effect on
For the comprehensive model for the CT memory cells, we included following key physics in our simulation code: (1) tunneling from the nitride trap to substrate conduction band, (2) tunneling from the nitride conduction band to substrate conduction band, (3) transport of trapped electron (via SRH and Poole Frankel), (4) transport in the nitride conduction band, (5) transport in the substrate channel region. We used a 3D in-house simulation code built for CT memory devices. Some key master equations and details for each mechanisms are summarized in the following [21–23]. 2.2.1. The tunneling current through the tunneling oxide The non-local tunneling current (J n ) through the tunneling (bottom) oxide is calculated with
J n ¼ mqnT ox
ð1Þ
where n is a charge concentration in the conduction band or traps, T ox is a tunneling probability of the bottom oxide calculated by the WKB approximation and m is a hitting frequency. For the programming phase, n is the charge concentration in the substrate m is a hitting frequency in the quasi-bound state which is an electric field dependent at the channel surface. 2.2.2. The trapped charge loss mechanism The transport of trapped charge is calculated using the Poole– Frankel model which can be written as
pffiffiffi! @nc Et b E nT ¼ r J n cn NT nc þ m exp kB T @t
ð2Þ
where nc is a charge concentration in the conduction band, N T is a concentration of traps with an energy level Et ; b is the Frenkel constant, E is a local electric field, cn and m are constants. This equation is solved for the entire nitride region in 3D space. 2.2.3. The transport of carriers in the nitride conduction band The electron transport in the nitride conduction band is solved with the drift–diffusion formalism than can be written as
J n ¼ qln nc E þ qDn rnc
ð3Þ
where ln is a mobility and Dn is a diffusion constant. This equation is also solved for the entire nitride region in 3D space. 2.2.4. Density gradient The electron distribution in the channel region is calculated with the density-gradient formalism with quantum potential
pffiffiffi
r ðbn r nÞ
pffiffiffi n w ¼0 2 qn
ð4Þ
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026
S. Park et al. / Solid-State Electronics xxx (2015) xxx–xxx
where ln is a mobility and Dn is a diffusion constant. In case of the high electric field at the channel, the narrow potential well is formed at the channel surface, so the quantum correction can give more accurate electron density. Hence, more accurate tunneling current can be calculated compared to classical drift diffusion formalism [24].
2.2.5. Simulation parameters The simulation parameters such as a trap position/energy, capture/emission rate and tunneling probabilities are calibrated with own experimental data [22] and agree with that of literature [13] within the same order of magnitude. The detailed descriptions about the model and the calibration with the experimental data are well presented in [22,23]. In this simulation study, an initial charge distribution for the retention simulation is extracted from the 3D simulation after programming until the threshold voltage shift reaches to 4 V. More simulation results including data in this paper can also be found in elsewhere [21,23].
3. Simulation results 3.1. Programming phase Prior to the retention simulation, the programming phase is calculated which will be used for the initial condition for the retention simulation. The electron profile when the threshold voltage shift becomes 4 V is selected for each oxide thickness as an initial condition thus the programming time before the retention simulation is different if the device and operation condition is different (such as oxide thickness and temperature). As an example of 4 nm tunneling oxide case, the electron distribution at the conduction band and trap during the programming stage are shown in Fig. 3 for each programming time from 106 s to 0.1 s. At the early stage of programming, electrons are piled up near the bottom (tunneling) oxide side. However, at later time, the electron profile shows higher concentration at the top (blocking) oxide side. This is because the direction of electron field at the programming phase as shown in Fig. 3 so the electrons are swept from the bottom oxide side to the top oxide side. It is worthwhile to mention that the
Fig. 3. Vertical electron profile during the programming stage in the trap state (a) and the conduction band (b) of the nitride layer. The tunneling oxide thickness is 4.0 nm and programming temperature is 500 K. The electron is injected from the bottom oxide side at the position of 0 nm.
3
programming characteristics in Fig. 3 are similar to that using 1D simulation reported in [12].
3.2. Retention phase We plot retention vs bake time at a temperature range of 300– 550 K for devices with various tunneling oxide thickness in Fig. 4. It is interesting to point out that the retention curves at lower temperature are dented for thin oxide cases (2.4 nm and 2.6 nm). In order to investigate effect of the dent point to the activation energy, we define the criteria for the retention time as the time for 15% charge loss (above the dent) and 20% charge loss (below the dent). The retention time vs. temperature is shown in Fig. 5(a) and (b) for both criteria, showing the different activation energy for different criterion. We define region-1, 2 and 3 according to the different slope in the Arrhenius plot. In the following subsections, we analyze the mechanisms for each region in detail.
4. Analysis on activation energy 4.1. Criterion above dent point The data retention time defined by 15% charge loss criterion vs 1=kB T is depicted in Fig. 5(a). The trend shows that the device with the oxide of 4 nm has a unique slope while thinner devices have a slope varying according to temperature. It is known that the Arrhenius plot shows unique activation energy when thermal emission is the dominant charge loss mechanism [4]. As the tunneling current becomes important for the cases of thinner oxide, the slope of the Arrhenius plots decreases in low temperature region. Thus, the different activation energy can be defined according to the different temperature regions. Region-1 in Fig. 5(a) represents a high temperature region which has the same activation energy as that of the tunneling free case (4 nm oxide). In order to identify the charge loss mechanism in this region, a transient distribution of trapped electrons in Region-1 (500 K for 2.4 nm oxide) is shown in Fig. 6(a). As shown in the figure, the thermal emission and lateral transport (Ilat ) is dominant than the tunneling charge loss and thus the data retention time is dependent on temperature in this region. In other words, Region-1 can be characterized as ‘Ilat -dominant’ region. The temperature region showing the reduced activation energy is called Region-2 in Fig. 5(a), in which the lateral charge transport and the tunneling charge loss is shown in Fig. 6(c)–(f). In this region, the direct tunneling current (Itun ), which is insensitive to temperature, becomes more dominant than the thermal emission and lateral transport. As a result, the thinner tunneling oxide causes more charge loss and reduces more data retention times. The independent characteristic of the regions on temperature is also more obvious in the thinner tunneling oxide because of the fact that the impact of the tunneling current becomes larger. Hence, Region-2 can be defined as ‘Itun -dominant’ region. The interplay of the two leakage mechanism – Ilat and Itun – according to the temperature is more clearly understood by comparing the two cases in Fig. 7: 4 nm and 2.8 nm oxide thickness. For the 4 nm oxide case, there are no tunneling current thus the trapped charge loss near the bottom oxide when the temperature is 500 K (Fig. 7(a)) is caused by Ilat only. As the temperature decreases to 300 K, Ilat is significantly reduced as can be seen in the lateral profile, Fig. 6(e). As a result, it is hard to identify the reduction of the trapped charge near the bottom oxide side in Fig. 7(e). Hence, Region-2 cannot be observed in devices with thicker oxide.
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026
4
S. Park et al. / Solid-State Electronics xxx (2015) xxx–xxx
Fig. 4. Simulated retention curves at various temperatures for 4 nm, 2.8 nm, 2.6 nm and 2.4 nm tunneling oxide devices. Two different criteria (15% and 20%) for extracting the Arrhenius plot are also indicated.
For device with 2.8 nm oxide, Itun now increase so that there are additional reduction of the trapped charge near the surface compared to that of 4.0 nm oxide (Compare the left and right figures
in Fig. 7). This additional reduction at the bottom oxide side varies a little as the temperature changes because Itun has very small activation energy. This tunneling effect on activation energy also agrees with the trend reported in [8] for the FG structure where the charge loss through an IPD layer is the dominant charge loss mechanism. Thus, the degradation of the activation energy reported in [5] can be explained by the tunneling leakage. It is worthwhile to note that, in Region-1, the retention time is smaller for the 4.0 nm case than that for the 2.8 nm case as shown in Fig. 5(a). At first glance, it may sound strange because the thicker tunneling oxide seems to give better retention characteristics. It is true if the initial electron profile before the retention phase are equivalent for the two cases. However, in our case, the initial electron profile is different because the profile is calculated when the threshold voltage shift reaches 4 V. Therefore, a total amount of the stored charge in the trap is larger for the device with 4 nm oxide. The difference in the initial charge density can be verified in Fig. 7(a) and (b). In the figure, the net amount of trapped charge between 4 nm and 8 nm (the charge accumulated near nitride/top oxide interface) for the device with 4 nm oxide is higher than that with 2.8 nm oxide. Hence, for the retention phase, the electric field is smaller for the device with 4 nm oxide as shown in Fig. 8. As a result, the electron in this region (moving left to right in Fig. 7) moves slower for the device with 4 nm oxide. Since the charge flows from left to right in Fig. 7 increases the threshold voltage shift, the device with 4 nm oxide shows lower threshold voltage and thus shows worse retention characteristics. 4.2. Criterion below the dent point
Fig. 5. Simulated Arrhenius plots of the various tunneling oxide thickness when the criterion is 15% (a) and 20% (b) charge loss. According to the criterion for the lifetime, the Arrhenius shows different characteristics.
The Arrhenius plots with the 20% charge loss criterion are depicted in Fig. 5(b). Unlike the case of the 15% charge loss criterion, the Arrhenius plots can be divided into three regions according to the slope that represents an activation energy. Here, Region-1 and Region-2 have the same meaning as stated for case of 15% criterion. Interestingly, the activation energy in Region-3 restores back to that in Region-1. Referring the tunneling current profile in Fig. 9,
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026
S. Park et al. / Solid-State Electronics xxx (2015) xxx–xxx
5
Fig. 6. Trapped electron density distributions of the 2.4 nm tunneling oxide structure along both the channel direction (left figures) and the vertical direction (right figures) at temperature 300 K, 400 K and 500 K from 105 s to 105 s.
the reason for the transition from Region-2 to Region-3 is due to a limitation of the tunneling current density. When there are no transition from Region-2 to Region-3 like the case of 2.8 nm oxide, the tunneling current continuously decreases as shown in Fig. 9(a). The decrease is due to the leakage by the lateral transport. But, in the case of 2.4 nm oxide, an abrupt change in the tunneling current can be found as shown in Fig. 9(b). This abrupt change appears at the transition time from Region-2 to Region-3 (between 102 s and 103 s). Because of the limitation of Itun ; Ilat becomes a dominant mechanism so the activation energy in Region-3 shows same one in Region-1 which is Ilat -dominant region. This abrupt change can be more clearly observed for various tunneling oxide thickness and temperature as shown in Fig. 10. In the figure, the tunneling current density at the center of the channel are plotted as the retention time and the cases for 300 K of temperature are shown with black lines while others are shown with gray lines. As the temperature increases, the tunneling current decreases faster for each oxide thickness due to the influence of Ilat , and this trend is general for all oxide thickness. However, for Itun -dominant cases, there are additional special case which shows an abrupt decrease of Itun at the temperature of 300 K. The start time of the abrupt change decreases as Itun increases, which is consistent of the appearance of Region-3. In sum, Region-3 is due to the limitation of Itun and the transition to Region-3 is accelerated for higher Itun . In order to explain the limitation of Itun , another current component should be defined called a supply current, Isup . When the trapped electron tunnels out from a nitride trap, the trap becomes
empty. Isup is a current that fills this empty trap via a lateral and vertical movement according to (2). The role of Isup for Region-3 can be explained by the electron distributions shown in Fig. 6(f). In order to retain a certain current level, the empty trap site after the tunneling should be filled by Isup . However, at the low temperatures, Isup is much smaller than Itun , thus traps becomes empty. the electrons near the interface are depleted and eventually become negligible as can be observed in Fig. 6(f). After the depletion, there are no source of electron tunneling which is n in Eq. (1) and thus Itun decreases abruptly as shown in Figs. 9 and 10. This is why there are the dent point in Fig. 4(c) and (d). Therefore, we can call Region-3 as a Isup -limited region. In this way, an additional charge loss is determined by electron transport (Isup ) only in Region-3, and the activation energy increases up to the tunneling free activation energy in Region-1. This phenomenon, which is a key finding in this study, is one of the effects caused by the electron transport at the trapping layer on the activation energy. 4.3. Summary and lifetime estimation In Table 1, we summarize the dominant current component and mechanisms for each region. For Region-1, the lateral current is a dominant loss mechanism. In Region-2, the tunneling current is a dominant loss mechanisms. In Region-3, the supply current determines the characteristics of retention by limiting the tunneling current. This limitation is due to the depletion region near the tunneling oxide surface. Note that unlike other tunneling mechanisms
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026
6
S. Park et al. / Solid-State Electronics xxx (2015) xxx–xxx
Fig. 7. Trapped electron density distributions of the 4.0 nm (left figures) and 2.8 nm (right figures) tunneling oxide structure along the vertical direction at the temperature of 300 K, 400 K and 500 K and with the retention time from 105 s to 105 s.
depletion of trapped electrons, Region-3 is not observed in Fig. 5(a). Hence, great cares are needed when estimating the lifetime projection in room temperature because of the multiple activation energies. For example, under the lifetime criterion of 20% shift, the prediction of the lifetime would be overestimated if the activation energy is extracted from the high temperature stress
Fig. 8. Electric field profile along the vertical direction of the nitride layer before the retention phase (or after programming phase with 4 V of a thereshold voltage shift. The electric field for the oxide thickness of 2.8 nm shows higher electric field than that of 4.0 nm. The direction of electric field is from the top oxide side to the bottom oxide side.
in MOSFET device such as Stress Induced Leakage Current, Itun in CT Flash memory devices has a limited source of tunneling. Therefore, if a source for the tunneling is depleted, the tunneling current is being limited. It is interesting point that the transition temperatures between regions are highly affected not only by a tunneling oxide thickness but also by the lifetime criterion as shown in Fig. 5(a) and (b). Moreover, since the 15% criterion can be satisfied before the
Fig. 9. Tunneling current profile along the lateral (channel) direction from 105 s to 105 s. The oxide thickness is 2.8 nm for (a) and 2.4 nm for (b) and the temperature is 300 K for both case.
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026
S. Park et al. / Solid-State Electronics xxx (2015) xxx–xxx
[3]
[4] [5]
[6]
[7]
[8]
[9] Fig. 10. Tunneling current density at the center of channel for all oxide thickness and temperatures. The thinner oxide gives higher tunneling current density at the early stage. The cases for 300 K are drawn with black lines and others are drawn with grey lines.
[10]
[11] Table 1 Mechanisms for each retention regions. Region
Mechanism
Description
I
Ilat dominant Itun dominant Isup limited
Lateral transport is a dominant loss mechanism
II III
[12]
[13]
Tunneling current is a dominant loss mechanism Tunneling electron should be supplied by lateral and vertical transport. Otherwise, the trapped electron near the surface would be depleted
condition. On the other hand, if the lifetime is extrapolated from Region-2, the retention time could be seriously underestimated. Therefore, for an accurate prediction of the reliability of the CT Flash memory, it is an essential prerequisite to understand the characteristics of multiple activation energy according to the lifetime criterion and device geometry.
[14]
[15]
[16]
[17]
[18]
5. Conclusion [19]
To investigate the activation energy of the CT Flash memory, the SANOS structures with various tunneling oxide thickness are simulated under a several temperatures considering the vertical and lateral charge transport. For the first time, we found that the Arrhenius plots of the simulation results are divided into three regions, resulting in the multiple activation energies. The decrease and increase of the activation energy according to the stress temperature condition can be understood with tunneling leakage and electron transport effect, respectively. Therefore, understanding of the multiple activation energy is necessary for an accurate prediction of the retention time. References [1] Lee W-S. Future memory technologies. In: International conference on solidstate and integrated-circuit technology (ICSICT); 2008. p. 1–4. [2] Jang J, Kim Hs, Choi W, Cho H, Kim J, Shim SI, Jang Y, Jeong Jh, Son Bk, Kim DW, Shim Jj, Lim, JS, Kim Kh, Yi SY, Lim Jy, Chung D, Moon Hc, Hwang S, Lee Jw, Son
[20]
[21]
[22]
[23]
[24]
7
Yh, in CU, Lee W-s. Vertical cell array using tcat (terabit cell array transistor) technology for ultra high density nand flash memory. In: VLSI Symp. Tech. Dig; 2009. p. 192–3. Tanaka H, Kido M, Yahashi K, Oomura M, Katsumata R, Kito M, Fukuzumi Y, Sato M, Nagata Y, Matsuoka Y, Iwata Y, Aochi H, Nitayama A. Bit cost scalable technology with punch and plug process for ultra high density flash memory. In: VLSI Symp. Tech. Dig; 2007. p. 14–15. Nozawa H, Kohyama S. A thermionic electron emission model for charge retention in sanos structures. Jpn J Appl Phys 1982;21(2):111. Molas G, Colonna JP, Kies R, Belhachemi D, Bocquet M, Gely M, et al. Investigation of charge-trap memories with AIN based band engineered storage layers. Solid-State Electron 2011;58:68–74. Kim J, Kang C, Chang Si, Kim J, Jeong Y, Park C, Kang Jh, Kim Sh, Hwang S, Choe Bi, Park J, Chung J, Park Y, Choi J, Chung C. New phenomena for the lifetime prediction of tanos based charge trap nand flash memory. In: Device research conference (DRC); 2010. p. 99–100. Govoreanu B, Houdt JV. On the roll-off of the activation energy plot in hightemperature flash memory retention tests and its impact on the reliability assessment. IEEE Electron Dev Lett 2008;29(2):177–9. Salvo BD, Ghibaudo G, Pananakakis G, Reimbold G, Mondond F, Guillaumot B, et al. Experimental and theoretical investigation of nonvolatile memory dataretention. IEEE Trans Electron Dev 1999;46:1518–24. Pellerin JP, Lalande F, Canet P, Bouchakour R, Jeuland F, Morancho L. Modeling charge variation during data retention of MLC flash memories. Microelectron Reliab 2009;49:1060–3. Lue HT, Wang SY, Hsiao YH, Lai EK, Yang LW, Yang T, Chen KC, Hsieh KY, Liu R, Lu CY. Reliability model of bandgap engineered sonos (be-sonos). In: Tech. Dig. Inter. Electron Dev. Meeting; 2006, p. 1 – 4. Compagnoni C, Spinelli AS, Lacaita AL. Experimental study of data retention in nitride memories by temperature and field acceleration. IEEE Electron Dev Lett 2007;28(7):628–30. Arreghini A, Akil N, Driussi F, Esseni D, Selmi L, van Duuren MJ. Long term charge retention dynamics of sonos cells. Solid-State Electron 2008;52:1460–6. Maconi A, Arreghini A, Compagnoni CM, den bosch GV, Spinelli AS, Houdt JV, et al. Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3d sonos devices. Solid-State Electron 2012;74:64–70. Shapira A, Shur Y, Diamand YS, Shappir A, Eitan B. Unified retention model for localized charge trapping nonvolatile memory device. Appl Phys Lett 2008;92:133514. Vianello E, Nowak E, Mariolle D, Chevalier N, Perniola L, Molas G, Colonna JP, Driussi F, Selmi L. Direct probing of trapped charge dynamics in sin by kelvin force microscopy. In: Int. Conf. on microelectronic test structures; 2010, p. 94– 97. Baik SJ, Lim KS, Choi W, Yoo H, Shin H. Charge diffusion in silicon nitrides: scalability assessment of nitride based flash memory. In: Int. Reliab. Phys. Symp; 2011. p. 650–5. Kang C, Choi J, Sim J, Lee C, Shin Y, Park J, Sel J, Jeon S, Park Y, Kim K. Effects of lateral charge spreading on the reliability of tanos (tan/alo/sin/oxide/si) nand flash memory. In: Int. Reliab. Phys. Symp; 2007. p. 167–9. Furn’emont A, Cacciato A, Breuil L, Rosmeulen M, Maes H, Meyer KD, et al. Physical understanding and modeling of sanos retention in programmed state. Solid State Electron 2008;52:577–83. Benvenuti A, Ghetti A, Mauri A, Liu H, Mouli C. Current status and future prospects of non-volatile memory modeling. In: Int. Conf. simulation of semiconductor processes and devices (SISPAD); 2014. p. 5–8. Lun Z, Liu S, He Y, Hou Y, Zhao K, Du G, Liu X, Wang Y. Investigation of retention behavior for 3d charge trapping nand flash memory by 2d selfconsistent simulation. In: Int. Conf. simulation of semiconductor processes and devices (SISPAD); 2014. p. 141–4. Park S, Choi S, Jeon KS, Kim HJ, Rhee SM, Yoon I, Park YJ. A 3d simulation of the lateral charge spreading effect in charge trapping nand flash memory. In: Int. Conf. simulation of semiconductor processes and devices (SISPAD); 2012. p. 376–9. Jeon KS, Choe KS, Choi S, Park SY, Park YJ. Modeling the geometric effects on programming characteristics for the tanos device by developing a 3d selfconsistent simulation. Solid-State Electron; 2013;79:117–24. Park S. Three dimensional simulation of retention characteristics of charge trap (ct) nand flash memory, Master’s thesis, Seoul Nat’l Univ., Seoul Nat’l Univ., Gwanack-gu, Seoul, Korea; 2013. Choi S, Baek C-K, Park S, Park YJ. An analysis of the field dependence of interface trap generation under negative bias temperature instability stress using wentzelkramersbrillouin with density gradient method. Japan J Appl Phys 2011;50:014302.
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory Sangyong Park a, Seongwook Choi b,⇑, Kwang Sun Jun b, HuiJung Kim b, SungMan Rhee b, Young June Park b a b
Flash TD Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., Seoul, Republic of Korea Department of Electrical and Computer Engineering, Seoul National University, Seoul, Republic of Korea
a r t i c l e
i n f o
Article history: Available online xxxx Keywords: Charge trap memory SONOS Data retention Lifetime estimation Non-Arrhenius behavior Multiple activation energy
a b s t r a c t Non-Arrhenius behavior has been reported in a various temperature range for the retention time of CT Flash memories. In order to understand the physical origin of the multiple activation energy due to the non-Arrhenius behavior, we conduct a simulation study using a 3D self-consistent numerical simulator developed in-house. As a result, it is found that both vertical and lateral charge transport in the conduction band of nitride layer are responsible for the non-Arrhenius retention characteristic. Also, the tunneling current through the bottom oxide and a lifetime criteria are turned out to be the key parameters which determine the multiple activation energy. Ó 2015 Elsevier Ltd. All rights reserved.
1. Introduction The Charge Trap (CT) Flash memory, based on the nitride trap layer, is one of the most promising candidates for next Flash memory generation due to its ability to be scaled down [1]. Especially, for the 3D vertical NAND (VNAND) flash structure, the CT type cell is an inevitable choice considering the ease of processing the 3D structures [2,3]. For actual production of flash cells, it is important to understand and properly model the data retention characteristics to guarantee the desired lifetime of the device. The widely used method predicting the data lifetime is an extrapolation using the activation energy, which is represented by the slope of the Arrhenius plot, as used in the conventional Floating Gate (FG) cell [4]. Usually, this method is used under the assumption that the activation energy is constant (satisfying Arrhenius equation) within the temperature of interest. However, it has been continuously reported that the Arrhenius plot shows not a straight line but shows the multiple activation energies [5,6]. Several experimental data showing the non-Arrhenius relation is summarized in Fig. 1(a) for FG cells and Fig. 1(b) for CT memory cells [5–11]. This characteristics give rise to the problem that the expected lifetime varies according to the choice of the activation energy depending on the stress temperatures.
⇑ Corresponding author. E-mail address: [email protected] (S. Choi).
It is more interesting that there are different kind of non-Arrhenius behavior in Fig. 1: A decrease of activation energy ((ii)–(iii) in Fig. 1(a), (iii) in Fig. 1(b)), an increase of activation energy ((iv) in Fig. 1(b)) and recovery after the decrease of activation energy ((iv) in Fig. 1(a)). Therefore, for more accurate prediction of the device lifetime, a physical mechanism of the retention phase related to the non-Arrhenius behavior should be understood. Some authors have been reported about the origin of the multiple activation energy in the CT memory but limited to the decreasing activation energy only [12]. Also, their theoretical model is based on the 1D model which cannot consider the lateral charge redistribution [12]. This may be problematic because, until recently, it has been continually reported that the lateral charge transport gives a significant effect to the charge retention [13,14]. The lateral migration was proved in many different ways, for example, the direct probing method (AFM) [15,16], electrical measurement [13,17] and theoretical simulation [13]. This lateral leakage cannot be eliminated by separating the nitride region for each cells because of the reliability degradation due to the cutting of the nitride layer [17]. Moreover, the nitride layer cannot be separated at all for 3D VNAND structure. Hence, it is crucial to consider the comprehensive models including the lateral transport for modeling the retention phase. However, to the authors best knowledge, most of previous retention modeling and simulation works do not comprehensively considers the structural and physical effects; Some model does not consider the electron transport in the nitride region [12]. Others tried to include all the physical equations, yet they are limited in
http://dx.doi.org/10.1016/j.sse.2015.05.026 0038-1101/Ó 2015 Elsevier Ltd. All rights reserved.
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026
2
S. Park et al. / Solid-State Electronics xxx (2015) xxx–xxx
Fig. 2. Simulated structures of the SA-STI SANOS device with continuous nitride (Si3N4). The electron transport in the whole nitride region is calculated. We use Gate 1 for the program and retention while other cells are biased with 0 V.
the adjacent cells by the lateral charge spreading can be found in elsewhere [21]. 2.2. Simulation models
Fig. 1. Arrhenius plot for the retention time extracted from experimental data of (a) Floating Gate (FG) cells and (b) Charge Trapping memories. The percentage represents the criteria for the retention time.
the 1 dimensional simulation [17]. There is a report considering the 2D lateral transport [18]but it does not calculate the tunneling component and the channel region. Only recently, one can find some efforts to include 3D comprehensive model to the retention phase simulation [19,20] including author’s previous work [21]. In this context, it is worthwhile to study the retention characteristics with 3D comprehensive physical models including the lateral/vertical transport, trapping/de-trapping and tunneling in a self-consistent manner. Hence, in this paper, we used the self-consistent 3D CT memory simulator [21–23] for investigating the non-Arrhenius behavior to explain all the trends in Fig. 1. In this way, the relationship between the multiple activation energies according to the temperature range and the stored charge transport in lateral as well as vertical direction could be understood. The P/E cycling also play a central role for the retention as well as the lateral diffusion [14]. But, please note that it is beyond the scope of this paper to consider the new trap generation during the P/E cycling. Here, the pre-stress characteristic condition is only considered here because the pre-stress measurement data in Fig. 1 indicates the non-Arrhenius behavior. Based on the work on the pre-stress condition, we expect that the acceleration of retention due to the P/E cycling also could be accurately modeled.
2. Simulation structure and physics 2.1. Simulation structure The simulation structures are based on SA-STI (Self-Aligned STI) SANOS (Si/Al2O3/Si3N4/SiO2/Si) device with 4 nm tunneling oxide, 8 nm Si3N4, 14 nm Al2O3, and 30 nm channel length. In order to include the actual CT memory structure, the trap layer (Si3N4) is continuous along the active line as shown in Fig. 2. Because of the continuous trap layer, there is a leakage current in the lateral direction through this continuous layer. In this study, three adjacent cells are simulated and the device at the center (Gate 1 in Fig. 2) are programmed only while the adjacent cells (Gate 0 and Gate 2 in Fig. 2) are biased with 0 V. More study of the effect on
For the comprehensive model for the CT memory cells, we included following key physics in our simulation code: (1) tunneling from the nitride trap to substrate conduction band, (2) tunneling from the nitride conduction band to substrate conduction band, (3) transport of trapped electron (via SRH and Poole Frankel), (4) transport in the nitride conduction band, (5) transport in the substrate channel region. We used a 3D in-house simulation code built for CT memory devices. Some key master equations and details for each mechanisms are summarized in the following [21–23]. 2.2.1. The tunneling current through the tunneling oxide The non-local tunneling current (J n ) through the tunneling (bottom) oxide is calculated with
J n ¼ mqnT ox
ð1Þ
where n is a charge concentration in the conduction band or traps, T ox is a tunneling probability of the bottom oxide calculated by the WKB approximation and m is a hitting frequency. For the programming phase, n is the charge concentration in the substrate m is a hitting frequency in the quasi-bound state which is an electric field dependent at the channel surface. 2.2.2. The trapped charge loss mechanism The transport of trapped charge is calculated using the Poole– Frankel model which can be written as
pffiffiffi! @nc Et b E nT ¼ r J n cn NT nc þ m exp kB T @t
ð2Þ
where nc is a charge concentration in the conduction band, N T is a concentration of traps with an energy level Et ; b is the Frenkel constant, E is a local electric field, cn and m are constants. This equation is solved for the entire nitride region in 3D space. 2.2.3. The transport of carriers in the nitride conduction band The electron transport in the nitride conduction band is solved with the drift–diffusion formalism than can be written as
J n ¼ qln nc E þ qDn rnc
ð3Þ
where ln is a mobility and Dn is a diffusion constant. This equation is also solved for the entire nitride region in 3D space. 2.2.4. Density gradient The electron distribution in the channel region is calculated with the density-gradient formalism with quantum potential
pffiffiffi
r ðbn r nÞ
pffiffiffi n w ¼0 2 qn
ð4Þ
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026
S. Park et al. / Solid-State Electronics xxx (2015) xxx–xxx
where ln is a mobility and Dn is a diffusion constant. In case of the high electric field at the channel, the narrow potential well is formed at the channel surface, so the quantum correction can give more accurate electron density. Hence, more accurate tunneling current can be calculated compared to classical drift diffusion formalism [24].
2.2.5. Simulation parameters The simulation parameters such as a trap position/energy, capture/emission rate and tunneling probabilities are calibrated with own experimental data [22] and agree with that of literature [13] within the same order of magnitude. The detailed descriptions about the model and the calibration with the experimental data are well presented in [22,23]. In this simulation study, an initial charge distribution for the retention simulation is extracted from the 3D simulation after programming until the threshold voltage shift reaches to 4 V. More simulation results including data in this paper can also be found in elsewhere [21,23].
3. Simulation results 3.1. Programming phase Prior to the retention simulation, the programming phase is calculated which will be used for the initial condition for the retention simulation. The electron profile when the threshold voltage shift becomes 4 V is selected for each oxide thickness as an initial condition thus the programming time before the retention simulation is different if the device and operation condition is different (such as oxide thickness and temperature). As an example of 4 nm tunneling oxide case, the electron distribution at the conduction band and trap during the programming stage are shown in Fig. 3 for each programming time from 106 s to 0.1 s. At the early stage of programming, electrons are piled up near the bottom (tunneling) oxide side. However, at later time, the electron profile shows higher concentration at the top (blocking) oxide side. This is because the direction of electron field at the programming phase as shown in Fig. 3 so the electrons are swept from the bottom oxide side to the top oxide side. It is worthwhile to mention that the
Fig. 3. Vertical electron profile during the programming stage in the trap state (a) and the conduction band (b) of the nitride layer. The tunneling oxide thickness is 4.0 nm and programming temperature is 500 K. The electron is injected from the bottom oxide side at the position of 0 nm.
3
programming characteristics in Fig. 3 are similar to that using 1D simulation reported in [12].
3.2. Retention phase We plot retention vs bake time at a temperature range of 300– 550 K for devices with various tunneling oxide thickness in Fig. 4. It is interesting to point out that the retention curves at lower temperature are dented for thin oxide cases (2.4 nm and 2.6 nm). In order to investigate effect of the dent point to the activation energy, we define the criteria for the retention time as the time for 15% charge loss (above the dent) and 20% charge loss (below the dent). The retention time vs. temperature is shown in Fig. 5(a) and (b) for both criteria, showing the different activation energy for different criterion. We define region-1, 2 and 3 according to the different slope in the Arrhenius plot. In the following subsections, we analyze the mechanisms for each region in detail.
4. Analysis on activation energy 4.1. Criterion above dent point The data retention time defined by 15% charge loss criterion vs 1=kB T is depicted in Fig. 5(a). The trend shows that the device with the oxide of 4 nm has a unique slope while thinner devices have a slope varying according to temperature. It is known that the Arrhenius plot shows unique activation energy when thermal emission is the dominant charge loss mechanism [4]. As the tunneling current becomes important for the cases of thinner oxide, the slope of the Arrhenius plots decreases in low temperature region. Thus, the different activation energy can be defined according to the different temperature regions. Region-1 in Fig. 5(a) represents a high temperature region which has the same activation energy as that of the tunneling free case (4 nm oxide). In order to identify the charge loss mechanism in this region, a transient distribution of trapped electrons in Region-1 (500 K for 2.4 nm oxide) is shown in Fig. 6(a). As shown in the figure, the thermal emission and lateral transport (Ilat ) is dominant than the tunneling charge loss and thus the data retention time is dependent on temperature in this region. In other words, Region-1 can be characterized as ‘Ilat -dominant’ region. The temperature region showing the reduced activation energy is called Region-2 in Fig. 5(a), in which the lateral charge transport and the tunneling charge loss is shown in Fig. 6(c)–(f). In this region, the direct tunneling current (Itun ), which is insensitive to temperature, becomes more dominant than the thermal emission and lateral transport. As a result, the thinner tunneling oxide causes more charge loss and reduces more data retention times. The independent characteristic of the regions on temperature is also more obvious in the thinner tunneling oxide because of the fact that the impact of the tunneling current becomes larger. Hence, Region-2 can be defined as ‘Itun -dominant’ region. The interplay of the two leakage mechanism – Ilat and Itun – according to the temperature is more clearly understood by comparing the two cases in Fig. 7: 4 nm and 2.8 nm oxide thickness. For the 4 nm oxide case, there are no tunneling current thus the trapped charge loss near the bottom oxide when the temperature is 500 K (Fig. 7(a)) is caused by Ilat only. As the temperature decreases to 300 K, Ilat is significantly reduced as can be seen in the lateral profile, Fig. 6(e). As a result, it is hard to identify the reduction of the trapped charge near the bottom oxide side in Fig. 7(e). Hence, Region-2 cannot be observed in devices with thicker oxide.
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026
4
S. Park et al. / Solid-State Electronics xxx (2015) xxx–xxx
Fig. 4. Simulated retention curves at various temperatures for 4 nm, 2.8 nm, 2.6 nm and 2.4 nm tunneling oxide devices. Two different criteria (15% and 20%) for extracting the Arrhenius plot are also indicated.
For device with 2.8 nm oxide, Itun now increase so that there are additional reduction of the trapped charge near the surface compared to that of 4.0 nm oxide (Compare the left and right figures
in Fig. 7). This additional reduction at the bottom oxide side varies a little as the temperature changes because Itun has very small activation energy. This tunneling effect on activation energy also agrees with the trend reported in [8] for the FG structure where the charge loss through an IPD layer is the dominant charge loss mechanism. Thus, the degradation of the activation energy reported in [5] can be explained by the tunneling leakage. It is worthwhile to note that, in Region-1, the retention time is smaller for the 4.0 nm case than that for the 2.8 nm case as shown in Fig. 5(a). At first glance, it may sound strange because the thicker tunneling oxide seems to give better retention characteristics. It is true if the initial electron profile before the retention phase are equivalent for the two cases. However, in our case, the initial electron profile is different because the profile is calculated when the threshold voltage shift reaches 4 V. Therefore, a total amount of the stored charge in the trap is larger for the device with 4 nm oxide. The difference in the initial charge density can be verified in Fig. 7(a) and (b). In the figure, the net amount of trapped charge between 4 nm and 8 nm (the charge accumulated near nitride/top oxide interface) for the device with 4 nm oxide is higher than that with 2.8 nm oxide. Hence, for the retention phase, the electric field is smaller for the device with 4 nm oxide as shown in Fig. 8. As a result, the electron in this region (moving left to right in Fig. 7) moves slower for the device with 4 nm oxide. Since the charge flows from left to right in Fig. 7 increases the threshold voltage shift, the device with 4 nm oxide shows lower threshold voltage and thus shows worse retention characteristics. 4.2. Criterion below the dent point
Fig. 5. Simulated Arrhenius plots of the various tunneling oxide thickness when the criterion is 15% (a) and 20% (b) charge loss. According to the criterion for the lifetime, the Arrhenius shows different characteristics.
The Arrhenius plots with the 20% charge loss criterion are depicted in Fig. 5(b). Unlike the case of the 15% charge loss criterion, the Arrhenius plots can be divided into three regions according to the slope that represents an activation energy. Here, Region-1 and Region-2 have the same meaning as stated for case of 15% criterion. Interestingly, the activation energy in Region-3 restores back to that in Region-1. Referring the tunneling current profile in Fig. 9,
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026
S. Park et al. / Solid-State Electronics xxx (2015) xxx–xxx
5
Fig. 6. Trapped electron density distributions of the 2.4 nm tunneling oxide structure along both the channel direction (left figures) and the vertical direction (right figures) at temperature 300 K, 400 K and 500 K from 105 s to 105 s.
the reason for the transition from Region-2 to Region-3 is due to a limitation of the tunneling current density. When there are no transition from Region-2 to Region-3 like the case of 2.8 nm oxide, the tunneling current continuously decreases as shown in Fig. 9(a). The decrease is due to the leakage by the lateral transport. But, in the case of 2.4 nm oxide, an abrupt change in the tunneling current can be found as shown in Fig. 9(b). This abrupt change appears at the transition time from Region-2 to Region-3 (between 102 s and 103 s). Because of the limitation of Itun ; Ilat becomes a dominant mechanism so the activation energy in Region-3 shows same one in Region-1 which is Ilat -dominant region. This abrupt change can be more clearly observed for various tunneling oxide thickness and temperature as shown in Fig. 10. In the figure, the tunneling current density at the center of the channel are plotted as the retention time and the cases for 300 K of temperature are shown with black lines while others are shown with gray lines. As the temperature increases, the tunneling current decreases faster for each oxide thickness due to the influence of Ilat , and this trend is general for all oxide thickness. However, for Itun -dominant cases, there are additional special case which shows an abrupt decrease of Itun at the temperature of 300 K. The start time of the abrupt change decreases as Itun increases, which is consistent of the appearance of Region-3. In sum, Region-3 is due to the limitation of Itun and the transition to Region-3 is accelerated for higher Itun . In order to explain the limitation of Itun , another current component should be defined called a supply current, Isup . When the trapped electron tunnels out from a nitride trap, the trap becomes
empty. Isup is a current that fills this empty trap via a lateral and vertical movement according to (2). The role of Isup for Region-3 can be explained by the electron distributions shown in Fig. 6(f). In order to retain a certain current level, the empty trap site after the tunneling should be filled by Isup . However, at the low temperatures, Isup is much smaller than Itun , thus traps becomes empty. the electrons near the interface are depleted and eventually become negligible as can be observed in Fig. 6(f). After the depletion, there are no source of electron tunneling which is n in Eq. (1) and thus Itun decreases abruptly as shown in Figs. 9 and 10. This is why there are the dent point in Fig. 4(c) and (d). Therefore, we can call Region-3 as a Isup -limited region. In this way, an additional charge loss is determined by electron transport (Isup ) only in Region-3, and the activation energy increases up to the tunneling free activation energy in Region-1. This phenomenon, which is a key finding in this study, is one of the effects caused by the electron transport at the trapping layer on the activation energy. 4.3. Summary and lifetime estimation In Table 1, we summarize the dominant current component and mechanisms for each region. For Region-1, the lateral current is a dominant loss mechanism. In Region-2, the tunneling current is a dominant loss mechanisms. In Region-3, the supply current determines the characteristics of retention by limiting the tunneling current. This limitation is due to the depletion region near the tunneling oxide surface. Note that unlike other tunneling mechanisms
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026
6
S. Park et al. / Solid-State Electronics xxx (2015) xxx–xxx
Fig. 7. Trapped electron density distributions of the 4.0 nm (left figures) and 2.8 nm (right figures) tunneling oxide structure along the vertical direction at the temperature of 300 K, 400 K and 500 K and with the retention time from 105 s to 105 s.
depletion of trapped electrons, Region-3 is not observed in Fig. 5(a). Hence, great cares are needed when estimating the lifetime projection in room temperature because of the multiple activation energies. For example, under the lifetime criterion of 20% shift, the prediction of the lifetime would be overestimated if the activation energy is extracted from the high temperature stress
Fig. 8. Electric field profile along the vertical direction of the nitride layer before the retention phase (or after programming phase with 4 V of a thereshold voltage shift. The electric field for the oxide thickness of 2.8 nm shows higher electric field than that of 4.0 nm. The direction of electric field is from the top oxide side to the bottom oxide side.
in MOSFET device such as Stress Induced Leakage Current, Itun in CT Flash memory devices has a limited source of tunneling. Therefore, if a source for the tunneling is depleted, the tunneling current is being limited. It is interesting point that the transition temperatures between regions are highly affected not only by a tunneling oxide thickness but also by the lifetime criterion as shown in Fig. 5(a) and (b). Moreover, since the 15% criterion can be satisfied before the
Fig. 9. Tunneling current profile along the lateral (channel) direction from 105 s to 105 s. The oxide thickness is 2.8 nm for (a) and 2.4 nm for (b) and the temperature is 300 K for both case.
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026
S. Park et al. / Solid-State Electronics xxx (2015) xxx–xxx
[3]
[4] [5]
[6]
[7]
[8]
[9] Fig. 10. Tunneling current density at the center of channel for all oxide thickness and temperatures. The thinner oxide gives higher tunneling current density at the early stage. The cases for 300 K are drawn with black lines and others are drawn with grey lines.
[10]
[11] Table 1 Mechanisms for each retention regions. Region
Mechanism
Description
I
Ilat dominant Itun dominant Isup limited
Lateral transport is a dominant loss mechanism
II III
[12]
[13]
Tunneling current is a dominant loss mechanism Tunneling electron should be supplied by lateral and vertical transport. Otherwise, the trapped electron near the surface would be depleted
condition. On the other hand, if the lifetime is extrapolated from Region-2, the retention time could be seriously underestimated. Therefore, for an accurate prediction of the reliability of the CT Flash memory, it is an essential prerequisite to understand the characteristics of multiple activation energy according to the lifetime criterion and device geometry.
[14]
[15]
[16]
[17]
[18]
5. Conclusion [19]
To investigate the activation energy of the CT Flash memory, the SANOS structures with various tunneling oxide thickness are simulated under a several temperatures considering the vertical and lateral charge transport. For the first time, we found that the Arrhenius plots of the simulation results are divided into three regions, resulting in the multiple activation energies. The decrease and increase of the activation energy according to the stress temperature condition can be understood with tunneling leakage and electron transport effect, respectively. Therefore, understanding of the multiple activation energy is necessary for an accurate prediction of the retention time. References [1] Lee W-S. Future memory technologies. In: International conference on solidstate and integrated-circuit technology (ICSICT); 2008. p. 1–4. [2] Jang J, Kim Hs, Choi W, Cho H, Kim J, Shim SI, Jang Y, Jeong Jh, Son Bk, Kim DW, Shim Jj, Lim, JS, Kim Kh, Yi SY, Lim Jy, Chung D, Moon Hc, Hwang S, Lee Jw, Son
[20]
[21]
[22]
[23]
[24]
7
Yh, in CU, Lee W-s. Vertical cell array using tcat (terabit cell array transistor) technology for ultra high density nand flash memory. In: VLSI Symp. Tech. Dig; 2009. p. 192–3. Tanaka H, Kido M, Yahashi K, Oomura M, Katsumata R, Kito M, Fukuzumi Y, Sato M, Nagata Y, Matsuoka Y, Iwata Y, Aochi H, Nitayama A. Bit cost scalable technology with punch and plug process for ultra high density flash memory. In: VLSI Symp. Tech. Dig; 2007. p. 14–15. Nozawa H, Kohyama S. A thermionic electron emission model for charge retention in sanos structures. Jpn J Appl Phys 1982;21(2):111. Molas G, Colonna JP, Kies R, Belhachemi D, Bocquet M, Gely M, et al. Investigation of charge-trap memories with AIN based band engineered storage layers. Solid-State Electron 2011;58:68–74. Kim J, Kang C, Chang Si, Kim J, Jeong Y, Park C, Kang Jh, Kim Sh, Hwang S, Choe Bi, Park J, Chung J, Park Y, Choi J, Chung C. New phenomena for the lifetime prediction of tanos based charge trap nand flash memory. In: Device research conference (DRC); 2010. p. 99–100. Govoreanu B, Houdt JV. On the roll-off of the activation energy plot in hightemperature flash memory retention tests and its impact on the reliability assessment. IEEE Electron Dev Lett 2008;29(2):177–9. Salvo BD, Ghibaudo G, Pananakakis G, Reimbold G, Mondond F, Guillaumot B, et al. Experimental and theoretical investigation of nonvolatile memory dataretention. IEEE Trans Electron Dev 1999;46:1518–24. Pellerin JP, Lalande F, Canet P, Bouchakour R, Jeuland F, Morancho L. Modeling charge variation during data retention of MLC flash memories. Microelectron Reliab 2009;49:1060–3. Lue HT, Wang SY, Hsiao YH, Lai EK, Yang LW, Yang T, Chen KC, Hsieh KY, Liu R, Lu CY. Reliability model of bandgap engineered sonos (be-sonos). In: Tech. Dig. Inter. Electron Dev. Meeting; 2006, p. 1 – 4. Compagnoni C, Spinelli AS, Lacaita AL. Experimental study of data retention in nitride memories by temperature and field acceleration. IEEE Electron Dev Lett 2007;28(7):628–30. Arreghini A, Akil N, Driussi F, Esseni D, Selmi L, van Duuren MJ. Long term charge retention dynamics of sonos cells. Solid-State Electron 2008;52:1460–6. Maconi A, Arreghini A, Compagnoni CM, den bosch GV, Spinelli AS, Houdt JV, et al. Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3d sonos devices. Solid-State Electron 2012;74:64–70. Shapira A, Shur Y, Diamand YS, Shappir A, Eitan B. Unified retention model for localized charge trapping nonvolatile memory device. Appl Phys Lett 2008;92:133514. Vianello E, Nowak E, Mariolle D, Chevalier N, Perniola L, Molas G, Colonna JP, Driussi F, Selmi L. Direct probing of trapped charge dynamics in sin by kelvin force microscopy. In: Int. Conf. on microelectronic test structures; 2010, p. 94– 97. Baik SJ, Lim KS, Choi W, Yoo H, Shin H. Charge diffusion in silicon nitrides: scalability assessment of nitride based flash memory. In: Int. Reliab. Phys. Symp; 2011. p. 650–5. Kang C, Choi J, Sim J, Lee C, Shin Y, Park J, Sel J, Jeon S, Park Y, Kim K. Effects of lateral charge spreading on the reliability of tanos (tan/alo/sin/oxide/si) nand flash memory. In: Int. Reliab. Phys. Symp; 2007. p. 167–9. Furn’emont A, Cacciato A, Breuil L, Rosmeulen M, Maes H, Meyer KD, et al. Physical understanding and modeling of sanos retention in programmed state. Solid State Electron 2008;52:577–83. Benvenuti A, Ghetti A, Mauri A, Liu H, Mouli C. Current status and future prospects of non-volatile memory modeling. In: Int. Conf. simulation of semiconductor processes and devices (SISPAD); 2014. p. 5–8. Lun Z, Liu S, He Y, Hou Y, Zhao K, Du G, Liu X, Wang Y. Investigation of retention behavior for 3d charge trapping nand flash memory by 2d selfconsistent simulation. In: Int. Conf. simulation of semiconductor processes and devices (SISPAD); 2014. p. 141–4. Park S, Choi S, Jeon KS, Kim HJ, Rhee SM, Yoon I, Park YJ. A 3d simulation of the lateral charge spreading effect in charge trapping nand flash memory. In: Int. Conf. simulation of semiconductor processes and devices (SISPAD); 2012. p. 376–9. Jeon KS, Choe KS, Choi S, Park SY, Park YJ. Modeling the geometric effects on programming characteristics for the tanos device by developing a 3d selfconsistent simulation. Solid-State Electron; 2013;79:117–24. Park S. Three dimensional simulation of retention characteristics of charge trap (ct) nand flash memory, Master’s thesis, Seoul Nat’l Univ., Seoul Nat’l Univ., Gwanack-gu, Seoul, Korea; 2013. Choi S, Baek C-K, Park S, Park YJ. An analysis of the field dependence of interface trap generation under negative bias temperature instability stress using wentzelkramersbrillouin with density gradient method. Japan J Appl Phys 2011;50:014302.
Please cite this article in press as: Park S et al. Self-consistent simulation on multiple activation energy of retention characteristics in charge trapping flash memory. Solid State Electron (2015), http://dx.doi.org/10.1016/j.sse.2015.05.026