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Comparison of gadolinium oxide trapping layers in flash memory applications
Vacuum 118 (2015) 74e79
Contents lists available at ScienceDirect
Vacuum journal homepage: www.elsevier.com/locate/vacuum
Comparison of gadolinium oxide trapping layers in flash memory applications Chyuan Haur Kao*, Chun Chi Chen, Chih Ju Lin Department of Electronic Engineering, Chang Gung University, 259 Wen-Hwa 1st Road, Kwei-Shan Tao-Yuan 333, Taiwan, ROC
a r t i c l e i n f o
a b s t r a c t
Article history: Received 30 July 2014 Received in revised form 2 February 2015 Accepted 27 February 2015 Available online 6 March 2015
This paper examines a high-k dielectric material used as a flash memory charge trapping layer. Specifically, the addition Ti into a Gd2O3 film trapping layer and placed under different RTA is compared with Gd2O3 samples, and the physical and electrical characterizations of different MOHOS-type memory structures are compared. Our research shows a faster program/erase speed and larger memory window resulting from the Gd2TiO5 trapping layer due to its increased charge capture density. Furthermore, a structure comprised of Al/SiO2/Gd2TiO5/SiO2/Si annealed at 900 C in O2 ambient for 30 s demonstrated superior electrical characteristics. Our research indicates that memory devices using Gd2TiO5 with postannealing treatment show promise for future flash memory applications. © 2015 Elsevier Ltd. All rights reserved.
Keywords: High k dielectric GdTixOy based memory MOHOS capacitors
1. Introduction High dielectric constant materials used as trapping layers for flash memory have been investigated for several years, and research has revealed that high-k materials such as Al2O3, La2O3, ZrO2, and HfO2 can increase programming/erase speed [1e4]. Recently, Gadolinium oxide materials such as Gd2O3 have been used as high-k charge trapping layers due to their high dielectric constant (k ~ 18), wide band gap (5.8e6.4 eV), large conduction band offset (2.21 eV), and stability at high temperature [5e9]. Nano-crystalline (NC) particles of Gd2O3 embedded in silica glass have been used as memory devices, including crystallized Gd2O3NC memory comprised of a Gd2O3 nano-dot surrounded by amorphous Gd2O3 dielectrics [10,11]. Current research shows Gd2O3 to be one of the most promising alternative metal oxides for use in flash memory applications. Van Dover [12] indicated that Ti or TiO2 film combined with lanthanide oxide dielectrics as a high-k dielectric material can achieve outstanding electrical properties in terms of a large dielectric constant, a high breakdown voltage, and a low leakage current. A trapping layer mixture of Gd2O3 and Ti can result in an increase in the dielectric constant and increase barrier height from the trapping layer to the tunneling oxide [13e16]. Pan et al. [17] also
* Corresponding author. Tel.: þ886 3 2118800x5783. E-mail address: [email protected] (C.H. Kao). http://dx.doi.org/10.1016/j.vacuum.2015.02.033 0042-207X/© 2015 Elsevier Ltd. All rights reserved.
demonstrated that a flash memory device with a high-k PrTixOy film exhibited an improved memory window and faster program/ erase speeds due to the higher charge-trapping efficiency and deeper electron trap levels. For this research, the trapping layer in a MOHOS-type structure using Ti-doped Gd2O3 was compared with that of a Gd2O3 trapping layer. The structural and electrical properties of the Ti-doped Gd2O3 (Gd2TiO5) trapping layer were investigated using X-ray Diffraction (XRD), atomic force microscopy (AFM), and capacitanceevoltage (CeV) curves. Results show that a Gd2TiO5 trapping layer annealed at 900 C had a higher window of 3.8 V in the CeV hysteresis loop, and demonstrated good endurance with superior reliability. 2. Experimental This study examines the fabrication of a MOHOS (metal-oxidehigh-k-oxide-silicon) flash memory structure on n-type silicon (100) wafers. First, a 3 nm-thick tunnel oxide was thermally grown at 850 С in a horizontal furnace system after undergoing a standard RCA (Radio Corporation of America) cleaning process. Then, an 8 nm-thick Gd2O3 film was deposited by RF (Radio Frequency) sputtering with a pure gadolinium target (99.9%) in a gas ambient
C.H. Kao et al. / Vacuum 118 (2015) 74e79
mixture of oxygen (O2) and argon (Ar). The RF sputtering process was performed with 10 mTorr at room temperature and with precursors of O2 (3 sccm) and Ar (21 sccm), and the RF sputter power was set at 150 W. Then, Ti metal film with a thickness of 4 nm was deposited on Gd2O3 by RF sputtering from a Ti target to prepare Gd2TiO5 film. For comparison purposes a pure Gd2O3 charge trapping layer with a thickness of 8 nm was deposited on tunneling oxide. The samples were then subjected to rapid thermal annealing (RTA) treatment in O2 ambient for 30 s at 800 C and 900 C, respectively. A SiO2 film with a thickness of 10 nm was deposited on the Ti metal film as a blocking oxide by PECVD (plasma enhanced chemical vapor deposition). Then, aluminum 300 nm thick was deposited by a thermal evaporator and the pattern was defined by lithography. The Al gate was then patterned by wet etching using an Al etching solution (H3PO4: H2NO3:CH3COOH:H2O ¼ 50:2:10:9). Finally, the backside Al was also deposited by a thermal evaporator to fabricate the Gd2O3 and Ti-doped (Gd2TiO5) memory structures shown in Fig. 1(a) and (b), respectively. The hysteresis memory window of high frequency CeV curves and data retention were measured using an HP-4285 LCR meter and an HP-8110 signal generator. The crystalline structure and the
75
chemical binding status of the annealing were investigated using Xray diffraction (XRD) with a grazing incidence of Cu Ka(l ¼ 1.542 Å) radiation for the crystalline property and binding status, and a diffraction angle of 2 q ranging from 30 to 60 with a grazing incidence angle at 0.5 . Further, the surface morphologies of the Gd2TiO5 sensing membranes were monitored using atomic force microscopy (AFM) by a Veeco model D5000 operated in tapping mode using an Applied Nano silicon tip with a 50 N/m spring constant. The scan rate used was 1 Hz, the scan area was 3 3 mm, and the set engagement ratio was 80%. 3. Results and discussion To study device performance and investigate the relationship between material and electrical properties, this experiment measured the CV hysteresis curves and data storage capabilities of the above Gd2O3 and Gd2TiO5 memory devices under different annealing conditions. CV hysteresis curves swept back and forth from 10 V to þ10 V, as shown in Fig. 2(a) and (b). It can be seen that that the memory windows of the Gd2TiO5 memory device are larger than those of the Gd2O3 memory device, and that the Gd2TiO5 memory device had the largest memory window (3.8 V)
Fig. 1. Process flow and memory structures of (a) Al/SiO2/Gd2O3/SiO2/Si; and (b) Al/SiO2/Gd2TiO5/SiO2/Si.
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after RTA at 900 С. This may be due to proper RTA annealing improving the material quality and enhancing the formation of well-crystallized Gd2O3 and Gd2TiO5 memory structures, thereby strengthening overall storage capability. The program/erase speed versus VFB shift values of the Gd2O3 and Gd2TiO5 memory structures annealed at 800 С and 900 С after the P/E operation shown in Fig. 3(a) and (b) were consistent with the CV hysteresis curves. The device with the higher annealing temperature of 900 С performed better, with a larger amount of positive VFB shift and negative VFB shift than the device with a lower annealing temperature of 800 С after the programming operation (Vg ¼ 13 V from 1 ms to 10 s) and the erasing operation (Vg ¼ 15 V from 1 ms to 10 s). According to FN tunneling theory, during the programming operation, hot electrons tunnel through the tunneling oxide as the triangular barrier under a high applied electric field to the Gd2TiO5 charge-trapping layer. Proper annealing can still enhance P/E speed because annealing improves the high-k layer quality and increases electron trapping by increasing the effective electric field across the tunneling oxide. In addition, adding Ti to Gd2O3 can improve program and erase speed because of an increased dielectric constant and electrical field at the same programming or erasing voltage.
Fig. 2. High frequency CeV hysteresis curves of the (a) Gd2O3 and (b) Gd2TiO5 memory structures for the as-deposited films and the films annealed at 800 C and 900 C.
Fig. 4(a) shows the Vfb shift versus retention time (charge loss rate) of the Gd2O3 and Gd2TiO5 memory structures with 800 C and 900 C annealing. The retention characteristics were measured by using the same electric field and the observed CeV curves passed through 104 s at room temperature. Fig. 4(b) shows the charge loss rate of the Gd2O3 and Gd2TiO5 memory structures measured at 25 C and 85 C. It can be been seen that charge retention of the memory structure annealed at 900 C was better than that annealed at 800 C, and the Gd2TiO5 memory structure had better retention characteristics than the Gd2O3 sample. This is likely due to the trapping layer mixture of Gd2O3 and Ti, resulting in a decrease in the band gap value and increasing the barrier height from the trapping layer to the tunneling oxide. Therefore, a wellcrystallized Gd2TiO5 charge trapping layer after proper annealing can improve high-k layer quality and increase deep-level electron trapping by increasing the effective electric field across the tunneling oxide, thus enhancing the memory window and P/E speed and retention of the device. To evaluate the crystalline structure of the films, XRD was used to analyze the as-deposited sample and the samples with annealed at 800 C, and 900 C, respectively, as shown in Fig. 5. A detailed study of the crystalline structure of the as-deposited film and the films after RTA annealing treatments was
Fig. 3. (a) Program speed of the Gd2O3 and Gd2TiO5 memory structures annealed at 800 С and 900 С. (b) Erase speed of the Gd2O3 and Gd2TiO5 memory structures annealed at 800 С and 900 С.
C.H. Kao et al. / Vacuum 118 (2015) 74e79
Fig. 4. (a) Charge loss rate of the Gd2O3 and Gd2TiO5 memory structures annealed at 800 С and 900 С under room temperature (25 С) measurement. (b) Charge loss rate of the Gd2O3 and Gd2TiO5 memory structures annealed at 900 С under 25 С and 85 С measurement.
undertaken, using a grazing incidence angle (q ¼ 0.5 ) in an XRD spectrum in the range of a diffraction angle (2q) from 32 to 60 . Fig. 5(a) presents an intense diffraction peak for Gd2O3 (440) at 2q ¼ 47.6, Gd2O3 (622) at 2q ¼ 54.7, Gd2O3 (022) ¼ 55.4 and Gd2O3 (622) ¼ 56.4 in the as-deposited sample. On the other hand, the peaks for Gd2TiO5 (341) at 2q ¼ 47.8, Gd2TiO5 (540) at 2q ¼ 54.4, Gd2O3 (022) ¼ 55.4 and Gd2O3 (622) ¼ 56.4 are shown in Fig. 5(b). It can be seen that the higher the annealing temperature was, the stronger the diffraction peak of films became, suggesting a preferential orientation of the crystallites with the formation of well-crystallized memory structures. Consequently, the peak intensity of Gd2O3 (400) at 2q ¼ 33.1 and the peak intensity of Gd2TiO5 (140) at 2q ¼ 32.9 appeared when the annealing temperature rose to 900 C. To analyze the surface texture of the film, AFM was used to examine the film grain size. Fig. 6(a)e(f) show the AFM images of the Gd2O3 and Gd2TiO5 samples as-deposited and annealed at 800 C and 900 C, respectively. Based on the image data, it is clear that surface roughness increased as the annealing temperature increased to 900 C. The increase in surface roughness was attributed to larger grain size, due to the enhancement of Gd2O3 crystallization growth under the higher annealing conditions.
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Fig. 5. XRD of the (a) Gd2O3 and (b) Gd2TiO5 films for the as-deposited sample, and the samples annealed at 800 C and 900 C.
Therefore, as the XRD peak became stronger in certain index directions, the surface became remarkably rougher. A wellcrystallized high-k structure can increase the effective electric field across the tunneling oxide, and thus enhance deep-level electron trapping. From the AFM image of the sample annealed at 900 C, a large grain size, which implies a high deep-level trap density, can be detected from a larger surface roughness [18]. This trend was consistent with the XRD data. On the other hand, the surface roughness of the Ti-doped Gd2O3 samples decreased; this can be attributed to the Gd2TiO5 film forming a better, more compact structure with a smooth surface.
4. Conclusion This study examined the fabrication of a memory device incorporating Ti-doped Gd2O3 as the charge-trapping layer. Material XRD and AFM analyses, as well as electrical measurements were performed to determine the relationship between material and electrical properties of the device under different annealing conditions. Our research indicates that the best performance and material quality occurred when the film was fabricated at an annealing temperature of 900 С. When compared with a Gd2O3 trapping layer, the Gd2TiO5 trapping layer demonstrates increased charge capture density, a faster program/erase speed, and larger memory
78
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Fig. 6. The surface roughness (AFM image) of Gd2O3 film for the (a) as-deposited and the samples annealed at (b) 800 C and (c) 900 C; and the surface roughness of Gd2TiO5 film for the (d) as-deposited and the samples annealed at (e) 800 C and (f) 900 C.
window. This type of MOHOS memory device shows great promise for future flash memory applications. References [1] Hsien Lin Yu-, et al. IEEE Electron Device Lett 2005;26:154.
[2] Pan TM, Lee JD, Shu WH, Chen TT. Appl Phys Lett 2006;89:232908. [3] You HC, Hsu TH, Ko FH, Huang JW, Yang WL, Lei TF. IEEE Electron Device Lett 2006;27:653. [4] Pan TM, Tsai FJ, Hsieh CI, Wu TW. Electrochem Solid State Lett 2007;10:G21. [5] Zhou JP, Chai CL, Yang SY, Liu ZK, Song SL, Li YL, et al. J Cryst Growth 2004;270: 21. [6] Li YL, Chen NF, Zhou JP, Song SL, Liu LF, Yin ZG, et al. J Cryst Growth 2004;265: 548.
C.H. Kao et al. / Vacuum 118 (2015) 74e79 [7] Czernohorsky M, Tetzlaff D, Bugiel E, Dargis R, Osten HJ, Gottlob HDB, et al. Semicond Sci Technol 2008;23:035010. [8] Wang JC, Lai CS, Chen YK, Lin CT, Liu CP, Huang MichaelR S, et al. Electrochem Solid State Lett 2009;12:H202. [9] Mukherjee S, Dasgupta P, Jana PK. J Phys D Appl Phys 2008;41:215004. [10] Chang YC, Lee YJ, Chiu YN, Lin TD, Wu SY, Chiu HC, et al. J Cryst Growth 2007;301:390. [11] Milanov AP, Xu K, Laha A, Bugiel E, Ranjith R, Schwendt D, et al. J Am Chem Soc 2010;132:37.
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[12] van Dover RB. Appl Phys Lett 1999;74:1967. [13] Wang YQ, Chen JH, Yoo WJ, Yeo Y-C, Kim SJ, Gupta R, et al. Appl Phys Lett 2004;84:5407. [14] Chan JP, H DS, Kim SJ, Cho BJ. IEEE Trans Electron Devices 2009;56(11):2739. [15] Starykov Oleksiy, Sakurai Kenji. Vacuum 2005;80:117. [16] Dargis R, Fissel A, Schwendt D, Bugiel E, Krügener J, Wietler T, et al. Vacuum 2010;85:523. [17] Pan TM, Yu TY, Hsieh YY. J Appl Phys 2007;102:074111. [18] Pan TM, Chen FH, Jung JS. Appl Phys Lett 2010;96:102904.
Contents lists available at ScienceDirect
Vacuum journal homepage: www.elsevier.com/locate/vacuum
Comparison of gadolinium oxide trapping layers in flash memory applications Chyuan Haur Kao*, Chun Chi Chen, Chih Ju Lin Department of Electronic Engineering, Chang Gung University, 259 Wen-Hwa 1st Road, Kwei-Shan Tao-Yuan 333, Taiwan, ROC
a r t i c l e i n f o
a b s t r a c t
Article history: Received 30 July 2014 Received in revised form 2 February 2015 Accepted 27 February 2015 Available online 6 March 2015
This paper examines a high-k dielectric material used as a flash memory charge trapping layer. Specifically, the addition Ti into a Gd2O3 film trapping layer and placed under different RTA is compared with Gd2O3 samples, and the physical and electrical characterizations of different MOHOS-type memory structures are compared. Our research shows a faster program/erase speed and larger memory window resulting from the Gd2TiO5 trapping layer due to its increased charge capture density. Furthermore, a structure comprised of Al/SiO2/Gd2TiO5/SiO2/Si annealed at 900 C in O2 ambient for 30 s demonstrated superior electrical characteristics. Our research indicates that memory devices using Gd2TiO5 with postannealing treatment show promise for future flash memory applications. © 2015 Elsevier Ltd. All rights reserved.
Keywords: High k dielectric GdTixOy based memory MOHOS capacitors
1. Introduction High dielectric constant materials used as trapping layers for flash memory have been investigated for several years, and research has revealed that high-k materials such as Al2O3, La2O3, ZrO2, and HfO2 can increase programming/erase speed [1e4]. Recently, Gadolinium oxide materials such as Gd2O3 have been used as high-k charge trapping layers due to their high dielectric constant (k ~ 18), wide band gap (5.8e6.4 eV), large conduction band offset (2.21 eV), and stability at high temperature [5e9]. Nano-crystalline (NC) particles of Gd2O3 embedded in silica glass have been used as memory devices, including crystallized Gd2O3NC memory comprised of a Gd2O3 nano-dot surrounded by amorphous Gd2O3 dielectrics [10,11]. Current research shows Gd2O3 to be one of the most promising alternative metal oxides for use in flash memory applications. Van Dover [12] indicated that Ti or TiO2 film combined with lanthanide oxide dielectrics as a high-k dielectric material can achieve outstanding electrical properties in terms of a large dielectric constant, a high breakdown voltage, and a low leakage current. A trapping layer mixture of Gd2O3 and Ti can result in an increase in the dielectric constant and increase barrier height from the trapping layer to the tunneling oxide [13e16]. Pan et al. [17] also
* Corresponding author. Tel.: þ886 3 2118800x5783. E-mail address: [email protected] (C.H. Kao). http://dx.doi.org/10.1016/j.vacuum.2015.02.033 0042-207X/© 2015 Elsevier Ltd. All rights reserved.
demonstrated that a flash memory device with a high-k PrTixOy film exhibited an improved memory window and faster program/ erase speeds due to the higher charge-trapping efficiency and deeper electron trap levels. For this research, the trapping layer in a MOHOS-type structure using Ti-doped Gd2O3 was compared with that of a Gd2O3 trapping layer. The structural and electrical properties of the Ti-doped Gd2O3 (Gd2TiO5) trapping layer were investigated using X-ray Diffraction (XRD), atomic force microscopy (AFM), and capacitanceevoltage (CeV) curves. Results show that a Gd2TiO5 trapping layer annealed at 900 C had a higher window of 3.8 V in the CeV hysteresis loop, and demonstrated good endurance with superior reliability. 2. Experimental This study examines the fabrication of a MOHOS (metal-oxidehigh-k-oxide-silicon) flash memory structure on n-type silicon (100) wafers. First, a 3 nm-thick tunnel oxide was thermally grown at 850 С in a horizontal furnace system after undergoing a standard RCA (Radio Corporation of America) cleaning process. Then, an 8 nm-thick Gd2O3 film was deposited by RF (Radio Frequency) sputtering with a pure gadolinium target (99.9%) in a gas ambient
C.H. Kao et al. / Vacuum 118 (2015) 74e79
mixture of oxygen (O2) and argon (Ar). The RF sputtering process was performed with 10 mTorr at room temperature and with precursors of O2 (3 sccm) and Ar (21 sccm), and the RF sputter power was set at 150 W. Then, Ti metal film with a thickness of 4 nm was deposited on Gd2O3 by RF sputtering from a Ti target to prepare Gd2TiO5 film. For comparison purposes a pure Gd2O3 charge trapping layer with a thickness of 8 nm was deposited on tunneling oxide. The samples were then subjected to rapid thermal annealing (RTA) treatment in O2 ambient for 30 s at 800 C and 900 C, respectively. A SiO2 film with a thickness of 10 nm was deposited on the Ti metal film as a blocking oxide by PECVD (plasma enhanced chemical vapor deposition). Then, aluminum 300 nm thick was deposited by a thermal evaporator and the pattern was defined by lithography. The Al gate was then patterned by wet etching using an Al etching solution (H3PO4: H2NO3:CH3COOH:H2O ¼ 50:2:10:9). Finally, the backside Al was also deposited by a thermal evaporator to fabricate the Gd2O3 and Ti-doped (Gd2TiO5) memory structures shown in Fig. 1(a) and (b), respectively. The hysteresis memory window of high frequency CeV curves and data retention were measured using an HP-4285 LCR meter and an HP-8110 signal generator. The crystalline structure and the
75
chemical binding status of the annealing were investigated using Xray diffraction (XRD) with a grazing incidence of Cu Ka(l ¼ 1.542 Å) radiation for the crystalline property and binding status, and a diffraction angle of 2 q ranging from 30 to 60 with a grazing incidence angle at 0.5 . Further, the surface morphologies of the Gd2TiO5 sensing membranes were monitored using atomic force microscopy (AFM) by a Veeco model D5000 operated in tapping mode using an Applied Nano silicon tip with a 50 N/m spring constant. The scan rate used was 1 Hz, the scan area was 3 3 mm, and the set engagement ratio was 80%. 3. Results and discussion To study device performance and investigate the relationship between material and electrical properties, this experiment measured the CV hysteresis curves and data storage capabilities of the above Gd2O3 and Gd2TiO5 memory devices under different annealing conditions. CV hysteresis curves swept back and forth from 10 V to þ10 V, as shown in Fig. 2(a) and (b). It can be seen that that the memory windows of the Gd2TiO5 memory device are larger than those of the Gd2O3 memory device, and that the Gd2TiO5 memory device had the largest memory window (3.8 V)
Fig. 1. Process flow and memory structures of (a) Al/SiO2/Gd2O3/SiO2/Si; and (b) Al/SiO2/Gd2TiO5/SiO2/Si.
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C.H. Kao et al. / Vacuum 118 (2015) 74e79
after RTA at 900 С. This may be due to proper RTA annealing improving the material quality and enhancing the formation of well-crystallized Gd2O3 and Gd2TiO5 memory structures, thereby strengthening overall storage capability. The program/erase speed versus VFB shift values of the Gd2O3 and Gd2TiO5 memory structures annealed at 800 С and 900 С after the P/E operation shown in Fig. 3(a) and (b) were consistent with the CV hysteresis curves. The device with the higher annealing temperature of 900 С performed better, with a larger amount of positive VFB shift and negative VFB shift than the device with a lower annealing temperature of 800 С after the programming operation (Vg ¼ 13 V from 1 ms to 10 s) and the erasing operation (Vg ¼ 15 V from 1 ms to 10 s). According to FN tunneling theory, during the programming operation, hot electrons tunnel through the tunneling oxide as the triangular barrier under a high applied electric field to the Gd2TiO5 charge-trapping layer. Proper annealing can still enhance P/E speed because annealing improves the high-k layer quality and increases electron trapping by increasing the effective electric field across the tunneling oxide. In addition, adding Ti to Gd2O3 can improve program and erase speed because of an increased dielectric constant and electrical field at the same programming or erasing voltage.
Fig. 2. High frequency CeV hysteresis curves of the (a) Gd2O3 and (b) Gd2TiO5 memory structures for the as-deposited films and the films annealed at 800 C and 900 C.
Fig. 4(a) shows the Vfb shift versus retention time (charge loss rate) of the Gd2O3 and Gd2TiO5 memory structures with 800 C and 900 C annealing. The retention characteristics were measured by using the same electric field and the observed CeV curves passed through 104 s at room temperature. Fig. 4(b) shows the charge loss rate of the Gd2O3 and Gd2TiO5 memory structures measured at 25 C and 85 C. It can be been seen that charge retention of the memory structure annealed at 900 C was better than that annealed at 800 C, and the Gd2TiO5 memory structure had better retention characteristics than the Gd2O3 sample. This is likely due to the trapping layer mixture of Gd2O3 and Ti, resulting in a decrease in the band gap value and increasing the barrier height from the trapping layer to the tunneling oxide. Therefore, a wellcrystallized Gd2TiO5 charge trapping layer after proper annealing can improve high-k layer quality and increase deep-level electron trapping by increasing the effective electric field across the tunneling oxide, thus enhancing the memory window and P/E speed and retention of the device. To evaluate the crystalline structure of the films, XRD was used to analyze the as-deposited sample and the samples with annealed at 800 C, and 900 C, respectively, as shown in Fig. 5. A detailed study of the crystalline structure of the as-deposited film and the films after RTA annealing treatments was
Fig. 3. (a) Program speed of the Gd2O3 and Gd2TiO5 memory structures annealed at 800 С and 900 С. (b) Erase speed of the Gd2O3 and Gd2TiO5 memory structures annealed at 800 С and 900 С.
C.H. Kao et al. / Vacuum 118 (2015) 74e79
Fig. 4. (a) Charge loss rate of the Gd2O3 and Gd2TiO5 memory structures annealed at 800 С and 900 С under room temperature (25 С) measurement. (b) Charge loss rate of the Gd2O3 and Gd2TiO5 memory structures annealed at 900 С under 25 С and 85 С measurement.
undertaken, using a grazing incidence angle (q ¼ 0.5 ) in an XRD spectrum in the range of a diffraction angle (2q) from 32 to 60 . Fig. 5(a) presents an intense diffraction peak for Gd2O3 (440) at 2q ¼ 47.6, Gd2O3 (622) at 2q ¼ 54.7, Gd2O3 (022) ¼ 55.4 and Gd2O3 (622) ¼ 56.4 in the as-deposited sample. On the other hand, the peaks for Gd2TiO5 (341) at 2q ¼ 47.8, Gd2TiO5 (540) at 2q ¼ 54.4, Gd2O3 (022) ¼ 55.4 and Gd2O3 (622) ¼ 56.4 are shown in Fig. 5(b). It can be seen that the higher the annealing temperature was, the stronger the diffraction peak of films became, suggesting a preferential orientation of the crystallites with the formation of well-crystallized memory structures. Consequently, the peak intensity of Gd2O3 (400) at 2q ¼ 33.1 and the peak intensity of Gd2TiO5 (140) at 2q ¼ 32.9 appeared when the annealing temperature rose to 900 C. To analyze the surface texture of the film, AFM was used to examine the film grain size. Fig. 6(a)e(f) show the AFM images of the Gd2O3 and Gd2TiO5 samples as-deposited and annealed at 800 C and 900 C, respectively. Based on the image data, it is clear that surface roughness increased as the annealing temperature increased to 900 C. The increase in surface roughness was attributed to larger grain size, due to the enhancement of Gd2O3 crystallization growth under the higher annealing conditions.
77
Fig. 5. XRD of the (a) Gd2O3 and (b) Gd2TiO5 films for the as-deposited sample, and the samples annealed at 800 C and 900 C.
Therefore, as the XRD peak became stronger in certain index directions, the surface became remarkably rougher. A wellcrystallized high-k structure can increase the effective electric field across the tunneling oxide, and thus enhance deep-level electron trapping. From the AFM image of the sample annealed at 900 C, a large grain size, which implies a high deep-level trap density, can be detected from a larger surface roughness [18]. This trend was consistent with the XRD data. On the other hand, the surface roughness of the Ti-doped Gd2O3 samples decreased; this can be attributed to the Gd2TiO5 film forming a better, more compact structure with a smooth surface.
4. Conclusion This study examined the fabrication of a memory device incorporating Ti-doped Gd2O3 as the charge-trapping layer. Material XRD and AFM analyses, as well as electrical measurements were performed to determine the relationship between material and electrical properties of the device under different annealing conditions. Our research indicates that the best performance and material quality occurred when the film was fabricated at an annealing temperature of 900 С. When compared with a Gd2O3 trapping layer, the Gd2TiO5 trapping layer demonstrates increased charge capture density, a faster program/erase speed, and larger memory
78
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Fig. 6. The surface roughness (AFM image) of Gd2O3 film for the (a) as-deposited and the samples annealed at (b) 800 C and (c) 900 C; and the surface roughness of Gd2TiO5 film for the (d) as-deposited and the samples annealed at (e) 800 C and (f) 900 C.
window. This type of MOHOS memory device shows great promise for future flash memory applications. References [1] Hsien Lin Yu-, et al. IEEE Electron Device Lett 2005;26:154.
[2] Pan TM, Lee JD, Shu WH, Chen TT. Appl Phys Lett 2006;89:232908. [3] You HC, Hsu TH, Ko FH, Huang JW, Yang WL, Lei TF. IEEE Electron Device Lett 2006;27:653. [4] Pan TM, Tsai FJ, Hsieh CI, Wu TW. Electrochem Solid State Lett 2007;10:G21. [5] Zhou JP, Chai CL, Yang SY, Liu ZK, Song SL, Li YL, et al. J Cryst Growth 2004;270: 21. [6] Li YL, Chen NF, Zhou JP, Song SL, Liu LF, Yin ZG, et al. J Cryst Growth 2004;265: 548.
C.H. Kao et al. / Vacuum 118 (2015) 74e79 [7] Czernohorsky M, Tetzlaff D, Bugiel E, Dargis R, Osten HJ, Gottlob HDB, et al. Semicond Sci Technol 2008;23:035010. [8] Wang JC, Lai CS, Chen YK, Lin CT, Liu CP, Huang MichaelR S, et al. Electrochem Solid State Lett 2009;12:H202. [9] Mukherjee S, Dasgupta P, Jana PK. J Phys D Appl Phys 2008;41:215004. [10] Chang YC, Lee YJ, Chiu YN, Lin TD, Wu SY, Chiu HC, et al. J Cryst Growth 2007;301:390. [11] Milanov AP, Xu K, Laha A, Bugiel E, Ranjith R, Schwendt D, et al. J Am Chem Soc 2010;132:37.
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