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Investigation of STI edge effect on programming disturb in localized charge trapping SONOS flash memory cells
Microelectronics Reliability 52 (2012) 1337–1341
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Investigation of STI edge effect on programming disturb in localized charge trapping SONOS flash memory cells Yue Xu a,b,⇑, Feng Yan b, ZhiGuo Li c, Fan Yang c, Jianguang Chang c, YongGang Wang c a
College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003, China College of Electronic Science and Engineering, Nanjing University, Nanjing 210093, China c Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai 201203, China b
a r t i c l e
i n f o
Article history: Received 18 October 2011 Received in revised form 27 December 2011 Accepted 15 February 2012 Available online 16 March 2012
a b s t r a c t s The impact of shallow trench isolation (STI) on non-volatile memories has become much more serious for sub-90-nm CMOS technologies. This paper uses the localized charge trapping polysilicon-oxide-nitrideoxide-silicon (SONOS) flash memory cells to investigate STI edge effect on programming disturb when the channel hot electron injection programming method is applied. The different programming disturbs between the central cells far from STI and the edge cells close to STI are experimentally presented on the array level. At the programmed state, the edge cells suffer larger decrease of threshold voltage compared to the central cells under the same drain disturb. However, both edge and central cells at the erased state have not any significant variations of threshold voltage distribution under the same disturb conditions. In addition, both edge and central cells demonstrate almost the same behaviors under gate disturb. Two-dimension process simulation results show that the edge cells suffer a higher compressive stress caused from STI corner than the central cells. The higher compressive stress increases hole mobility, which is mainly responsible for the relatively serious drain disturb in the programmed edge cells. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction Presently, non-volatile memories have been widely used in many portable electronics including USB storage drivers, flash memory cards, laptop computers, personal digital assistants (PDAs), mobile phones, etc. [1]. Shallow trench isolation (STI), as an isolation purpose, has been broadly used in non-volatile memories to isolate array-to-array, contact-to-contact, etc. However, as the aggressive downscaling of memory cell size, the impact of STI on the performances of memory cells is becoming much more severe [2,3]. Earlier works mainly studied the STI mechanical stress effect on the performances of MOSFETs. The decrease of drive current, mobility variation and threshold voltage (Vth) shift were experimentally found in theses devices close to STI and the STI stress-induced diffusivity is thought as a plausible origin responsible for these issues [4–6]. Later, Sheu et al. proposed a stress-dependent dopant diffusion model and successfully analyzed device characteristics related to STI stress [7]. Recently, a few researches also have been conducted in studying STI edge effect on the program⇑ Corresponding author at: College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003, China. Tel.: +86 25 83593965. E-mail address: [email protected] (Y. Xu). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2012.02.010
ming behaviors of polysilicon-oxide-nitride-oxide-silicon (SONOS) memory. It has been found that the edge cells adjacent to STI have a lower channel hot electron (CHE) injection programming efficiency than the central cells far from STI. Boron segregation induced by STI is thought to be the main reason for this problem [2–3]. However, STI edge effect on programming disturbs has been seldom studied in non-volatile memory cells. In addition to cycling endurance and data retention, the programming disturb is another important reliability issue in non-volatile memories [8–11]. There are two major programming disturbs, namely, drain disturb and gate disturb. Drain disturb is very serious in the NOR-type memory cells at the programmed state. It causes an obvious Vth shift in those cells that have unselected word line (WL) but share the same bit line (BL) of cells that are being programmed [9–11]. During programming, gate disturb can also cause Vth shift in those cells that have shared the same WL with the being programmed cells but unselect BL [9–11]. In this work, first of all, we have investigated the STI edge effect on CHE programming on the array level in a NOR-type localized trapping SONOS memory product. The different programming disturb behaviors are compared between edge and central cells. Next, two-dimension (2D) process simulations have been performed to analyze the mechanical stress and boron concentration variation induced by STI. Finally, we explain the experimental results with the aid of TCAD process simulations.
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2. Experimental results The measured localized trapping SONOS memory cells were fabricated in a 90 nm standard CMOS technology. The cells used in this study are illustrated in Fig. 1a. The channel length and width of the cell are 100 nm and 90 nm, respectively. The thickness of ONO layers are 4/7/12 nm (bottom oxide/nitride/top oxide). Programming of the SONOS cells is performed by using CHE injection [12]. Due to the completely symmetrical cell structure, the electrons can be trapped in the nitride layer above the source and drain junctions simultaneously, realizing two physical bits storage per cell. To read one of the two bits, reading is implemented by reversing the role of the drain and the source in contrast to programming. Erasing is performed by band-to-band tunnel-assisted hot-hole (BBHH) injection [12,13]. Fig. 1b shows the schematic diagram of the NOR-type array structure used in the tested SONOS memory. It is a high-density virtual ground array which is composed of the cross stack of BLs and WLs. Here, WLs are poly strips and BLs are buried N + diffusions. Each array contains 32 WLs and 34 BLs. Both the width and the spacing of WLs are 90 nm. Both the width and the spacing of BLs are 100 nm. Inside each array, it is contactless because there is no need for field isolation. It is noted that a
Fig. 1. (a) SONOS cell cross section along a word line. (b) The schematic diagram of the array structure in the experiments.
staggered BL contact structure is applied. STI locates in these BL contracts for isolating two adjacent arrays. The distance from edge WLs to STI corner is a key parameter, which determines the impact of STI on edge cells. It is 215 nm in the tested array. In order to statistically evaluate the different STI effects on edge and central cells, 32 pages of cells with 32 k bits per page, including 28 pages of central cells and four pages of edge cells were measured in our experiments. Before programming, the native threshold voltage (Vth) distributions of edge and central cells were firstly examined on the page level. The Vth is determined from Id–Vg measurements using constant current definition (Id = 5 lA at Vd = 1.3 V). Fig. 2 shows the tested results for one page of central cells and one page of edge cells. It can be clearly observed that the native Vth distribution of the edge cells is about 0.1 V higher than that of the central cells, suggesting STI has a significant impact on the native Vth distribution of the edge cells. Next, 32 pages of native cells were programmed to four-level storage states. When CHE programming is performed, two different positive voltages are applied to one WLi (gate) and one BLi (drain), respectively. The other corresponding BLi+1 (source) and substrate are grounded. Hence, electrons travel from the source to the drain and are accelerated by the high lateral electric field in the depletion region on the drain side. Few ‘‘lucky’’ electrons obtain high enough kinetic energy and inject into the ONO stack to implement self-aligned storage above drain junction. In order to obtain a tight Vth distribution in the multi-level cell (MLC) programming, an incremental-step pulse programming (ISPP) method is applied [3]. During the ISPP programming, the programming voltage is stepped by a constant voltage increasing after each programming pulse. In the experiments, two-stage CHE programming with ISPP approach is used. At the first stage, a fast programming rate is provided by using drain voltage stepping to reach a lower Vth than the final target. This is done to all cells on a given page simultaneously. At the second stage, an accurate programming is achieved by using gate stepping and an adjusted drain voltage. During the MLC programming courses, there are validation steps. When the readout current of the programmed cells reaches a reference level, the programming operations stop. We compared the programming conditions of two stages at the ‘‘00’’ programming state (highest Vth state) between edge and central cells, as shown in Table 1. In the first programming stage, the edge and central cells exhibit approximately the same maximum drain voltage and maximum pulse numbers. In the second programming stage, nearly the same maximum drain and gate pro-
Fig. 2. The native threshold voltage (Vth) distributions of edge and central cells on the page level.
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Table 1 Average programming conditions per page at the ‘‘00’’ state (highest Vth state). Average programming conditions
Central cells
Edge cells
Maximum Maximum Maximum Maximum Maximum
5.39 34.7 4.76 8.95 80.6
5.33 33.5 4.76 9.18 87.0
drain voltage in phase 1 (V) pulse number in phase 1 drain voltage in phase 2 (V) gate voltage in phase 2 (V) pulse number in phase 2
gramming voltages are also obtained for both central and edge cells except a little more programming pulses for edge cells. The programming conditions indicate that the programming behaviors of edge cells are not impacted by STI. In addition, the overall programming time of all cells on one page was also measured to evaluate the CHE programming behaviors of edge and central cells. The box chart of programming time of four pages of edge cells and 28 pages of central cells is shown in Fig. 3. It can be seen that the average programming time of one page of edge cells is only little longer than that of central cells. The very small difference of the average programming time between edge and central cells also demonstrates the STI edge effect do not seriously impact the programming behaviors of edge cells. Further, the gate programming disturbs for edge and central cells were measured. First, we selected one part of native cells on one WL and programmed them to the ‘‘00’’ state by using ISPP CHE programming method. After that, the other part of native cells on the same WL are programmed to the ‘‘11’’ state (erased state). During the programming, the drain terminals of unselected cells that share the same WL with the being programmed cells were grounded. At last, we tested the Vth distribution of all cells including theses unselected cells, as illustrated in Fig. 4. We found the Vth distribution of the non-programmed native cells makes more than 0.1 V upward shift under gate disturb. There might be tunneling of electrons from the substrate to the nitride storage layer in the nonprogrammed cells. Furthermore, we can observe the Vth shift is almost the same for both native edge and central cells, which shows STI edge effect does not aggravate gate disturb for edge cells. Additionally, it is noticed that the Vth distribution of edge cells is also 0.1 V higher than that of central cells at the erased state. Finally, the drain programming disturbs for edge and central cells were tested. Above all, one page of native edge cells was programmed to ‘‘11’’ and ‘‘00’’ states in turn as the programmed reference cells. Next, an additional CHE programming was performed to obtain ‘‘00’’ state for another page of native cells that share the same BL but different WL with the programmed reference cells. During the additional programming, the gate of the programmed
Fig. 4. The measured Vth distribution of one page of edge cells and one page of central cells under gate disturb.
Fig. 5. The measured Vth distribution of one page of programmed reference edge cells and one page of programmed reference central cells under drain disturb.
reference cells is grounded. The measured Vth distributions of the programmed reference cells induced by BL disturb are illustrated in Fig. 5. It can be obviously seen that the Vth distributions are decreased concurrently in the programmed reference edge and central cells at the ‘‘00’’ state. The hole injection from the drain junction may be responsible for the decrease of Vth Moreover, we notice the reduction of Vth of edge cells is larger than that of central cells. Accordingly, we infer that more holes could be generated in the drain junction and are locally injected into the nitride layer of edge cells, which means that STI edge effect aggravates the drain disturb for the programmed reference edge cells. Nevertheless, an obvious reduction of Vth cannot be found in the programmed reference edge and central cells at the ‘‘11’’ state. It indicates that both edge and central cells are not suffered from serious drain disturb at the erased state. 3. TCAD process simulation
Fig. 3. The box chart of programming time of four pages of edge cells and 28 pages of central cells.
To explain the observed experimental results, 2D process simulations were conducted to analyze the STI-induced effects by using TSUPREM4 simulator. We mainly used point defect enhancement, activation and compress models to profile dopant diffusion and
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mechanical stress distribution induced by STI in the edge cells. All process parameters in the TCAD simulations were calibrated to the 90 nm CMOS fabrication technology of the SONOS memory. The simulated contour of mechanical stress distribution from the STI corner to the cell channel center region along the BL direction is given in Fig. 6. It can be observed that the polarity of the mechanical stress in the BL direction is negative, suggesting that the channel region of edge cell suffers a compressive stress. It is well known that the mechanical stress is exerted by STI well on device active area due to the volume of STI well increasing during STI
process [5–6]. Because of the lower thermal expansion rate of the STI oxide relative to silicon, the mismatch of thermal expansion coefficient difference results in a compressive stress near the STI interface. As seen in Fig. 6, we can distinctly observe a higher compressive stress extends into active area about 300 nm. With the distance from the STI edge to the cell channel region exceeding 300 nm, no higher compressive stress can be found in the channel region of central cells. The stress simulation results show the edge cells suffer about 20% higher compressive stress than central cells. Fig. 7 shows the simulated boron doping distribution profile across the cell channel center region along the BL direction. From the contour of the active boron doping, it can be seen that boron concentration of the edge channel region in the circle is almost the same with that of the central channel region. Further, the lateral boron doping curve along BL direction more clearly displays the boron concentration of the channel center region of edge cells is only slightly higher than that of central cells. The simulation results indicate that the phenomenon of born segregation due to STI impact does not occur when the distance from STI corner to edge WL reaches 215 nm [14].
4. Discussion
Fig. 6. The simulated mechanical stress contour from the STI corner to the cell channel center region along the BL direction.
Fig. 7. The simulated boron distribution profiles across the cell channel center region along the BL direction, (a) doping contour, and (b) lateral boron doping concentration curve.
With the aid of 2D process simulations, we can reasonably interpret the experimental results. Because the larger compressive stress originates in the STI edge and spreads to the channel region of edge cell, diffusion of boron pockets in N-channel edge cell is retarded [5,7]. The doping concentration in pockets region of edge cells becomes relatively higher than that of central cells [5]. As a consequence, the Vth distribution of edge cells shows 0.1 V higher than that of central cells at the native and erased states. On the other hand, the higher compressive stress in the edge channel region reduces electron mobility and increases hole mobility for edge cells [5,6]. Thus, the moving rate of electrons in the edge channel region is reduced and the edge cells exhibits a slightly longer programming time than that of central cells. Under gate disturb, a small number of electrons could tunnel from the substrate to the nitride layer in the non-programmed native cells that share the same WL with the programmed cells. The experimental results show that there is no obvious differences of gate disturb between edge and central cells. There might be the same tunneling field in the bottom oxide due to almost the same doping level in the edge and central channel regions. Consequently, both edge and central cells exhibit the same gate disturb behaviors [8]. Compared with central cells, a relatively larger decrease of Vth in edge cells is observed under drain disturb at the ‘‘00’’ state. However, both edge and central cells have not any significant variation of Vth under the same disturb condition at the ‘‘11’’ state. The unintentional erasure of the programmed cells with an unbiased gate attributes to a low rate of hole creation in a reversely biased drain junction [11]. When BBHH erasing is performed, holes are generated by band-to-band tunneling (BTBT) in the drain region and are heated by the lateral field in drain-substrate junction. If there is a favorable vertical field, these generated holes can locally inject into the nitride storage layer above drain junction [13]. Under drain disturb, this case near drain region is similar to the situation of BTBT erasure except that the vertical fields could be significantly different. For the programmed reference cells at ‘‘00’’ state, there are more electrons locally stored in ONO stack, which may be equivalent as a negative gate bias for erasing. Although the vertical field is lower compared to the erasing electric field, the BTBT generated holes injection should be responsible for drain disturb. However, for the programmed reference cells at the ‘‘11’’ state, there is no more electrons trapped in nitride layer, so
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the vertical electric field is obviously decreased. As a result, the probability of hot holes injecting into the ONO stack is greatly reduced and the influence of drain disturb is not remarkable in both edge and central cells. For the programmed reference edge cells at the ‘‘00’’ state, there is a slightly higher lateral field in the drain junction due to a little higher boron doping level, which could slightly increase the hole generation rate in drain depletion region. However, it is important to note the higher hole mobility of edge cells due to STI compressive stress effectively increases hole tunneling current, which could be the main reason for the relatively serious drain disturb in the edge cells [13]. 5. Conclusions STI edge effect on programming disturb has been investigated on the array level in a 90 nm localized trapping SONOS memory product. We have found that the edge cells suffer the same gate disturb with the central cells. This is attributed to the same tunneling fields in the bottom oxide for edge and central cells because of almost the same doping concentration in the edge and central channel regions. However, the edge cells at the ‘‘00’’ programmed state suffer a relatively serious drain disturb than the central cells. The higher hole mobility of edge cell induced by compressive stress is mainly responsible for this issue. In contrast, both edge and central cells at the ‘‘11’’ erased state do not suffer obvious drain disturb. This is due to the fact that the lower vertical electric field in the erased cells greatly reduces the probability of hot holes injecting into the ONO stack. References [1] White MH, Adams DA, Bu J. On the go with SONOS. IEEE Circ Dev Mag 2000;16(4):22–31.
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[2] Yue X, Feng Y, DunJun C, Yi Shi, YongGang W, ZhiGuo L, et al. Improved programming efficiency through additional boron Implantation at the active area edge in 90 nm localized charge-trapping non-volatile memory. Chin Phys Lett 2010;6(27):67201–13. [3] Hang-Ting L, Tzu-Hsuan H, Szu-Yu W, Erh-Kun L, Kuang-Yeu H, Rich L, et al. Study of incremental step pulse programming (ISPP) and STI edge effect of BESONOS NAND flash. In: Proceedings of the international reliability physics symposium (IRPS). USA: Phoenix; 2008. p. 693–4. [4] Bianchi RA, Bouche G, Roux-dit-Buisson O. Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance. In: International electron devices meeting, digest of technical papers. USA: SanFranciso; 2002. p. 117–20. [5] Masafumi M, Hiroyuki O, Yukihiro K. Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics. IEEE Trans Electron Dev 2004;51(3):440–3. [6] Gallon C, Reimbold G, Ghibaudo G, Bianchi RA, Gwoziecki R, Orain S, et al. Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress. IEEE Trans Electron Dev 2004;51(8):1254–61. [7] Yi-Ming Sheu, Sheng-jier Yang, Sheng-Jier Yang, Chih-Chiang Wang, ChihSheng Chang, Li-Ping Huang, et al. Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs. IEEE Trans Electron Dev 2005;52(1):30–8. [8] Nair DR, Mahapatra S, Shukuri S, Bude JD. Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters. IEEE Trans Electron Dev 2004;51(5):701–7. [9] Wen-Jer T, Chih-Chieh Y, Nian-Kai Z, Chen-Chin L, Shih-Keng C, Tahui W, et al. Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell. IEEE Trans Electron Dev 2004;51(3):434–9. [10] Kumar PB, Sharma R, Nair PR, Nair DR, Kamohara S, Mahapatra S, Asi J. Mechanism of drain disturb in SONOS Flash EEPROMs. In: Proceedings of the international reliability physics symposium (IRPS). USA: San Jose; 2005. p. 186–90. [11] Bharath Kumar P, Ravinder S, Nair PR, Mahapatra S. Investigation of drain disturb in SONOS flash EEPROMs. IEEE Trans Electron Dev 2007;54(1):98–105. [12] Eitan B, Pavan P, Bloom I, Aloni E, Frommer A, Finzi D. NROM: a novel localized trapping, 2-bit nonvolatile memory cell. IEEE Electron Dev Lett 2000;21(11):543–5. [13] Larcher L, Pavan P, Eitan B. On the physical mechanism of NROM memory erase. IEEE Trans Electron Dev 2004;51(10):1593–9. [14] Ghetti A, Benvenuti A, Molteni G, Alberici S, Soncini V, Pavan A. Experimental and simulation study of boron segregation and diffusion during gate oxidation and spike annealing. In: International electron devices meeting, digest of technical papers. USA: SanFranciso; 2004. p. 983–6.
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Investigation of STI edge effect on programming disturb in localized charge trapping SONOS flash memory cells Yue Xu a,b,⇑, Feng Yan b, ZhiGuo Li c, Fan Yang c, Jianguang Chang c, YongGang Wang c a
College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003, China College of Electronic Science and Engineering, Nanjing University, Nanjing 210093, China c Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai 201203, China b
a r t i c l e
i n f o
Article history: Received 18 October 2011 Received in revised form 27 December 2011 Accepted 15 February 2012 Available online 16 March 2012
a b s t r a c t s The impact of shallow trench isolation (STI) on non-volatile memories has become much more serious for sub-90-nm CMOS technologies. This paper uses the localized charge trapping polysilicon-oxide-nitrideoxide-silicon (SONOS) flash memory cells to investigate STI edge effect on programming disturb when the channel hot electron injection programming method is applied. The different programming disturbs between the central cells far from STI and the edge cells close to STI are experimentally presented on the array level. At the programmed state, the edge cells suffer larger decrease of threshold voltage compared to the central cells under the same drain disturb. However, both edge and central cells at the erased state have not any significant variations of threshold voltage distribution under the same disturb conditions. In addition, both edge and central cells demonstrate almost the same behaviors under gate disturb. Two-dimension process simulation results show that the edge cells suffer a higher compressive stress caused from STI corner than the central cells. The higher compressive stress increases hole mobility, which is mainly responsible for the relatively serious drain disturb in the programmed edge cells. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction Presently, non-volatile memories have been widely used in many portable electronics including USB storage drivers, flash memory cards, laptop computers, personal digital assistants (PDAs), mobile phones, etc. [1]. Shallow trench isolation (STI), as an isolation purpose, has been broadly used in non-volatile memories to isolate array-to-array, contact-to-contact, etc. However, as the aggressive downscaling of memory cell size, the impact of STI on the performances of memory cells is becoming much more severe [2,3]. Earlier works mainly studied the STI mechanical stress effect on the performances of MOSFETs. The decrease of drive current, mobility variation and threshold voltage (Vth) shift were experimentally found in theses devices close to STI and the STI stress-induced diffusivity is thought as a plausible origin responsible for these issues [4–6]. Later, Sheu et al. proposed a stress-dependent dopant diffusion model and successfully analyzed device characteristics related to STI stress [7]. Recently, a few researches also have been conducted in studying STI edge effect on the program⇑ Corresponding author at: College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003, China. Tel.: +86 25 83593965. E-mail address: [email protected] (Y. Xu). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2012.02.010
ming behaviors of polysilicon-oxide-nitride-oxide-silicon (SONOS) memory. It has been found that the edge cells adjacent to STI have a lower channel hot electron (CHE) injection programming efficiency than the central cells far from STI. Boron segregation induced by STI is thought to be the main reason for this problem [2–3]. However, STI edge effect on programming disturbs has been seldom studied in non-volatile memory cells. In addition to cycling endurance and data retention, the programming disturb is another important reliability issue in non-volatile memories [8–11]. There are two major programming disturbs, namely, drain disturb and gate disturb. Drain disturb is very serious in the NOR-type memory cells at the programmed state. It causes an obvious Vth shift in those cells that have unselected word line (WL) but share the same bit line (BL) of cells that are being programmed [9–11]. During programming, gate disturb can also cause Vth shift in those cells that have shared the same WL with the being programmed cells but unselect BL [9–11]. In this work, first of all, we have investigated the STI edge effect on CHE programming on the array level in a NOR-type localized trapping SONOS memory product. The different programming disturb behaviors are compared between edge and central cells. Next, two-dimension (2D) process simulations have been performed to analyze the mechanical stress and boron concentration variation induced by STI. Finally, we explain the experimental results with the aid of TCAD process simulations.
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2. Experimental results The measured localized trapping SONOS memory cells were fabricated in a 90 nm standard CMOS technology. The cells used in this study are illustrated in Fig. 1a. The channel length and width of the cell are 100 nm and 90 nm, respectively. The thickness of ONO layers are 4/7/12 nm (bottom oxide/nitride/top oxide). Programming of the SONOS cells is performed by using CHE injection [12]. Due to the completely symmetrical cell structure, the electrons can be trapped in the nitride layer above the source and drain junctions simultaneously, realizing two physical bits storage per cell. To read one of the two bits, reading is implemented by reversing the role of the drain and the source in contrast to programming. Erasing is performed by band-to-band tunnel-assisted hot-hole (BBHH) injection [12,13]. Fig. 1b shows the schematic diagram of the NOR-type array structure used in the tested SONOS memory. It is a high-density virtual ground array which is composed of the cross stack of BLs and WLs. Here, WLs are poly strips and BLs are buried N + diffusions. Each array contains 32 WLs and 34 BLs. Both the width and the spacing of WLs are 90 nm. Both the width and the spacing of BLs are 100 nm. Inside each array, it is contactless because there is no need for field isolation. It is noted that a
Fig. 1. (a) SONOS cell cross section along a word line. (b) The schematic diagram of the array structure in the experiments.
staggered BL contact structure is applied. STI locates in these BL contracts for isolating two adjacent arrays. The distance from edge WLs to STI corner is a key parameter, which determines the impact of STI on edge cells. It is 215 nm in the tested array. In order to statistically evaluate the different STI effects on edge and central cells, 32 pages of cells with 32 k bits per page, including 28 pages of central cells and four pages of edge cells were measured in our experiments. Before programming, the native threshold voltage (Vth) distributions of edge and central cells were firstly examined on the page level. The Vth is determined from Id–Vg measurements using constant current definition (Id = 5 lA at Vd = 1.3 V). Fig. 2 shows the tested results for one page of central cells and one page of edge cells. It can be clearly observed that the native Vth distribution of the edge cells is about 0.1 V higher than that of the central cells, suggesting STI has a significant impact on the native Vth distribution of the edge cells. Next, 32 pages of native cells were programmed to four-level storage states. When CHE programming is performed, two different positive voltages are applied to one WLi (gate) and one BLi (drain), respectively. The other corresponding BLi+1 (source) and substrate are grounded. Hence, electrons travel from the source to the drain and are accelerated by the high lateral electric field in the depletion region on the drain side. Few ‘‘lucky’’ electrons obtain high enough kinetic energy and inject into the ONO stack to implement self-aligned storage above drain junction. In order to obtain a tight Vth distribution in the multi-level cell (MLC) programming, an incremental-step pulse programming (ISPP) method is applied [3]. During the ISPP programming, the programming voltage is stepped by a constant voltage increasing after each programming pulse. In the experiments, two-stage CHE programming with ISPP approach is used. At the first stage, a fast programming rate is provided by using drain voltage stepping to reach a lower Vth than the final target. This is done to all cells on a given page simultaneously. At the second stage, an accurate programming is achieved by using gate stepping and an adjusted drain voltage. During the MLC programming courses, there are validation steps. When the readout current of the programmed cells reaches a reference level, the programming operations stop. We compared the programming conditions of two stages at the ‘‘00’’ programming state (highest Vth state) between edge and central cells, as shown in Table 1. In the first programming stage, the edge and central cells exhibit approximately the same maximum drain voltage and maximum pulse numbers. In the second programming stage, nearly the same maximum drain and gate pro-
Fig. 2. The native threshold voltage (Vth) distributions of edge and central cells on the page level.
Y. Xu et al. / Microelectronics Reliability 52 (2012) 1337–1341
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Table 1 Average programming conditions per page at the ‘‘00’’ state (highest Vth state). Average programming conditions
Central cells
Edge cells
Maximum Maximum Maximum Maximum Maximum
5.39 34.7 4.76 8.95 80.6
5.33 33.5 4.76 9.18 87.0
drain voltage in phase 1 (V) pulse number in phase 1 drain voltage in phase 2 (V) gate voltage in phase 2 (V) pulse number in phase 2
gramming voltages are also obtained for both central and edge cells except a little more programming pulses for edge cells. The programming conditions indicate that the programming behaviors of edge cells are not impacted by STI. In addition, the overall programming time of all cells on one page was also measured to evaluate the CHE programming behaviors of edge and central cells. The box chart of programming time of four pages of edge cells and 28 pages of central cells is shown in Fig. 3. It can be seen that the average programming time of one page of edge cells is only little longer than that of central cells. The very small difference of the average programming time between edge and central cells also demonstrates the STI edge effect do not seriously impact the programming behaviors of edge cells. Further, the gate programming disturbs for edge and central cells were measured. First, we selected one part of native cells on one WL and programmed them to the ‘‘00’’ state by using ISPP CHE programming method. After that, the other part of native cells on the same WL are programmed to the ‘‘11’’ state (erased state). During the programming, the drain terminals of unselected cells that share the same WL with the being programmed cells were grounded. At last, we tested the Vth distribution of all cells including theses unselected cells, as illustrated in Fig. 4. We found the Vth distribution of the non-programmed native cells makes more than 0.1 V upward shift under gate disturb. There might be tunneling of electrons from the substrate to the nitride storage layer in the nonprogrammed cells. Furthermore, we can observe the Vth shift is almost the same for both native edge and central cells, which shows STI edge effect does not aggravate gate disturb for edge cells. Additionally, it is noticed that the Vth distribution of edge cells is also 0.1 V higher than that of central cells at the erased state. Finally, the drain programming disturbs for edge and central cells were tested. Above all, one page of native edge cells was programmed to ‘‘11’’ and ‘‘00’’ states in turn as the programmed reference cells. Next, an additional CHE programming was performed to obtain ‘‘00’’ state for another page of native cells that share the same BL but different WL with the programmed reference cells. During the additional programming, the gate of the programmed
Fig. 4. The measured Vth distribution of one page of edge cells and one page of central cells under gate disturb.
Fig. 5. The measured Vth distribution of one page of programmed reference edge cells and one page of programmed reference central cells under drain disturb.
reference cells is grounded. The measured Vth distributions of the programmed reference cells induced by BL disturb are illustrated in Fig. 5. It can be obviously seen that the Vth distributions are decreased concurrently in the programmed reference edge and central cells at the ‘‘00’’ state. The hole injection from the drain junction may be responsible for the decrease of Vth Moreover, we notice the reduction of Vth of edge cells is larger than that of central cells. Accordingly, we infer that more holes could be generated in the drain junction and are locally injected into the nitride layer of edge cells, which means that STI edge effect aggravates the drain disturb for the programmed reference edge cells. Nevertheless, an obvious reduction of Vth cannot be found in the programmed reference edge and central cells at the ‘‘11’’ state. It indicates that both edge and central cells are not suffered from serious drain disturb at the erased state. 3. TCAD process simulation
Fig. 3. The box chart of programming time of four pages of edge cells and 28 pages of central cells.
To explain the observed experimental results, 2D process simulations were conducted to analyze the STI-induced effects by using TSUPREM4 simulator. We mainly used point defect enhancement, activation and compress models to profile dopant diffusion and
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mechanical stress distribution induced by STI in the edge cells. All process parameters in the TCAD simulations were calibrated to the 90 nm CMOS fabrication technology of the SONOS memory. The simulated contour of mechanical stress distribution from the STI corner to the cell channel center region along the BL direction is given in Fig. 6. It can be observed that the polarity of the mechanical stress in the BL direction is negative, suggesting that the channel region of edge cell suffers a compressive stress. It is well known that the mechanical stress is exerted by STI well on device active area due to the volume of STI well increasing during STI
process [5–6]. Because of the lower thermal expansion rate of the STI oxide relative to silicon, the mismatch of thermal expansion coefficient difference results in a compressive stress near the STI interface. As seen in Fig. 6, we can distinctly observe a higher compressive stress extends into active area about 300 nm. With the distance from the STI edge to the cell channel region exceeding 300 nm, no higher compressive stress can be found in the channel region of central cells. The stress simulation results show the edge cells suffer about 20% higher compressive stress than central cells. Fig. 7 shows the simulated boron doping distribution profile across the cell channel center region along the BL direction. From the contour of the active boron doping, it can be seen that boron concentration of the edge channel region in the circle is almost the same with that of the central channel region. Further, the lateral boron doping curve along BL direction more clearly displays the boron concentration of the channel center region of edge cells is only slightly higher than that of central cells. The simulation results indicate that the phenomenon of born segregation due to STI impact does not occur when the distance from STI corner to edge WL reaches 215 nm [14].
4. Discussion
Fig. 6. The simulated mechanical stress contour from the STI corner to the cell channel center region along the BL direction.
Fig. 7. The simulated boron distribution profiles across the cell channel center region along the BL direction, (a) doping contour, and (b) lateral boron doping concentration curve.
With the aid of 2D process simulations, we can reasonably interpret the experimental results. Because the larger compressive stress originates in the STI edge and spreads to the channel region of edge cell, diffusion of boron pockets in N-channel edge cell is retarded [5,7]. The doping concentration in pockets region of edge cells becomes relatively higher than that of central cells [5]. As a consequence, the Vth distribution of edge cells shows 0.1 V higher than that of central cells at the native and erased states. On the other hand, the higher compressive stress in the edge channel region reduces electron mobility and increases hole mobility for edge cells [5,6]. Thus, the moving rate of electrons in the edge channel region is reduced and the edge cells exhibits a slightly longer programming time than that of central cells. Under gate disturb, a small number of electrons could tunnel from the substrate to the nitride layer in the non-programmed native cells that share the same WL with the programmed cells. The experimental results show that there is no obvious differences of gate disturb between edge and central cells. There might be the same tunneling field in the bottom oxide due to almost the same doping level in the edge and central channel regions. Consequently, both edge and central cells exhibit the same gate disturb behaviors [8]. Compared with central cells, a relatively larger decrease of Vth in edge cells is observed under drain disturb at the ‘‘00’’ state. However, both edge and central cells have not any significant variation of Vth under the same disturb condition at the ‘‘11’’ state. The unintentional erasure of the programmed cells with an unbiased gate attributes to a low rate of hole creation in a reversely biased drain junction [11]. When BBHH erasing is performed, holes are generated by band-to-band tunneling (BTBT) in the drain region and are heated by the lateral field in drain-substrate junction. If there is a favorable vertical field, these generated holes can locally inject into the nitride storage layer above drain junction [13]. Under drain disturb, this case near drain region is similar to the situation of BTBT erasure except that the vertical fields could be significantly different. For the programmed reference cells at ‘‘00’’ state, there are more electrons locally stored in ONO stack, which may be equivalent as a negative gate bias for erasing. Although the vertical field is lower compared to the erasing electric field, the BTBT generated holes injection should be responsible for drain disturb. However, for the programmed reference cells at the ‘‘11’’ state, there is no more electrons trapped in nitride layer, so
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the vertical electric field is obviously decreased. As a result, the probability of hot holes injecting into the ONO stack is greatly reduced and the influence of drain disturb is not remarkable in both edge and central cells. For the programmed reference edge cells at the ‘‘00’’ state, there is a slightly higher lateral field in the drain junction due to a little higher boron doping level, which could slightly increase the hole generation rate in drain depletion region. However, it is important to note the higher hole mobility of edge cells due to STI compressive stress effectively increases hole tunneling current, which could be the main reason for the relatively serious drain disturb in the edge cells [13]. 5. Conclusions STI edge effect on programming disturb has been investigated on the array level in a 90 nm localized trapping SONOS memory product. We have found that the edge cells suffer the same gate disturb with the central cells. This is attributed to the same tunneling fields in the bottom oxide for edge and central cells because of almost the same doping concentration in the edge and central channel regions. However, the edge cells at the ‘‘00’’ programmed state suffer a relatively serious drain disturb than the central cells. The higher hole mobility of edge cell induced by compressive stress is mainly responsible for this issue. In contrast, both edge and central cells at the ‘‘11’’ erased state do not suffer obvious drain disturb. This is due to the fact that the lower vertical electric field in the erased cells greatly reduces the probability of hot holes injecting into the ONO stack. References [1] White MH, Adams DA, Bu J. On the go with SONOS. IEEE Circ Dev Mag 2000;16(4):22–31.
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[2] Yue X, Feng Y, DunJun C, Yi Shi, YongGang W, ZhiGuo L, et al. Improved programming efficiency through additional boron Implantation at the active area edge in 90 nm localized charge-trapping non-volatile memory. Chin Phys Lett 2010;6(27):67201–13. [3] Hang-Ting L, Tzu-Hsuan H, Szu-Yu W, Erh-Kun L, Kuang-Yeu H, Rich L, et al. Study of incremental step pulse programming (ISPP) and STI edge effect of BESONOS NAND flash. In: Proceedings of the international reliability physics symposium (IRPS). USA: Phoenix; 2008. p. 693–4. [4] Bianchi RA, Bouche G, Roux-dit-Buisson O. Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance. In: International electron devices meeting, digest of technical papers. USA: SanFranciso; 2002. p. 117–20. [5] Masafumi M, Hiroyuki O, Yukihiro K. Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics. IEEE Trans Electron Dev 2004;51(3):440–3. [6] Gallon C, Reimbold G, Ghibaudo G, Bianchi RA, Gwoziecki R, Orain S, et al. Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress. IEEE Trans Electron Dev 2004;51(8):1254–61. [7] Yi-Ming Sheu, Sheng-jier Yang, Sheng-Jier Yang, Chih-Chiang Wang, ChihSheng Chang, Li-Ping Huang, et al. Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs. IEEE Trans Electron Dev 2005;52(1):30–8. [8] Nair DR, Mahapatra S, Shukuri S, Bude JD. Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters. IEEE Trans Electron Dev 2004;51(5):701–7. [9] Wen-Jer T, Chih-Chieh Y, Nian-Kai Z, Chen-Chin L, Shih-Keng C, Tahui W, et al. Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell. IEEE Trans Electron Dev 2004;51(3):434–9. [10] Kumar PB, Sharma R, Nair PR, Nair DR, Kamohara S, Mahapatra S, Asi J. Mechanism of drain disturb in SONOS Flash EEPROMs. In: Proceedings of the international reliability physics symposium (IRPS). USA: San Jose; 2005. p. 186–90. [11] Bharath Kumar P, Ravinder S, Nair PR, Mahapatra S. Investigation of drain disturb in SONOS flash EEPROMs. IEEE Trans Electron Dev 2007;54(1):98–105. [12] Eitan B, Pavan P, Bloom I, Aloni E, Frommer A, Finzi D. NROM: a novel localized trapping, 2-bit nonvolatile memory cell. IEEE Electron Dev Lett 2000;21(11):543–5. [13] Larcher L, Pavan P, Eitan B. On the physical mechanism of NROM memory erase. IEEE Trans Electron Dev 2004;51(10):1593–9. [14] Ghetti A, Benvenuti A, Molteni G, Alberici S, Soncini V, Pavan A. Experimental and simulation study of boron segregation and diffusion during gate oxidation and spike annealing. In: International electron devices meeting, digest of technical papers. USA: SanFranciso; 2004. p. 983–6.