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Investigation on the origin of the anomalous tail bits on nitrided charge trap flash memory
Microelectronics Reliability 55 (2015) 337–341
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Investigation on the origin of the anomalous tail bits on nitrided charge trap flash memory Meng Chuan Lee ⇑, Hin Yong Wong Faculty of Engineering, Multimedia University, Persiaran Multimedia, 63100 Cyberjaya, Selangor, Malaysia
a r t i c l e
i n f o
Article history: Received 13 August 2014 Received in revised form 7 October 2014 Accepted 22 October 2014 Available online 15 November 2014 Keywords: Anomalous tail bits Nitrided flash memory Reliability analysis Threshold voltage instability Trap-assisted-tunneling
a b s t r a c t In this work, the origin of the anomalous tail bits have been examined thoroughly on 43 nm nitride based charge trap flash memory devices. Tunnel oxide nitridation was implemented on the device under study to enhance its immunity to charge loss mechanism. Due to the extensive program/erase cycling, the increment in the defect density in tunnel oxide layer has generated significant tail bits that exhibited detrimental charge loss at room temperature. The findings have indicated that these tail bits are attributed to randomly distributed defects due to extensive program/erase cycling stress. Furthermore, these tail bits enhanced with longer storage duration at room temperature but deterred at high storage temperature. In this work, the anomalous tail bits were suppressed at high storage temperature. The underlying physical mechanism for these anomalous tail bits was found to be attributed to trap-assisted-tunneling mechanism that enables trapped charges from nitride storage layer to leak out along the vertical path of oxide–nitride–oxide stack of nitrided flash memory. These findings have implied that the anomalous tail bits are one of the critical reliability concerns that need to be addressed to achieve desired reliability performance. This work also demonstrated that room temperature storage test is a critical test to investigate the generation of the detrimental anomalous tail bits in reliability characterization and qualification for future nitrided flash memory. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction Since the invention of flash memory by Dr. Fujio Masuoka in 1981, flash memory is one of the key enablers to realize the modern day’s information technology (IT) products, such as smart phones and mobile computing devices. Typical flash memory devices are Floating Gate (FG) flash memory and nitride based charge trap flash (NBCTF) memory. The injected charges are stored in conductive poly silicon FG and discrete inherent trap sites of nitride layer respectively. In order to consistently push for lower average cost per bit of high density flash memory, technology scaling is implemented aggressively on flash memory devices that will miniaturize the flash memory cell’s dimensions while maintaining good data retention capability. This technology scaling method enables more memory transistors to be fitted into smaller design floor space. This will increase the storage space of flash memory to meet the growing need for larger memory space in the market. Nevertheless, there are three critical limitations that prevent further technology scaling on FG flash memory, i.e. (1) severe stress induced leakage current (SILC) triggered if the tunnel oxide ⇑ Corresponding author. E-mail address: [email protected] (M.C. Lee). http://dx.doi.org/10.1016/j.microrel.2014.10.013 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
layer is scaled to less than 8 nm; (2) gate coupling ratio of minimum 0.6 has to be met in order for control gate of FG flash memory to properly exert control to FG and the channel; (3) severe cellto-cell interference [1–8]. As compared to FG flash memory, NBCTF memory enables better downscaling of the tunnel oxide layer while still preserving overall good data retention performance. However, the downscaling of tunnel oxide layer of NBCTF memory has to be complemented with innovative approaches to continue the technology scaling trend for NBCTF memory [3,4]. Tunnel oxide nitridation (TON) is one of the approaches applied together with the downscaling of tunnel oxide layer in order to enhance the immunity of NBCTF memory to Fowler–Nordheim (FN) stress induced damages in tunnel oxide layer. By implementing various wet or dry nitridation processes, TON is done by incorporating nitrogen content into the tunnel oxide layer to achieve larger memory window and better hardening towards the damages due to extensive program/erase P/E) cycling stress through FN injection [1–10]. Nevertheless, TON was also found to result in several critical reliability issues such as Fermi-level defects and mid-gap defects. These defects would then lead to random telegraph noise and quick electron de-trapping respectively [4,9–11]. In our previous work, TON was found to modulate dominant charge loss (CL) mechanism from high temperature charge loss (HTCL) that
M.C. Lee, H.Y. Wong / Microelectronics Reliability 55 (2015) 337–341
resulted in uniform threshold voltage (Vt) distribution shift to room temperature charge loss (RTCL) as a result of the generation of severe anomalous tail bits [9]. In this work, the origin of the anomalous tail bits is examined and studied. Moreover, the dependency of the anomalous tail bits to storage temperatures is investigated on nitrided NBCTF memory. Furthermore, the effect of P/E stress to the anomalous tail bits is also thoroughly investigated by performing systematic experiments on nitrided NBCTF memory. Based on the experimental findings, the origin and the underlying physical mechanism of these anomalous tail bits on nitrided NBCTF memory are deliberated in this work. 2. Experimental As shown in Fig. 1, the devices under study were 43 nm NBCTF memory devices that consists of poly silicon gate, top silicon oxide layer, silicon nitride layer, tunnel silicon oxide layer and silicon substrate. The layers between the poly silicon gate and substrate form the oxide–nitride–oxide (ONO) stack of the NBCTF memory cell. The physical thicknesses for each layer of the ONO stack were 8, 7, 5.5 nm. The silicon nitride layer acts as the designated charge trap layer which is sandwiched between the top silicon oxide layer and tunnel silicon oxide layer. The intrinsic defects in silicon nitride layer which surrounded by oxide layers inherently trap injected charges during P/E operations [1–4]. The top and tunnel silicon oxide layers provide sufficient protection to prevent charge leakage due to direct tunneling of charges from silicon nitride layer. Nitridation was performed on tunnel oxide layer by annealing the grown tunnel oxide layer in nitric oxide ambient thereby incorporating the nitrogen content into the tunnel oxide layer. The memory density of the device used in this study is 0.5 million bits per block and total 100 blocks were used. Program and erase operations of this device were performed by implementing FN tunneling mechanism to inject electrons and holes into the silicon nitride layer until the memory cell’s Vt reached the target Vt level. Vt measurements were taken on all memory devices used in this study before P/E cycling. A set of functional memory devices were cycled repeatedly by programming zeros pattern and erasing them to uniformly induce damages onto the tested memory devices. In this work, a total of 8000 P/E cycle counts were implemented on a set of nitrided NBCTF memory devices to investigate the effect of P/E cycle count to the CL mechanism. The P/E cycling was performed at room temperature, i.e. 25 °C in order to avoid the recovery of P/E cycling induced damages if P/E cycling was performed at higher cycling temperature. Another set of functional memory devices were not cycled. After the completion of P/E cycling, Vt data was collected on all memory cells from both sets of memory devices. Subsequently, both sets of the memory devices were stored at 25, 55, 90, 125, and 175 °C. At each read point, i.e. time 0, 0.1, 1, 24, 100 and 500 h, Vt per bit measurements were collected on both sets of the memory devices. To further investigate the origin of tail bits, all devices were erased and programmed for one time. Vt per bit was then measured for 100 P/E cycled blocks on all devices. Once it is completed, both set of devices were annealed for 24 h before
Vt per bit data was measured again. The sequence of erase/program and Vt measurement before and after 24 h at room temperature was repeated for 6 times to count the number of tail bits repeated in each sequence. 3. Results and discussions To track the growth of the anomalous tail bits, Vt per bit measurements collected at all read points were used to calculate the Vt shift by subtracting the Vt per bit at each read point with the Vt of the same bit (the bit is identified by its physical location) at time 0 h which is before bake. In this work, the bits that have Vt shift of more than or equal to 0.2 A.U. are categorized as anomalous tail bits. This is because the resolution of Vt measurement used in this study is 0.025 A.U. per step. The Vt measurement range used in this work is 0 A.U. to 4.5 A.U. Vt fluctuation is 8 times of the resolution. Therefore, a bit that exhibits 0.2 A.U. fluctuations is considered as a tail bit with anomalously large Vt fluctuation as compared to the rest of the bits. Based on Vt per bit measurements collected at every read point throughout this work, anomalous tail bits were observed to perturbed from Vt distribution at room temperature as compared to high storage temperature. Fig. 2 shows the generation of anomalous tail bits is enhanced for lower storage temperature and peaked at room temperature, i.e. 25 °C. This clearly depicts that the generation of the anomalous tail bits favoured room temperature and enhanced with longer storage durations. Fig. 3(a) and (b) show the Vt distribution plotted for P/E cycled blocks stored at 25 °C and 175 °C. As shown in Fig. 3(a), significant number of tail bits was observed to be generated and enhanced at the low end of the distribution of programmed bits when the devices are stored at 25 °C. By comparing the Vt distributions shown in Fig. 3(a) and (b), the entire Vt distribution of programmed bits does not shift significantly as storage duration increases at 25 °C. Furthermore, the number of tail bits was observed to gradually increase as storage duration prolongs at 25 °C. This observation indicates that the underlying CL mechanism impacts only on a small portion of the programmed bits at 25 °C. On the contrary, the entire Vt distribution of programmed bits was observed to be shifted significantly to lower Vt level when the storage duration at 175 °C prolongs as shown in Fig. 3(b). Furthermore, as shown in Fig. 3(b), the generation of tail bits is not observed at 175 °C but uniform Vt distribution shift is observed on nitrided NBCTF memory. This observation indicates that the CL mechanism at 175 °C impacts all programmed bits. By comparing Fig. 3(a) and (b), the observations on the CL behaviour exhibited by the distinct Vt distribution shift implies the underlying physical mechanism attributed to the CL mechanism observed at 25 °C is different than at 175 °C. Fig. 4 shows the trend of average tail bits as a function of storage durations at room temperature and high storage temperature, i.e. 175 °C. The average tail bits per block was calculated by
Average Tail Bits Count
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Average Tail Bits Count for various storage temperatures
3.0
25 55
2.0
90
1.0
125
0.0
175 0.1
1
10
100
1000
Storage Duraon (hours) Fig. 1. Typical cell structure of nanoscale nitrided NBCTF memory with single bit per cell architecture.
Fig. 2. Average tail bits count per 100 P/E cycled blocks is plotted as a function of various storage temperatures.
M.C. Lee, H.Y. Wong / Microelectronics Reliability 55 (2015) 337–341
Fig. 3. Vt distributions of P/E cycled block annealed at 25 °C and 175 °C.
Average Tail Bits per Block vs. Storage Duraon Average Tail Bits per Block
1.E+01 1.E+00
P/E Cycled Devices
Storage Temperatures 25C
1.E-01 1.E-02
175C
No P/E Cycled Devices
25C
1.E-03
175C 1.E-04 1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
Storage Duraon (Hours)
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that stored at 175 °C. Therefore, this result infers that the underlying CL mechanism that induced tail bits is strongly dependent on the defects density in tunnel oxide layer. Thus, this finding further implies that the underlying CL mechanism is found to be most effective at room temperature storage. A lower average tail bit per block for P/E cycled devices stored at 175 °C is observed as compared to room temperature storage. This is found to be attributed to the annealing of P/E cycling induced defects in tunnel oxide layer due to high temperature storage. Thus, at high temperature storage, the defects density of nitrided tunnel oxide layer reduces and as a result, the generation of the anomalous tail bits deterred [9]. This finding is in good agreement with the result reported on FG flash memory that high temperature storage evidently heals the P/E cycling induced damages which induces lesser Vt shift [12]. In Fig. 5, the time to failure of Vt shift is plotted against the inverse of storage temperature in Kelvin to derive the activation energy (Ea) of the underlying CL mechanism. The time to failure is defined as the time to achieve Vt shift of 0.2 A.U. The Arrhenius plot in Fig. 5 clearly indicates two underlying physical mechanisms that dominate the charge loss behaviour for nitrided NBCTF memory at higher storage temperatures (i.e. 90 °C and above) and lower storage temperatures (i.e. room temperature and 55 °C). This finding corroborates to the observation made on Fig. 3 earlier whereby two distinct Vt shift behaviour is observed at 25 °C and 175 °C. As shown in Fig. 5, for higher storage temperature, i.e. 90 °C and above, the time to failure data points are fitted well and activation energy, Ea of 1.1456 eV is obtained. This value corroborates well with the typical Ea for NBCTF memory [1–3]. However, as shown in Fig. 5, for lower storage temperatures, e.g. room temperature and 55 °C, the data points do not fit well with the rest of storage temperatures on the Arrhenius plot. This implies that the underlying CL mechanism that dominates at lower storage temperatures is significantly different than the mechanism that dominates at higher storage temperatures, i.e. 90 °C and above. The origin of the anomalous tail bits is further investigated with the repeatability experiment. In this repeatability experiment, for a total of 6 iterations, erase, program and Vt per bit measurement was performed before and after 24 h of room temperature storage. If the origin of the anomalous tail bits is due to fabrication process related issues, then there should be consistent repetitions of the same populations of anomalous tail bits that would be captured at each iteration of erase/program/storage for 24 h at room temperature. However, if the origin of these tail bits is due to the stochastic defects induced by P/E cycling, there should be low repetition of the same tail bits for each repetition of erase/program/storage for 24 h at room temperature. As shown in Fig. 6, the percentage of repetitive tail bits is computed by counting the cumulative number of repetitive tail bits for each iteration of erase/program/storage for 24 h at room tempera-
Fig. 4. Average tail bits per block was plotted as a function of various storage duration at bake temperatures of 25 °C and 175 °C.
dividing the total number of tail bits (that exhibits greater than or equal to 0.2 A.U. of Vt shift) with total number of blocks tested which is 100. Thus, as shown in Fig. 4, the average tail bits per block for P/E cycled devices is approximately 2 orders higher than the average tail bits per block for no P/E cycled devices. This indicates the defects density induced by the extensive repeated cycles charge injections in P/E cycling intensifies the underlying CL mechanism of nitrided NBCTF memory. With the implementation of FN tunneling as charge injection mechanism, extensive P/E cycling will typically result in defects such as bulk oxide traps and charge trapping (CT) interface states [1–4]. As shown in Fig. 4, it is found that the average tail bits per block for P/E cycled devices stored at 25 °C is about 5 times higher as compared to the P/E cycled devices
Fig. 5. Arrhenius plot for tail bits exhibits that the charge loss mechanism for storage temperature 25 °C and 55 °C is different than the charge loss mechanism for higher storage temperatures (i.e. 90 °C and above).
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Percentage of repeve tail bits
Percentage of repeve tail bits across 6 repeons of Vt per bit measurements at 25 oC 100% 80% 60% 40% 20% 0% 1
2
3
4
5
6
Number of Iteraons Fig. 6. Percentage of repetitive tail bits across 6 iterations of erase, program and Vt per bit measurements at room temperature.
ture with respect to the physical locations of the tail bits in the memory array based on Vt per bit measurements. The purpose of this evaluation is to investigate whether the tail bits are caused by the stochastic defects generated by P/E cycling or process defects that may caused by TON process. If the tail bits are caused by process defects, there may be significant number of repetitive tail bits. On the other hand, if the tail bits are caused by stochastic defects attributed to the P/E cycling, the repetitive tail bits are relatively low after each iteration of erase/program/storage for 24 h at room temperature. Fig. 6 shows the percentage of repetitive tail bits has reduced significantly after the 1st iteration till the 6th iteration. Therefore, it can be inferred that the origin of these anomalous tail bits is attributed to the stochastic defects generated by P/E cycling stress that reshuffles the Vt level after each iteration of erase/program/storage for 24 h at room temperature. Based on these experimental findings obtained in this work, trap-assisted-tunneling (TAT) mechanism is found to be the dominant CL mechanism attributed to the origin of the generation of the anomalous tail bits on nitrided NBCTF memory [1–4,9,12]. As shown in Fig. 7, TAT mechanism enables the trapped charges in nitride storage layer to tunnel through the stochastic defects generated by extensive P/E cycling on nitrided tunnel oxide layer and leak out to substrate. This charge leakage mechanism dominates at room temperature since P/E cycling induced defects will anneal and heal at high storage temperature. Thus as shown in Fig. 2, the healing effect on P/E cycling induced defects will significantly reduce the number of anomalous tail bits at high storage temperature. Furthermore by comparing the Vt distribution shifts shown in Fig. 3(a) and (b), the CL mechanism that dominates at high temperature storage is clearly different as compare to the one that dominates at room temperature storage. This is because significant number of tail bits was observed to be generated and increased over the storage duration at 25 °C storage in Fig. 3(a). On the other hand in Fig. 3(b), uniform Vt distribution shift was observed to gradually increase over the storage duration at 175 °C but there is no tail bits observed at the lower end of the Vt distribution. Thus based on Figs. 2 and 3, these observations have implied that there are different CL mechanisms that dominate at room temperature storage and high temperature storage. In order to further validate this key finding, an Arrhenius plot was made as shown in Fig. 5 to understand the relationship between the time to failure and storage temperatures. Based on Fig. 5, the time to failure (i.e. time to achieve 0.2 A.U. as previously defined) data points were observed to relatively fit well for storage temperatures at 90, 125, 175 °C, but not for storage temperatures at 25, 55 °C. Furthermore, based on the time to failure data points at 90, 125, 175 °C. Therefore based on Fig. 5, this finding has led us to conclude that the CL mechanism that dominates at high temperature storage is different than the one that dominates at room temperature storage. Furthermore, the CL mechanism that dominates
Fig. 7. Simplified schematic diagram that elucidates the TAT mechanism that leaks the trapped charges in nitride storage layer through P/E cycling induced defects and out to substrate.
at high temperature storage is thermally enhanced with the derived Ea of 1.1456 eV [1–3] which is different than the CL mechanism that dominates at room temperature storage. As shown in Fig. 4, by comparing P/E cycled devices and non P/E cycled devices, extensive P/E cycling stress resulted in the increment of the stochastic defects in nitrided tunnel oxide layer that will significantly increase the probability of trapped charges leaked out through TAT mechanism. Fig. 6 clearly indicates the stochastic nature of the defects induced by P/E cycling stress is the origin of the anomalous tail bits. Moreover as shown in Fig. 6, the contribution of the fabrication related issues to the generation of anomalous tail bits is ruled out since the number of repetitive tail bits across all 6 repetitions is relatively small. Therefore, based on all these findings, the origin of the anomalous tail bits observed on nitrided NBCTF memory is attributed to the charge leakage of trapped charges from nitride storage layer to substrate through TAT mechanism of P/E cycling induced stochastic defects. Despite the key advantages that TON offers, the generation of the anomalous tail bits is genuine reliability concern for nitrided NBCTF memory that requires further optimization in nitridation process and nitrogen distribution profile in the nitrided tunnel oxide layer to achieve the desired reliability performance. Furthermore, in addition to typical high temperature storage test in flash memory qualification process, this work has demonstrated that room temperature storage data retention test can be applied to assess the Vt instability of nitrided NBCTF memory. The room temperature storage test is crucial to investigate the generation of anomalous tail bits since high temperature storage may have masked out the true reliability performance of nitrided NBCTF memory that may have degraded by the anomalous tail bits which dominates at room temperature.
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4. Conclusion
Acknowledgements
In this work, the electrical properties of the anomalous tail bits on 43 nm nitrided NBCTF memory were investigated. The results showed the anomalous tail bits enhances with longer storage durations and dominates at room temperature. Furthermore, the generation of the anomalous tail bits was suppressed at higher storage temperatures due to the annealing of defects that is responsible for TAT mechanism in nitrided tunnel oxide layer. The origin of the anomalous tail bits was found to be attributed to the stochastic defects induced by extensive P/E cycling stress on nitrided NBCTF. TAT mechanism was found to be attributed to the charge leakage mechanism that leads to the generation of the anomalous tail bits. These findings implied that room temperature storage test is a crucial reliability test to assess the reliability performance of nitrided flash memory devices due to the detrimental anomalous tail bits. For future nanoscale nitrided NBCTF memory devices, these findings have implied that the anomalous tail bits are one of the critical reliability concerns that need to be properly assessed in reliability characterization and qualification of nitrided flash memory devices.
The authors would like to recognize all critical research work done by all researchers on non-volatile memory devices. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
Lee MC, Wong HY. IEEE Trans Electron Devices 2013;60(10):3256–64. Lee MC, Wong HY. J Nanosci Nanotechnol 2014;14(7):4799–812. Lee MC, Wong HY. J Nanosci Nanotechnol 2014;14(2):1508–20. Lee MC, Wong HY. J Nanomater 2013;2013. Article ID 195325, 17p. Lu CY, Hsieh KY, Liu R. Microelectron Eng 2009;86(3):283–6. Ielmini D. Microelectron Eng 2009;86(7):1870–5. Ielmini D, Spinelli AS, Lacaita AL. Microelectron Eng 2005;80:321–8. Kim K. In: Proceedings of the European solid-state device research conference (ESSDERC), 2012. p. 1–6. Lee MC, Wong HY, Lee L. Solid State Electron 2014;99:78–83. Kim T, He D, Morinville K, Sarpatwari K, Millemon B, Goda A, et al. IEEE Electron Device Lett 2011;32(8):999–1001. Kim T, Koka S, Surthi S, Zhuang K. IEEE Electron Device Lett 2013; 34(3):405–7. Belgal HP, Righos N, Kalastirsky I, Peterson JJ, Shiner R, Mielke N. In IEEE international reliability physics symposium, 2002. p. 7–20.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Investigation on the origin of the anomalous tail bits on nitrided charge trap flash memory Meng Chuan Lee ⇑, Hin Yong Wong Faculty of Engineering, Multimedia University, Persiaran Multimedia, 63100 Cyberjaya, Selangor, Malaysia
a r t i c l e
i n f o
Article history: Received 13 August 2014 Received in revised form 7 October 2014 Accepted 22 October 2014 Available online 15 November 2014 Keywords: Anomalous tail bits Nitrided flash memory Reliability analysis Threshold voltage instability Trap-assisted-tunneling
a b s t r a c t In this work, the origin of the anomalous tail bits have been examined thoroughly on 43 nm nitride based charge trap flash memory devices. Tunnel oxide nitridation was implemented on the device under study to enhance its immunity to charge loss mechanism. Due to the extensive program/erase cycling, the increment in the defect density in tunnel oxide layer has generated significant tail bits that exhibited detrimental charge loss at room temperature. The findings have indicated that these tail bits are attributed to randomly distributed defects due to extensive program/erase cycling stress. Furthermore, these tail bits enhanced with longer storage duration at room temperature but deterred at high storage temperature. In this work, the anomalous tail bits were suppressed at high storage temperature. The underlying physical mechanism for these anomalous tail bits was found to be attributed to trap-assisted-tunneling mechanism that enables trapped charges from nitride storage layer to leak out along the vertical path of oxide–nitride–oxide stack of nitrided flash memory. These findings have implied that the anomalous tail bits are one of the critical reliability concerns that need to be addressed to achieve desired reliability performance. This work also demonstrated that room temperature storage test is a critical test to investigate the generation of the detrimental anomalous tail bits in reliability characterization and qualification for future nitrided flash memory. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction Since the invention of flash memory by Dr. Fujio Masuoka in 1981, flash memory is one of the key enablers to realize the modern day’s information technology (IT) products, such as smart phones and mobile computing devices. Typical flash memory devices are Floating Gate (FG) flash memory and nitride based charge trap flash (NBCTF) memory. The injected charges are stored in conductive poly silicon FG and discrete inherent trap sites of nitride layer respectively. In order to consistently push for lower average cost per bit of high density flash memory, technology scaling is implemented aggressively on flash memory devices that will miniaturize the flash memory cell’s dimensions while maintaining good data retention capability. This technology scaling method enables more memory transistors to be fitted into smaller design floor space. This will increase the storage space of flash memory to meet the growing need for larger memory space in the market. Nevertheless, there are three critical limitations that prevent further technology scaling on FG flash memory, i.e. (1) severe stress induced leakage current (SILC) triggered if the tunnel oxide ⇑ Corresponding author. E-mail address: [email protected] (M.C. Lee). http://dx.doi.org/10.1016/j.microrel.2014.10.013 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
layer is scaled to less than 8 nm; (2) gate coupling ratio of minimum 0.6 has to be met in order for control gate of FG flash memory to properly exert control to FG and the channel; (3) severe cellto-cell interference [1–8]. As compared to FG flash memory, NBCTF memory enables better downscaling of the tunnel oxide layer while still preserving overall good data retention performance. However, the downscaling of tunnel oxide layer of NBCTF memory has to be complemented with innovative approaches to continue the technology scaling trend for NBCTF memory [3,4]. Tunnel oxide nitridation (TON) is one of the approaches applied together with the downscaling of tunnel oxide layer in order to enhance the immunity of NBCTF memory to Fowler–Nordheim (FN) stress induced damages in tunnel oxide layer. By implementing various wet or dry nitridation processes, TON is done by incorporating nitrogen content into the tunnel oxide layer to achieve larger memory window and better hardening towards the damages due to extensive program/erase P/E) cycling stress through FN injection [1–10]. Nevertheless, TON was also found to result in several critical reliability issues such as Fermi-level defects and mid-gap defects. These defects would then lead to random telegraph noise and quick electron de-trapping respectively [4,9–11]. In our previous work, TON was found to modulate dominant charge loss (CL) mechanism from high temperature charge loss (HTCL) that
M.C. Lee, H.Y. Wong / Microelectronics Reliability 55 (2015) 337–341
resulted in uniform threshold voltage (Vt) distribution shift to room temperature charge loss (RTCL) as a result of the generation of severe anomalous tail bits [9]. In this work, the origin of the anomalous tail bits is examined and studied. Moreover, the dependency of the anomalous tail bits to storage temperatures is investigated on nitrided NBCTF memory. Furthermore, the effect of P/E stress to the anomalous tail bits is also thoroughly investigated by performing systematic experiments on nitrided NBCTF memory. Based on the experimental findings, the origin and the underlying physical mechanism of these anomalous tail bits on nitrided NBCTF memory are deliberated in this work. 2. Experimental As shown in Fig. 1, the devices under study were 43 nm NBCTF memory devices that consists of poly silicon gate, top silicon oxide layer, silicon nitride layer, tunnel silicon oxide layer and silicon substrate. The layers between the poly silicon gate and substrate form the oxide–nitride–oxide (ONO) stack of the NBCTF memory cell. The physical thicknesses for each layer of the ONO stack were 8, 7, 5.5 nm. The silicon nitride layer acts as the designated charge trap layer which is sandwiched between the top silicon oxide layer and tunnel silicon oxide layer. The intrinsic defects in silicon nitride layer which surrounded by oxide layers inherently trap injected charges during P/E operations [1–4]. The top and tunnel silicon oxide layers provide sufficient protection to prevent charge leakage due to direct tunneling of charges from silicon nitride layer. Nitridation was performed on tunnel oxide layer by annealing the grown tunnel oxide layer in nitric oxide ambient thereby incorporating the nitrogen content into the tunnel oxide layer. The memory density of the device used in this study is 0.5 million bits per block and total 100 blocks were used. Program and erase operations of this device were performed by implementing FN tunneling mechanism to inject electrons and holes into the silicon nitride layer until the memory cell’s Vt reached the target Vt level. Vt measurements were taken on all memory devices used in this study before P/E cycling. A set of functional memory devices were cycled repeatedly by programming zeros pattern and erasing them to uniformly induce damages onto the tested memory devices. In this work, a total of 8000 P/E cycle counts were implemented on a set of nitrided NBCTF memory devices to investigate the effect of P/E cycle count to the CL mechanism. The P/E cycling was performed at room temperature, i.e. 25 °C in order to avoid the recovery of P/E cycling induced damages if P/E cycling was performed at higher cycling temperature. Another set of functional memory devices were not cycled. After the completion of P/E cycling, Vt data was collected on all memory cells from both sets of memory devices. Subsequently, both sets of the memory devices were stored at 25, 55, 90, 125, and 175 °C. At each read point, i.e. time 0, 0.1, 1, 24, 100 and 500 h, Vt per bit measurements were collected on both sets of the memory devices. To further investigate the origin of tail bits, all devices were erased and programmed for one time. Vt per bit was then measured for 100 P/E cycled blocks on all devices. Once it is completed, both set of devices were annealed for 24 h before
Vt per bit data was measured again. The sequence of erase/program and Vt measurement before and after 24 h at room temperature was repeated for 6 times to count the number of tail bits repeated in each sequence. 3. Results and discussions To track the growth of the anomalous tail bits, Vt per bit measurements collected at all read points were used to calculate the Vt shift by subtracting the Vt per bit at each read point with the Vt of the same bit (the bit is identified by its physical location) at time 0 h which is before bake. In this work, the bits that have Vt shift of more than or equal to 0.2 A.U. are categorized as anomalous tail bits. This is because the resolution of Vt measurement used in this study is 0.025 A.U. per step. The Vt measurement range used in this work is 0 A.U. to 4.5 A.U. Vt fluctuation is 8 times of the resolution. Therefore, a bit that exhibits 0.2 A.U. fluctuations is considered as a tail bit with anomalously large Vt fluctuation as compared to the rest of the bits. Based on Vt per bit measurements collected at every read point throughout this work, anomalous tail bits were observed to perturbed from Vt distribution at room temperature as compared to high storage temperature. Fig. 2 shows the generation of anomalous tail bits is enhanced for lower storage temperature and peaked at room temperature, i.e. 25 °C. This clearly depicts that the generation of the anomalous tail bits favoured room temperature and enhanced with longer storage durations. Fig. 3(a) and (b) show the Vt distribution plotted for P/E cycled blocks stored at 25 °C and 175 °C. As shown in Fig. 3(a), significant number of tail bits was observed to be generated and enhanced at the low end of the distribution of programmed bits when the devices are stored at 25 °C. By comparing the Vt distributions shown in Fig. 3(a) and (b), the entire Vt distribution of programmed bits does not shift significantly as storage duration increases at 25 °C. Furthermore, the number of tail bits was observed to gradually increase as storage duration prolongs at 25 °C. This observation indicates that the underlying CL mechanism impacts only on a small portion of the programmed bits at 25 °C. On the contrary, the entire Vt distribution of programmed bits was observed to be shifted significantly to lower Vt level when the storage duration at 175 °C prolongs as shown in Fig. 3(b). Furthermore, as shown in Fig. 3(b), the generation of tail bits is not observed at 175 °C but uniform Vt distribution shift is observed on nitrided NBCTF memory. This observation indicates that the CL mechanism at 175 °C impacts all programmed bits. By comparing Fig. 3(a) and (b), the observations on the CL behaviour exhibited by the distinct Vt distribution shift implies the underlying physical mechanism attributed to the CL mechanism observed at 25 °C is different than at 175 °C. Fig. 4 shows the trend of average tail bits as a function of storage durations at room temperature and high storage temperature, i.e. 175 °C. The average tail bits per block was calculated by
Average Tail Bits Count
338
Average Tail Bits Count for various storage temperatures
3.0
25 55
2.0
90
1.0
125
0.0
175 0.1
1
10
100
1000
Storage Duraon (hours) Fig. 1. Typical cell structure of nanoscale nitrided NBCTF memory with single bit per cell architecture.
Fig. 2. Average tail bits count per 100 P/E cycled blocks is plotted as a function of various storage temperatures.
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Fig. 3. Vt distributions of P/E cycled block annealed at 25 °C and 175 °C.
Average Tail Bits per Block vs. Storage Duraon Average Tail Bits per Block
1.E+01 1.E+00
P/E Cycled Devices
Storage Temperatures 25C
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No P/E Cycled Devices
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175C 1.E-04 1.E-01
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that stored at 175 °C. Therefore, this result infers that the underlying CL mechanism that induced tail bits is strongly dependent on the defects density in tunnel oxide layer. Thus, this finding further implies that the underlying CL mechanism is found to be most effective at room temperature storage. A lower average tail bit per block for P/E cycled devices stored at 175 °C is observed as compared to room temperature storage. This is found to be attributed to the annealing of P/E cycling induced defects in tunnel oxide layer due to high temperature storage. Thus, at high temperature storage, the defects density of nitrided tunnel oxide layer reduces and as a result, the generation of the anomalous tail bits deterred [9]. This finding is in good agreement with the result reported on FG flash memory that high temperature storage evidently heals the P/E cycling induced damages which induces lesser Vt shift [12]. In Fig. 5, the time to failure of Vt shift is plotted against the inverse of storage temperature in Kelvin to derive the activation energy (Ea) of the underlying CL mechanism. The time to failure is defined as the time to achieve Vt shift of 0.2 A.U. The Arrhenius plot in Fig. 5 clearly indicates two underlying physical mechanisms that dominate the charge loss behaviour for nitrided NBCTF memory at higher storage temperatures (i.e. 90 °C and above) and lower storage temperatures (i.e. room temperature and 55 °C). This finding corroborates to the observation made on Fig. 3 earlier whereby two distinct Vt shift behaviour is observed at 25 °C and 175 °C. As shown in Fig. 5, for higher storage temperature, i.e. 90 °C and above, the time to failure data points are fitted well and activation energy, Ea of 1.1456 eV is obtained. This value corroborates well with the typical Ea for NBCTF memory [1–3]. However, as shown in Fig. 5, for lower storage temperatures, e.g. room temperature and 55 °C, the data points do not fit well with the rest of storage temperatures on the Arrhenius plot. This implies that the underlying CL mechanism that dominates at lower storage temperatures is significantly different than the mechanism that dominates at higher storage temperatures, i.e. 90 °C and above. The origin of the anomalous tail bits is further investigated with the repeatability experiment. In this repeatability experiment, for a total of 6 iterations, erase, program and Vt per bit measurement was performed before and after 24 h of room temperature storage. If the origin of the anomalous tail bits is due to fabrication process related issues, then there should be consistent repetitions of the same populations of anomalous tail bits that would be captured at each iteration of erase/program/storage for 24 h at room temperature. However, if the origin of these tail bits is due to the stochastic defects induced by P/E cycling, there should be low repetition of the same tail bits for each repetition of erase/program/storage for 24 h at room temperature. As shown in Fig. 6, the percentage of repetitive tail bits is computed by counting the cumulative number of repetitive tail bits for each iteration of erase/program/storage for 24 h at room tempera-
Fig. 4. Average tail bits per block was plotted as a function of various storage duration at bake temperatures of 25 °C and 175 °C.
dividing the total number of tail bits (that exhibits greater than or equal to 0.2 A.U. of Vt shift) with total number of blocks tested which is 100. Thus, as shown in Fig. 4, the average tail bits per block for P/E cycled devices is approximately 2 orders higher than the average tail bits per block for no P/E cycled devices. This indicates the defects density induced by the extensive repeated cycles charge injections in P/E cycling intensifies the underlying CL mechanism of nitrided NBCTF memory. With the implementation of FN tunneling as charge injection mechanism, extensive P/E cycling will typically result in defects such as bulk oxide traps and charge trapping (CT) interface states [1–4]. As shown in Fig. 4, it is found that the average tail bits per block for P/E cycled devices stored at 25 °C is about 5 times higher as compared to the P/E cycled devices
Fig. 5. Arrhenius plot for tail bits exhibits that the charge loss mechanism for storage temperature 25 °C and 55 °C is different than the charge loss mechanism for higher storage temperatures (i.e. 90 °C and above).
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Percentage of repeve tail bits
Percentage of repeve tail bits across 6 repeons of Vt per bit measurements at 25 oC 100% 80% 60% 40% 20% 0% 1
2
3
4
5
6
Number of Iteraons Fig. 6. Percentage of repetitive tail bits across 6 iterations of erase, program and Vt per bit measurements at room temperature.
ture with respect to the physical locations of the tail bits in the memory array based on Vt per bit measurements. The purpose of this evaluation is to investigate whether the tail bits are caused by the stochastic defects generated by P/E cycling or process defects that may caused by TON process. If the tail bits are caused by process defects, there may be significant number of repetitive tail bits. On the other hand, if the tail bits are caused by stochastic defects attributed to the P/E cycling, the repetitive tail bits are relatively low after each iteration of erase/program/storage for 24 h at room temperature. Fig. 6 shows the percentage of repetitive tail bits has reduced significantly after the 1st iteration till the 6th iteration. Therefore, it can be inferred that the origin of these anomalous tail bits is attributed to the stochastic defects generated by P/E cycling stress that reshuffles the Vt level after each iteration of erase/program/storage for 24 h at room temperature. Based on these experimental findings obtained in this work, trap-assisted-tunneling (TAT) mechanism is found to be the dominant CL mechanism attributed to the origin of the generation of the anomalous tail bits on nitrided NBCTF memory [1–4,9,12]. As shown in Fig. 7, TAT mechanism enables the trapped charges in nitride storage layer to tunnel through the stochastic defects generated by extensive P/E cycling on nitrided tunnel oxide layer and leak out to substrate. This charge leakage mechanism dominates at room temperature since P/E cycling induced defects will anneal and heal at high storage temperature. Thus as shown in Fig. 2, the healing effect on P/E cycling induced defects will significantly reduce the number of anomalous tail bits at high storage temperature. Furthermore by comparing the Vt distribution shifts shown in Fig. 3(a) and (b), the CL mechanism that dominates at high temperature storage is clearly different as compare to the one that dominates at room temperature storage. This is because significant number of tail bits was observed to be generated and increased over the storage duration at 25 °C storage in Fig. 3(a). On the other hand in Fig. 3(b), uniform Vt distribution shift was observed to gradually increase over the storage duration at 175 °C but there is no tail bits observed at the lower end of the Vt distribution. Thus based on Figs. 2 and 3, these observations have implied that there are different CL mechanisms that dominate at room temperature storage and high temperature storage. In order to further validate this key finding, an Arrhenius plot was made as shown in Fig. 5 to understand the relationship between the time to failure and storage temperatures. Based on Fig. 5, the time to failure (i.e. time to achieve 0.2 A.U. as previously defined) data points were observed to relatively fit well for storage temperatures at 90, 125, 175 °C, but not for storage temperatures at 25, 55 °C. Furthermore, based on the time to failure data points at 90, 125, 175 °C. Therefore based on Fig. 5, this finding has led us to conclude that the CL mechanism that dominates at high temperature storage is different than the one that dominates at room temperature storage. Furthermore, the CL mechanism that dominates
Fig. 7. Simplified schematic diagram that elucidates the TAT mechanism that leaks the trapped charges in nitride storage layer through P/E cycling induced defects and out to substrate.
at high temperature storage is thermally enhanced with the derived Ea of 1.1456 eV [1–3] which is different than the CL mechanism that dominates at room temperature storage. As shown in Fig. 4, by comparing P/E cycled devices and non P/E cycled devices, extensive P/E cycling stress resulted in the increment of the stochastic defects in nitrided tunnel oxide layer that will significantly increase the probability of trapped charges leaked out through TAT mechanism. Fig. 6 clearly indicates the stochastic nature of the defects induced by P/E cycling stress is the origin of the anomalous tail bits. Moreover as shown in Fig. 6, the contribution of the fabrication related issues to the generation of anomalous tail bits is ruled out since the number of repetitive tail bits across all 6 repetitions is relatively small. Therefore, based on all these findings, the origin of the anomalous tail bits observed on nitrided NBCTF memory is attributed to the charge leakage of trapped charges from nitride storage layer to substrate through TAT mechanism of P/E cycling induced stochastic defects. Despite the key advantages that TON offers, the generation of the anomalous tail bits is genuine reliability concern for nitrided NBCTF memory that requires further optimization in nitridation process and nitrogen distribution profile in the nitrided tunnel oxide layer to achieve the desired reliability performance. Furthermore, in addition to typical high temperature storage test in flash memory qualification process, this work has demonstrated that room temperature storage data retention test can be applied to assess the Vt instability of nitrided NBCTF memory. The room temperature storage test is crucial to investigate the generation of anomalous tail bits since high temperature storage may have masked out the true reliability performance of nitrided NBCTF memory that may have degraded by the anomalous tail bits which dominates at room temperature.
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4. Conclusion
Acknowledgements
In this work, the electrical properties of the anomalous tail bits on 43 nm nitrided NBCTF memory were investigated. The results showed the anomalous tail bits enhances with longer storage durations and dominates at room temperature. Furthermore, the generation of the anomalous tail bits was suppressed at higher storage temperatures due to the annealing of defects that is responsible for TAT mechanism in nitrided tunnel oxide layer. The origin of the anomalous tail bits was found to be attributed to the stochastic defects induced by extensive P/E cycling stress on nitrided NBCTF. TAT mechanism was found to be attributed to the charge leakage mechanism that leads to the generation of the anomalous tail bits. These findings implied that room temperature storage test is a crucial reliability test to assess the reliability performance of nitrided flash memory devices due to the detrimental anomalous tail bits. For future nanoscale nitrided NBCTF memory devices, these findings have implied that the anomalous tail bits are one of the critical reliability concerns that need to be properly assessed in reliability characterization and qualification of nitrided flash memory devices.
The authors would like to recognize all critical research work done by all researchers on non-volatile memory devices. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
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