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Program scheme using common source lines in channel stacked NAND flash memory with layer selection by multilevel operation
Solid State Electronics xxx (xxxx) xxx–xxx
Contents lists available at ScienceDirect
Solid State Electronics journal homepage: www.elsevier.com/locate/sse
Program scheme using common source lines in channel stacked NAND flash memory with layer selection by multilevel operation Do-Bin Kim, Dae Woong Kwon, Seunghyun Kim, Sang-Ho Lee, Byung-Gook Park
⁎
Inter-University Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea
A R T I C L E I N F O
A B S T R A C T
Keywords: 3D stacked NAND flash memory Channel stacked NAND flash memory Layer selection by multi-level operation (LSM)
To obtain high channel boosting potential and reduce a program disturbance in channel stacked NAND flash memory with layer selection by multilevel (LSM) operation, a new program scheme using boosted common source line (CSL) is proposed. The proposed scheme can be achieved by applying proper bias to each layer through its own CSL. Technology computer-aided design (TCAD) simulations are performed to verify the validity of the new method in LSM. Through TCAD simulation, it is revealed that the program disturbance characteristics is effectively improved by the proposed scheme.
1. Introduction Since recent mobile electronic devices such as tablets, laptops, smartphones, and solid-state drives have started to adopt NAND flash memory as their main data storage devices, the demand for low-cost, high-density NAND flash memory has been rapidly increasing. To satisfy the explosive demand for NAND flash memory and achieve continuous scaling, various types of three-dimensional (3D) stacked NAND flash memory have been proposed [1–4]. 3D-stacked NAND flash memory architectures can be divided into two categories. The first is the gate-stacked NAND flash memory, in which current flows through a vertical channel while the gates are shared horizontally by all the strings [1,2]. The second category consists of channel-stacked NAND flash memories, in which the current flows through the horizontally stacked channel and the gates are shared vertically by all the strings [3,4]. In 3D-stacked NAND flash memory architectures, the channelstacked type presents several outstanding advantages in terms of minimal unit cell size, bit line (BL) pitch scaling, use of a single-crystalline Si channel by Si/SiGe epitaxial growth process, and degradation characteristics of read currents caused by the increase in the number of stacked layers [4–7]. However, compared with the gate-stacked type, the channel-stacked type presents critical issues that hinder its use in commercial applications, such as complex array architectures and decoding of the stacked layer. To overcome these problems, our group has recently reported channel-stacked arrays with layer selection by multilevel (LSM) operation [8–11]. In this paper, a boosting scheme using boosted common source line (CSL) for increasing channel boosting potential in LSM is proposed and ⁎
verified by using technology computer-aided design (TCAD) simulations. Consequently, it was confirmed that the program disturbance is suppressed by applying the proposed scheme to LSM through TCAD simulation. 2. Concept of the proposed scheme Fig. 1(a) shows the proposed array architecture with layer selection by multilevel (LSM) operation. The structure has stacked channels made of single-crystalline silicon and similar placement of bit lines (BLs) and word lines (WLs) to that of conventional planar NAND flash memory. However, each vertically aligned string in all stacked layers shares one BL and each layer has its own common source line (CSL). In addition, body contact is eliminated to decrease wiring and process complexity. The detailed fabrication process can be seen in a previous report [8]. The timing and bias conditions of the new program scheme is shown in Fig. 1(b). The scheme is proposed to precharge all channels by applying bias to all CSLs. In the first step, depicted in Fig. 1(b), all channels having both unselected cells (cellunsel) and selected cells (cellsel) are boosted to high potential of VCSL. First, potential of VCSL applied to all CSLs is transferred to channel by turning on ground select line (GSL) and all WLs. At the same time, a voltage of about 1 V is applied to unselected BLs. Then, Vpass is applied to all WLs to increase the channel potential by capacitive coupling with gates. In the second step, shown in Fig. 1(b), program and inhibit operations are performed on each cell by changed channel potential according to the program data. At first, the GSL is discharged to 0 V to prevent potential of CSLs from being delivered to the channel. After that, specific voltages are
Corresponding author. E-mail address: [email protected] (B.-G. Park).
http://dx.doi.org/10.1016/j.sse.2017.10.014
0038-1101/ © 2017 Elsevier Ltd. All rights reserved.
Please cite this article as: Kim, D.-B., Solid State Electronics (2017), http://dx.doi.org/10.1016/j.sse.2017.10.014
Solid State Electronics xxx (xxxx) xxx–xxx
D.-B. Kim et al.
Fig. 1. (a) Bird’s eye view of the proposed channel stacked NAND array with LSM. (b) Bias and timing conditions used during program operations under the proposed scheme.
Fig. 2. Equivalent diagrams that show each case where bit by bit inhibit operation is required in the proposed LSM during program and inhibit operation under the proposed scheme. It explains how the program and inhibit operations occur in cases respectively.
where electrical disconnection is occurred by turned OFF SSTs are maintained. Therefore, the channel potential can be changed or kept according to the program data. As a result, the channel in which the cellsel is located has a potential of 0 V transferred from the BL by combination of the turned ON SSLs. On the other hand, the unselected channel can be boosted due to SSL and GSL being turned OFF. In case A, the cellunsels of BL (0 V)_SSL(OFF) are positioned in the unselected layer
applied to each string select lines (SSLs) for stable LSM operation [8]. For example, each SST in all layers are set to have the targeted Vth (E ∼ P3) for electrical separation of layers respectively, as shown in Fig. 2. When VP2 is applied to SSL1 and VP1 is applied to SSL2, all SSTs on the second layer are turned ON, while one or more SSTs are turned OFF at other layers. At this time, potential of BL can be transferred to channel in case of second layer, and channel potentials of other layers 2
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under the proposed scheme as depicted Fig. 4(a). Fig. 4(b) shows the channel potentials extracted at the interface between the channel and the tunneling oxide according to VCSL. As expected, it is verified that the channel potential is initially increased by precharging the unselected channels through boosted source lines and it makes easy to increase channel potential when Vpass and Vpgm are applied consecutively. In the proposed scheme, program pulse magnitude and duration determine the saturation of the channel potential which is enhanced by the precharge. Therefore, one can simply notice that the precharging effect and the leakage current flowing to the BL are the main factors determining the boosted channel potential in LSM [10]. When a voltage of about 1 V is applied to the CSLs, it can be expected to have the best effect in terms of energy dissipation. Fig. 4(c) and (d) shows potential and electron density in case B, respectively. It is confirmed that the unselected channel under the SSLs is disconnected by the voltage applied to the unselected BL, not the LSM operation. Consequently, Fig. 5 shows that the proposed scheme using boosted source line improves the disturbance characteristic effectively. The disturbance that can occur during the inhibit operation in LSM is similar to cells of conventional NAND flash memory except for the stress induced by the unique LSM operation. It is verified that electron-hole pair (EHP) can be generated by gate-induced drain leakage, and impact ionization between SSL and WL. Consequently, the disturbance characteristics can be degraded by the generated EHPs [10].
and connected to the same BL as that of the cellsel; they share a BL bias of 0 V. However, only cellsel can be programmed by transferring 0 V to the channel through all the SSTs, whereas the cellunsels are inhibited, because one or more SSTs are turned OFF and 0 V is blocked as the consequence. However, in case of B, unselected channel cannot be distinguished from selected channel by LSM operation since cellunsel of BL(1–2 V)_SSLs (ON) are placed in the same planed with the cellsel. Therefore, a sufficiently large voltage about 1–2 V should be applied to the unselected BLs to turn OFF SSLs by increasing channel potential. And then, program voltage is applied to cellunsels to inject electrons from the channel to charge storage layer. Fig. 2 shows program and inhibit situations during the program operation according to the cases described above. When the program operation is performed, it should be noted that cellunsels of case B have better disturbance immunity since channel of BL(1–2 V)_SSLs(ON) is initially precharged only, whereas cellunsels of case A have worse disturbance characteristic due to leakage current flowing from channel to BL [10]. 3. Simulation results and discussion To verify improved characteristics of program disturbance when the proposed scheme is applied, TCAD simulations are carried out using Synopsys Sentaurus. Fig. 3(a) shows the simulated cross-sectional structure of LSM, which are composed of two layers having four WLs, two SSLs, and GSL for simplicity. All the simulated devices have gateall-around (GAA) structure with Si nano-wire radius of 7 nm, gate length and space of 40 nm, BE-SONOS gate dielectric stacks (O/N/O/N/ O films with 1/2/2/6/6 nm), and virtual source/drain (S/D). Program operations are simulated under the bias and timing condition of Fig. 1(b) after block erase and initial setting of Vth of SSTs for LSM operation are executed. As shown in Fig. 2, each SST is set to have a state of E to P3 for layer selection. The results of the Vth setting are shown in Fig. 3(b) and (c) [9,11]. In case A, it is verified that each channel has different potential
4. Conclusion In this study, we proposed the new program scheme which can be adopted to LSM for improving program disturbance characteristics. The proposed scheme can be achieved by applying proper bias to each layer through own CSL. To verify the validity of the new method in LSM, TCAD simulations are performed. As a result, it was confirmed that the proposed scheme is operated properly in LSM after setting the Vths of all the SSTs and the program disturbance characteristics is significantly
Fig. 3. (a) The simulated cross-sectional structure of the proposed LSM. (b) The trapped electron density of each case after setting for the Vth of all SSTs to enable LSM operation. (c) Transfer characteristics of SSTs which are set to the targeted Vths by the Vth setting method.
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Fig. 4. Simulation results of the proposed program scheme. Figures are the cross-sectional images of the proposed LSM structure, and color code means electrostatic potential and electron density contour. The results show that each cell has different gate-to-channel potential under the proposed scheme. (a) Electrical potential contour of case A during program operation. (b) Electrical potentials of channel in case A according to VCSL. (c) Electrical potential contour of case B during program operation. (d) Electron density of (c).
improved by the proposed scheme. Acknowledgement This research was supported by Nano·Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning (2016M3A7B4910348). References [1] Katsumata R et al. Pipe-shaped BiCS flash memory with 16 stacked layers and multilevel-cell operation for ultra high density storage devices. In: Proc symp VLSI technol; June 2009. p. 136–137. [2] Jang J et al. Vertical cell array using TCAT (terabit cell array transistor) technology for ultra high density NAND flash memory. In: Proc symp VLSI technol; June 2009. p. 192–193. [3] Lue H-T et al. A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device. In: Proc symp VLSI technol; June 2010. p. 131–132. [4] Kim Y, et al. Three-dimensional NAND flash architecture design based on singlecrystalline stacked array. IEEE Trans Electron Devices 2012;59(1):35–45. [5] Lue H-T, Chen S-H, Shih Y-H, Hsieh K-Y, Lu C-Y. Overview of 3D NAND flash and progress of vertical gate (VG) architecture. In: Proc IEEE 11th int conf solid-state integr circuit technol (ICSICT); Oct/Nov 2012. p. 1–4. [6] Yun J-G, Kim G, Lee J-E, Kim Y, Shim WB, Lee J-H, et al. Single-crystalline Si
Fig. 5. Transfer characteristics of the cellsel in selected layer and the cellunsel with the proposed scheme and with conventional scheme in unselected layer.
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transistors for layer selection in channel stacked NAND flash memory. IEEE Electron Device Lett 2015;36(12):1318–20. [10] Kwon DW, et al. Analysis on program disturbance in channel-stacked NAND flash memory with layer selection by multilevel operation. IEEE Trans Electron Devices 2016;63(3):1041–6. [11] Kwon DW, et al. Novel program method of string select transistors for layer selection in channel-stacked NAND flash memory. IEEE Trans Electron Devices 2016;63(9):3521–6.
stacked array (STAR) NAND flash memory. IEEE Trans Electron Devices 2011;58(4):1006–14. [7] Hsiao Y-H, Lue H-T, Hsu T-H, Hsieh K-Y, Lu C-Y. A critical examination of 3D stackable NAND flash memory architectures by simulation study of the scaling capability. In: Proc IEEE int memory workshop; May 2010. p. 1–4. [8] Kim W, Seo JY, Kim Y, Park SH, Lee SH, Baek MH, et al. Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM). In: Proc IEEE int electron devices meeting (IEDM); December 2013. p. 3.8.1–3.8.4. [9] Kwon DW, et al. Multi-level threshold voltage setting method of string select
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Contents lists available at ScienceDirect
Solid State Electronics journal homepage: www.elsevier.com/locate/sse
Program scheme using common source lines in channel stacked NAND flash memory with layer selection by multilevel operation Do-Bin Kim, Dae Woong Kwon, Seunghyun Kim, Sang-Ho Lee, Byung-Gook Park
⁎
Inter-University Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea
A R T I C L E I N F O
A B S T R A C T
Keywords: 3D stacked NAND flash memory Channel stacked NAND flash memory Layer selection by multi-level operation (LSM)
To obtain high channel boosting potential and reduce a program disturbance in channel stacked NAND flash memory with layer selection by multilevel (LSM) operation, a new program scheme using boosted common source line (CSL) is proposed. The proposed scheme can be achieved by applying proper bias to each layer through its own CSL. Technology computer-aided design (TCAD) simulations are performed to verify the validity of the new method in LSM. Through TCAD simulation, it is revealed that the program disturbance characteristics is effectively improved by the proposed scheme.
1. Introduction Since recent mobile electronic devices such as tablets, laptops, smartphones, and solid-state drives have started to adopt NAND flash memory as their main data storage devices, the demand for low-cost, high-density NAND flash memory has been rapidly increasing. To satisfy the explosive demand for NAND flash memory and achieve continuous scaling, various types of three-dimensional (3D) stacked NAND flash memory have been proposed [1–4]. 3D-stacked NAND flash memory architectures can be divided into two categories. The first is the gate-stacked NAND flash memory, in which current flows through a vertical channel while the gates are shared horizontally by all the strings [1,2]. The second category consists of channel-stacked NAND flash memories, in which the current flows through the horizontally stacked channel and the gates are shared vertically by all the strings [3,4]. In 3D-stacked NAND flash memory architectures, the channelstacked type presents several outstanding advantages in terms of minimal unit cell size, bit line (BL) pitch scaling, use of a single-crystalline Si channel by Si/SiGe epitaxial growth process, and degradation characteristics of read currents caused by the increase in the number of stacked layers [4–7]. However, compared with the gate-stacked type, the channel-stacked type presents critical issues that hinder its use in commercial applications, such as complex array architectures and decoding of the stacked layer. To overcome these problems, our group has recently reported channel-stacked arrays with layer selection by multilevel (LSM) operation [8–11]. In this paper, a boosting scheme using boosted common source line (CSL) for increasing channel boosting potential in LSM is proposed and ⁎
verified by using technology computer-aided design (TCAD) simulations. Consequently, it was confirmed that the program disturbance is suppressed by applying the proposed scheme to LSM through TCAD simulation. 2. Concept of the proposed scheme Fig. 1(a) shows the proposed array architecture with layer selection by multilevel (LSM) operation. The structure has stacked channels made of single-crystalline silicon and similar placement of bit lines (BLs) and word lines (WLs) to that of conventional planar NAND flash memory. However, each vertically aligned string in all stacked layers shares one BL and each layer has its own common source line (CSL). In addition, body contact is eliminated to decrease wiring and process complexity. The detailed fabrication process can be seen in a previous report [8]. The timing and bias conditions of the new program scheme is shown in Fig. 1(b). The scheme is proposed to precharge all channels by applying bias to all CSLs. In the first step, depicted in Fig. 1(b), all channels having both unselected cells (cellunsel) and selected cells (cellsel) are boosted to high potential of VCSL. First, potential of VCSL applied to all CSLs is transferred to channel by turning on ground select line (GSL) and all WLs. At the same time, a voltage of about 1 V is applied to unselected BLs. Then, Vpass is applied to all WLs to increase the channel potential by capacitive coupling with gates. In the second step, shown in Fig. 1(b), program and inhibit operations are performed on each cell by changed channel potential according to the program data. At first, the GSL is discharged to 0 V to prevent potential of CSLs from being delivered to the channel. After that, specific voltages are
Corresponding author. E-mail address: [email protected] (B.-G. Park).
http://dx.doi.org/10.1016/j.sse.2017.10.014
0038-1101/ © 2017 Elsevier Ltd. All rights reserved.
Please cite this article as: Kim, D.-B., Solid State Electronics (2017), http://dx.doi.org/10.1016/j.sse.2017.10.014
Solid State Electronics xxx (xxxx) xxx–xxx
D.-B. Kim et al.
Fig. 1. (a) Bird’s eye view of the proposed channel stacked NAND array with LSM. (b) Bias and timing conditions used during program operations under the proposed scheme.
Fig. 2. Equivalent diagrams that show each case where bit by bit inhibit operation is required in the proposed LSM during program and inhibit operation under the proposed scheme. It explains how the program and inhibit operations occur in cases respectively.
where electrical disconnection is occurred by turned OFF SSTs are maintained. Therefore, the channel potential can be changed or kept according to the program data. As a result, the channel in which the cellsel is located has a potential of 0 V transferred from the BL by combination of the turned ON SSLs. On the other hand, the unselected channel can be boosted due to SSL and GSL being turned OFF. In case A, the cellunsels of BL (0 V)_SSL(OFF) are positioned in the unselected layer
applied to each string select lines (SSLs) for stable LSM operation [8]. For example, each SST in all layers are set to have the targeted Vth (E ∼ P3) for electrical separation of layers respectively, as shown in Fig. 2. When VP2 is applied to SSL1 and VP1 is applied to SSL2, all SSTs on the second layer are turned ON, while one or more SSTs are turned OFF at other layers. At this time, potential of BL can be transferred to channel in case of second layer, and channel potentials of other layers 2
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under the proposed scheme as depicted Fig. 4(a). Fig. 4(b) shows the channel potentials extracted at the interface between the channel and the tunneling oxide according to VCSL. As expected, it is verified that the channel potential is initially increased by precharging the unselected channels through boosted source lines and it makes easy to increase channel potential when Vpass and Vpgm are applied consecutively. In the proposed scheme, program pulse magnitude and duration determine the saturation of the channel potential which is enhanced by the precharge. Therefore, one can simply notice that the precharging effect and the leakage current flowing to the BL are the main factors determining the boosted channel potential in LSM [10]. When a voltage of about 1 V is applied to the CSLs, it can be expected to have the best effect in terms of energy dissipation. Fig. 4(c) and (d) shows potential and electron density in case B, respectively. It is confirmed that the unselected channel under the SSLs is disconnected by the voltage applied to the unselected BL, not the LSM operation. Consequently, Fig. 5 shows that the proposed scheme using boosted source line improves the disturbance characteristic effectively. The disturbance that can occur during the inhibit operation in LSM is similar to cells of conventional NAND flash memory except for the stress induced by the unique LSM operation. It is verified that electron-hole pair (EHP) can be generated by gate-induced drain leakage, and impact ionization between SSL and WL. Consequently, the disturbance characteristics can be degraded by the generated EHPs [10].
and connected to the same BL as that of the cellsel; they share a BL bias of 0 V. However, only cellsel can be programmed by transferring 0 V to the channel through all the SSTs, whereas the cellunsels are inhibited, because one or more SSTs are turned OFF and 0 V is blocked as the consequence. However, in case of B, unselected channel cannot be distinguished from selected channel by LSM operation since cellunsel of BL(1–2 V)_SSLs (ON) are placed in the same planed with the cellsel. Therefore, a sufficiently large voltage about 1–2 V should be applied to the unselected BLs to turn OFF SSLs by increasing channel potential. And then, program voltage is applied to cellunsels to inject electrons from the channel to charge storage layer. Fig. 2 shows program and inhibit situations during the program operation according to the cases described above. When the program operation is performed, it should be noted that cellunsels of case B have better disturbance immunity since channel of BL(1–2 V)_SSLs(ON) is initially precharged only, whereas cellunsels of case A have worse disturbance characteristic due to leakage current flowing from channel to BL [10]. 3. Simulation results and discussion To verify improved characteristics of program disturbance when the proposed scheme is applied, TCAD simulations are carried out using Synopsys Sentaurus. Fig. 3(a) shows the simulated cross-sectional structure of LSM, which are composed of two layers having four WLs, two SSLs, and GSL for simplicity. All the simulated devices have gateall-around (GAA) structure with Si nano-wire radius of 7 nm, gate length and space of 40 nm, BE-SONOS gate dielectric stacks (O/N/O/N/ O films with 1/2/2/6/6 nm), and virtual source/drain (S/D). Program operations are simulated under the bias and timing condition of Fig. 1(b) after block erase and initial setting of Vth of SSTs for LSM operation are executed. As shown in Fig. 2, each SST is set to have a state of E to P3 for layer selection. The results of the Vth setting are shown in Fig. 3(b) and (c) [9,11]. In case A, it is verified that each channel has different potential
4. Conclusion In this study, we proposed the new program scheme which can be adopted to LSM for improving program disturbance characteristics. The proposed scheme can be achieved by applying proper bias to each layer through own CSL. To verify the validity of the new method in LSM, TCAD simulations are performed. As a result, it was confirmed that the proposed scheme is operated properly in LSM after setting the Vths of all the SSTs and the program disturbance characteristics is significantly
Fig. 3. (a) The simulated cross-sectional structure of the proposed LSM. (b) The trapped electron density of each case after setting for the Vth of all SSTs to enable LSM operation. (c) Transfer characteristics of SSTs which are set to the targeted Vths by the Vth setting method.
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Fig. 4. Simulation results of the proposed program scheme. Figures are the cross-sectional images of the proposed LSM structure, and color code means electrostatic potential and electron density contour. The results show that each cell has different gate-to-channel potential under the proposed scheme. (a) Electrical potential contour of case A during program operation. (b) Electrical potentials of channel in case A according to VCSL. (c) Electrical potential contour of case B during program operation. (d) Electron density of (c).
improved by the proposed scheme. Acknowledgement This research was supported by Nano·Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning (2016M3A7B4910348). References [1] Katsumata R et al. Pipe-shaped BiCS flash memory with 16 stacked layers and multilevel-cell operation for ultra high density storage devices. In: Proc symp VLSI technol; June 2009. p. 136–137. [2] Jang J et al. Vertical cell array using TCAT (terabit cell array transistor) technology for ultra high density NAND flash memory. In: Proc symp VLSI technol; June 2009. p. 192–193. [3] Lue H-T et al. A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device. In: Proc symp VLSI technol; June 2010. p. 131–132. [4] Kim Y, et al. Three-dimensional NAND flash architecture design based on singlecrystalline stacked array. IEEE Trans Electron Devices 2012;59(1):35–45. [5] Lue H-T, Chen S-H, Shih Y-H, Hsieh K-Y, Lu C-Y. Overview of 3D NAND flash and progress of vertical gate (VG) architecture. In: Proc IEEE 11th int conf solid-state integr circuit technol (ICSICT); Oct/Nov 2012. p. 1–4. [6] Yun J-G, Kim G, Lee J-E, Kim Y, Shim WB, Lee J-H, et al. Single-crystalline Si
Fig. 5. Transfer characteristics of the cellsel in selected layer and the cellunsel with the proposed scheme and with conventional scheme in unselected layer.
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transistors for layer selection in channel stacked NAND flash memory. IEEE Electron Device Lett 2015;36(12):1318–20. [10] Kwon DW, et al. Analysis on program disturbance in channel-stacked NAND flash memory with layer selection by multilevel operation. IEEE Trans Electron Devices 2016;63(3):1041–6. [11] Kwon DW, et al. Novel program method of string select transistors for layer selection in channel-stacked NAND flash memory. IEEE Trans Electron Devices 2016;63(9):3521–6.
stacked array (STAR) NAND flash memory. IEEE Trans Electron Devices 2011;58(4):1006–14. [7] Hsiao Y-H, Lue H-T, Hsu T-H, Hsieh K-Y, Lu C-Y. A critical examination of 3D stackable NAND flash memory architectures by simulation study of the scaling capability. In: Proc IEEE int memory workshop; May 2010. p. 1–4. [8] Kim W, Seo JY, Kim Y, Park SH, Lee SH, Baek MH, et al. Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM). In: Proc IEEE int electron devices meeting (IEDM); December 2013. p. 3.8.1–3.8.4. [9] Kwon DW, et al. Multi-level threshold voltage setting method of string select
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