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Influence of SiH4 process step on physical and electrical properties of advanced copper interconnects
Microelectronic Engineering 76 (2004) 106–112 www.elsevier.com/locate/mee
Influence of SiH4 process step on physical and electrical properties of advanced copper interconnects S. Chhun a,*, L.G. Gosset a, N. Casanova b, J.F. Guillaumond b, P. Dumont-Girard b, X. Federspiel a, R. Pantel b, V. Arnal b, L. Arnaud c, J. Torres b a
Philips Semiconductors Crolles R&D, 860 rue Jean Monnet, 38920 Crolles, France b ST Microelectronics, 850 rue Jean Monnet, 38926 Crolles Cedex, France c CEA Grenoble-LETI, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France Available online 13 August 2004
Abstract Self-aligned barriers on copper are widely investigated as a promising solution to replace standard PECVD dielectric barriers for the 65 nm technology node and beyond. As an alternative to electroless or selective CVD deposition, CuSiN barriers, based on the controlled modification of copper surface using a sequential exposure to SiH4 flow and NH3 plasma has been proposed. This paper focuses on the key role played by SiH4 flow on the physical and electrical barrier characteristics and more particularly on the existing relation between silane flow and Ta atoms from the TaN/Ta metal barrier. Non-regular defects observed after electromigration tests were not only attributed to intentionally modified copper surface but also to the presence of Ta atoms that diffused through copper lines during the tests. Ó 2004 Elsevier B.V. All rights reserved. Keywords: Self-aligned barrier; Copper interconnects; Silicidation; Tantalum; Electromigration
1. Introduction To achieve a high level of propagation performances for global interconnects such as cross-talk or delay time for the 65 nm technology node and be*
Corresponding author. Tel.: +33 4 76 92 52 41; fax: +33 4 76 92 50 71. E-mail address: [email protected] (S. Chhun).
yond, integration of ultra-low k (ULK) dielectrics may require self-aligned barriers on copper. Indeed, standard plasma enhanced chemical vapor deposition (PECVD) liners have a higher k value than the inter-metal dielectric (IMD), thus degrading the effective dielectric permittivity of the total interconnect stack [1]. In addition, the weak Cu/dielectric capping interface was evidenced to be responsible for electromigration (EM) failure for
0167-9317/$ - see front matter Ó 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2004.07.022
S. Chhun et al. / Microelectronic Engineering 76 (2004) 106–112
narrow Cu lines, which is a major concern for next ICs generations. As an alternative to metal-based self-aligned barriers on copper, founded on selective CVD or electroless process [2–5], a simple process based on copper surface modification control and named CuSiN was proposed [6]. Promising results in terms of barrier efficiency against copper diffusion, EM performances were obtained. In this paper, the key role played by silane (SiH4) on physical and electrical barrier characteristics and its interaction with Ta atoms during CuSiN formation and EM tests was more particularly investigated.
2. Experimental The CuSiN self-aligned barrier formation is based on a sequential treatment using SiH4 flow and NH3 plasma, following process conditions previously described in [6]. Since SiH4 molecules decomposition on Cu surface is responsible for Cu enrichment with Si, silicidation of copper surface can be easily tuned through SiH4 concentration and temperature process conditions. Sheet resistance measurements were carried out prior and after CuSiN barrier formation using 8 in. blanket wafers with Cu/Ta/TaN/SiO2/Si stack. In parallel, non-treated Cu surfaces were also capped with 40 nm thick SiN layers with different process flow conditions. Finally, both splits were further capped with 100 nm thick undopped silicon glass (USG). Atomic depth profiles were measured for Cu, Si, N, and O atoms using secondary ion mass spectroscopy (SIMS) analyses and Cs+ ions bombardment. Three metal-levels of Cu–SiOC interconnect stack with CuSiN barrier processed at metal 2 level were prepared to electrically characterize the selfaligned barrier performances. Line resistance and leakage currents were measured using 7 m long, 0.14 lm wide and 0.14 lm spaced comb/serpentine test structures, before barrier formation and after metal-3 completion. The effect of a 50 min final annealing at 400 °C on electrical characteristics was also investigated. Top view scanning electron microscopy (SEM), transmission electron microscopy (TEM) observa-
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tions and electron energy loss spectroscopy (EELS) analyses were performed on EM structures previously described [6] to examine failure mechanisms occurring during EM tests.
3. Results and discussion 3.1. Silicidation impact on Cu Current technology nodes integrate dielectric capping layers (SiN, SiC, SiCN,. . .) on copper as a barrier against Cu diffusion. SiH4-based precursors used for these dielectrics may degrade Cu resistivity when process sequence for deposition is not controlled enough to limit Si atoms incorporation inside copper. Fig. 1(a) evidences this behavior for a SiN dielectric with a nonstandard deposition sequence. Hence, Si incorporation control at copper surface is a key point to keep the benefits of both introducing a modification of the copper surface and low resistive copper within the line to address propagation performances requests. CuSiN successful integration within ULK-Cu interconnects must overcome the same issues in addition to fill standard barrier performances (e.g. barrier efficiency to copper diffusion, to limit Cu corrosion, to improve stress-voiding and EM performances. . .). Obviously, such a process could also be implemented in current technologies in addition to standard dielectric deposition to improve EM performances as evidenced in [6]. Finally, Fig. 1(b) illustrates CuSiN integration with an optimized SiH4 process conditions to limit the incorporation inside the Cu at the very-near copper surface region, thus avoiding any degradation of Cu resistance. In Table 1, the dependence of Si incorporation level inside copper with process parameters (silicidation duration, Si concentration, and process temperature) was investigated using an invariable NH3 plasma step. Process temperature is a critical parameter that controls Si diffusion into Cu after SiH4-based precursors have decomposed on Cu surface. Moreover, the amount of available Si atoms at wafer surface, which depends on process temperature, SiH4 concentration and its
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Fig. 1. SIMS profiles for (a) uncontrolled Si incorporation during a SiN deposition step compared to (b) a localised Si incorporation at the copper surface for a CuSiN barrier.
Table 1 Impact of process temperature and Si amount on copper resistance increase Total amount of Si in process chamber
Process temperature
% Resistance increase
Q1 Q1 Q2 > Q1
T1 < T2 T2 T2
0.4 5.4 22
decomposition, will also drive Si incorporation inside copper. Therefore, it is necessary to limit Si atoms concentration at wafer surface so that Si incorporation only occurs at copper surface as evidenced for the CuSiN barrier analyzed by SIMS in Fig. 1(b). Finally, TOF SIMS experiments carried out after self-aligned barrier processing, USG capping and annealing confirmed barrier efficiency against Cu diffusion previously shown using LPD-AAS technique [6]. 3.2. CuSiN integration in multi-level Cu/SiOC interconnects Optimized CuSiN process was implemented in a standard integration process flow instead of SiCN as copper capping at metal 2 level and electrical characteristics such as line resistance and leakage currents were compared. A same gain of one decade on leakage current was measured for both
types of barriers after metal 3 was completed, in addition to a dispersion reduction of leakage current properties for CuSiN barrier (Fig. 2(a)). This result evidences improved CuSiN process control and integration performances since in first experiments [6], only leakage current improvement was observed for SiCN capping using the same integration scheme. However, an improvement of two decades of magnitude for leakage current was measured for SiCN after an additional annealing treatment, whereas only a slight enhancement was detected for CuSiN barrier. Typically, leakage current gain after annealing for SiCN barrier is due to out diffusing species such as H and OH initially incorporated during PECVD. Therefore, CuSiN formation process must lead to slight dielectric contamination with different species from those for SiCN PECVD process. In addition, these contaminating species can be characterized with lower out-diffusion properties. As expected from fullsheet experiments previously described, little impact on line resistance for CuSiN process was measured (Fig. 2(b)), even after annealing, thus confirming first integration experiments [6] and well controlled Si incorporation. Moreover, the lowest leakage currents were also measured for the most limiting Si incorporation CuSiN processes, demonstrating that SiH4 flow is at least partially responsible for leakage current slight degradation.
S. Chhun et al. / Microelectronic Engineering 76 (2004) 106–112
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Fig. 2. Cumulative curves of (a) leakage current and (b) lines resistance for CuSiN barrier (m) and SiCN (j) before barrier processing at metal 2 (bold), after barrier formation and metal 3 completion (grey) and after a 400 °C annealing (blank).
3.3. Electromigration defects analysis Wafer and packaged level EM tests demonstrated the benefits of introducing CuSiN barrier to improve EM performances for advanced interconnects stack. In fact, one order of magnitude in mean time to failure (MTTF) was measured for CuSiN in comparison to SiC dielectric capping [6]. Such promising results clearly opens perspectives for CuSiN integration as a stand-alone process for advanced interconnects as well as a surface preparation for standard dielectric capping in current technology nodes. However, top view SEM observations after line failure corresponding to a 10% line resistance in-
crease revealed that there is no extrusion for CuSiN capped 0.26 lm wide lines contrary to SiC ones (Fig. 3(a)). For wider lines, extrusions were observed, still at a less extend than for SiC (Fig. 3(b)). Since Si incorporation into Cu during silicidation occurs at Cu grain boundaries, CuSiN narrow and wide lines behavior variation can be attributed to the difference of line microstructure. Furthermore, extrusions happened at the end of EM test in the case of CuSiN barriers whereas for SiC ones, extrusions occurred throughout EM tests. Line resistance increase leading to line failure is typically due to voids formation in the middle of Cu lines as illustrated in Fig. 4. In order to
Fig. 3. (a) Extrusion observation for a 1.2 lm SiC barrier capped Cu line and (b) percentage of extrusion during EM tests for CuSiN and SiC barrier for 0.28 and 1.2 lm wide lines.
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Fig. 4. Top view void observation of a 1.2 lm wide CuSiN capped tested line by SEM.
understand that difference of trend in terms of time to failure, the atomic composition and the defects around the failing zone for CuSiN was carefully examined. Lengthwise (Fig. 5) and top view SEM cross-sections revealed standard voids formation at the interface between CuSiN and IMD, where adhesion is still weaker than elsewhere between Cu and TaN/Ta metallic barrier [7,8]. In addition to standard voids, the bottom interface is also impacted. That behavior was present neither for non-tested CuSiN structures nor for SiC ones, disapproving any standard integration trouble. Nevertheless, those new defects are not critical in terms of failure but its mechanism has to be understood.
In addition to these new defects, a non-negligible amount of Ta atoms was shown at the surface of CuSiN passivated lines using TEM EELS composition analyses (Fig. 6). On the contrary, nontested lines for both a standard dielectric barrier and for a CuSiN one revealed less than 1% of Ta at the Cu surface using the same analyses technique. Therefore, some tantalum from the TaN/ Ta metallic barrier has diffused through Cu during EM tests. But at the same time, the impact of Ta diffusion through Cu was not detectable using resistance increase detection of the EM structures, which was set to 10% of the nominal value. In fact, Latt et al. [9] reported Ta diffusion at Cu surface in association with a resistance increase by a factor 10, initiated after 30 min annealing at 650 °C for a Cu/Ta/SiO2/Si stack and at 750 °C when a SiNx coating is deposited on Cu. In our experiments, tantalum diffusion from TaN/Ta barrier to Cu surface concerned mainly CuSiN barriers after EM tests, for which a longer time to failure than a standard SiC barrier was demonstrated [6] without noticeable resistance increase before line failure. To evaluate the potential interactions between Si, Cu and Ta atoms, three different SiN process (including process analyzed in Fig. 1(a)) leading to Si incorporation in copper were deposited on blanket Cu wafers. An additional SiO2 layer was further deposited on SiN and accurate atomic depth profiles were obtained using SIMS analyses (Fig. 7). In the case of the highest level
Fig. 5. Lengthwise SEM cross-sections on the same 1.2 lm wide CuSiN capped tested line showing (left) standard voids and (right) new defect shape.
S. Chhun et al. / Microelectronic Engineering 76 (2004) 106–112
Fig. 6. EELS analyses of the top Cu interface on EM tested lines. As the analyzed multilayer is capped by SiO2, Si signal should be as deep as or deeper than O signal which is not the case here, since Ta, which is heavier than Si, hides Si signal. The first Ta peak decrease when O signal decreases can be explained by a TaxOy compound and a TaxSiy compound must be present between 15 and 25 nm.
of Si incorporation, a profound Ta diffusion to Cu is revealed (Fig. 7(a)). On the opposite, Ta diffusion is lowered as Si incorporation becomes weaker (Figs. 7(b) and (c)). Therefore, this
Fig. 7. SIMS profiles of SiO2/SiN/Cu/TaN/Ta/SiO2 multilayer after annealing for different SiN deposition processes.
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experiment evidenced a strong relation between Si incorporation from surface into Cu and Ta diffusion up to the surface of metal lines. This mechanism should also occur for CuSiN barrier and may explain residual Ta atoms initially detected on patterned structures. Cu–tantalum barrier bottom interface is also of high interest as supported by SIMS profiles. Si detection in this area can be explained by SIMS abrasion effect as in Fig. 7(c), where a bi-modal distribution is observed. As Si incorporation increases at this interface, in association with Ta diffusion through copper, Si distribution is modified. In fact, the first Si peak disappears in the second one due to a higher Si amount at the Cu/Ta interface, evidenced by a Ta signal increase when Si signal increased (Fig. 7(a)). In addition to the controlled introduction of Si at the very-near surface of copper lines, it is also necessary to point out that the mechanisms leading to Ta diffusion through the copper surface for blanket wafers experiments may slightly differ from patterned wafers when self-aligned barriers are processed. In fact, in this latter case, Ta atoms are also present on the edges of lines and direct reaction with Si atoms can occur during CuSiN process. As a consequence, Ta diffusion through Cu surface may participate in strengthening the interface between the metal line and the IMD against EM line failure. As a conclusion, the mechanisms responsible for Ta detection at copper surface for CuSiN barriers are very complex; it is necessary to distinguish the diffusion of Ta to the Cu surface due to Si incorporation in Cu as shown using SiN capping, from specific mechanisms leading to additional Ta diffusion through Cu surface and non-regular voids formation. However, since fewer extrusions are obtained during EM tests when CuSiN process is incorporated, it can also be assumed that a stronger interface at the top of side walls, between TaN/Ta barrier, Cu and IMD is formed because of interactions between Cu, Si and Ta atoms. Additional experiments and characterizations are in progress to understand the mechanisms responsible for Ta diffusion towards the surface, in the general case of dielectric as capping layers on copper, and in the more
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particular case of the CuSiN self-aligned barrier. However, Ta diffusion through Cu surface does not seem to be an issue, but on the opposite may participate in electrical and EM performances when CuSiN self-aligned barrier is integrated on copper.
Acknowledgement The authors would like to thank F. Pico (ST) from characterization group for FIB SEM observations.
References 4. Conclusion The crucial silicidation control of copper during SiH4 flow exposure to form CuSiN self-aligned barrier on copper was demonstrated. The barrier was integrated in a three metal level Cu–SiOC interconnect stack at metal two and excellent electrical performances in terms of line resistance and leakage current were obtained. Finally, the mechanisms responsible for tantalum diffusion to Cu surface observed after EM tests and its relation with Si incorporation in copper were investigated. As a consequence, CuSiN self-aligned barrier on copper is a promising technique either as a first step process before dielectric liners deposition to enhance reliability performances and as a standalone process to improve signal propagation performances for the 65 nm technology node and beyond.
[1] K. Goto, H. Yuasa, A. Andatsu, M. Matsuura, in: Proceedings of the 2003 International Interconnect Technology Conference, 2003, pp. 6–8. [2] E.G. Colgan, Thin Solid Films 262 (1995) 120–123. [3] Y. Shacham-Diamand, Y. Sverdlov, N. Petrov, J. Electrochem. Soc. 148 (2001) C162–C167. [4] C.-K. Hu, L. Gognac, R. Rosenberg, E. Liniger, J. Rubino, C. Sambucetti, A. Domenicucci, X. Chen, A.K. Stamper, Appl. Phys. Lett. 81 (2002) 1782. [5] T. Ko, C.L. Chang, S.W. Chou, M.W. Lin, C.J. Lin, C.H. Shih, S.H. Su, M.H. Tsai, W.S. Shue, M.S. Liang, High performance/reliability Cu interconnect with selective CoWP cap, Digest of Technical Papers of 2003 Symposium on VLSI Technology, 2003, pp. 106–110. [6] L.G. Gosset, V. Arnal, S. Chhun, in: Advanced Metallization Conference, 2003. [7] N.L. Michael, C.-U. Kim, Q.-T. Jiang, R.1. Augur, P. Gillepsie, J. Electron. Mater. 31 (2002) 1004–1008. [8] M.W. Lane, E.G. Ginger, J.R. Lloyd, J. Appl. Phys. 93 (2003) 1417. [9] K.M. Latt, H.S. Park, H.L. Seng, J. Mater. Sci. 37 (2002) 4181–8188.
Influence of SiH4 process step on physical and electrical properties of advanced copper interconnects S. Chhun a,*, L.G. Gosset a, N. Casanova b, J.F. Guillaumond b, P. Dumont-Girard b, X. Federspiel a, R. Pantel b, V. Arnal b, L. Arnaud c, J. Torres b a
Philips Semiconductors Crolles R&D, 860 rue Jean Monnet, 38920 Crolles, France b ST Microelectronics, 850 rue Jean Monnet, 38926 Crolles Cedex, France c CEA Grenoble-LETI, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France Available online 13 August 2004
Abstract Self-aligned barriers on copper are widely investigated as a promising solution to replace standard PECVD dielectric barriers for the 65 nm technology node and beyond. As an alternative to electroless or selective CVD deposition, CuSiN barriers, based on the controlled modification of copper surface using a sequential exposure to SiH4 flow and NH3 plasma has been proposed. This paper focuses on the key role played by SiH4 flow on the physical and electrical barrier characteristics and more particularly on the existing relation between silane flow and Ta atoms from the TaN/Ta metal barrier. Non-regular defects observed after electromigration tests were not only attributed to intentionally modified copper surface but also to the presence of Ta atoms that diffused through copper lines during the tests. Ó 2004 Elsevier B.V. All rights reserved. Keywords: Self-aligned barrier; Copper interconnects; Silicidation; Tantalum; Electromigration
1. Introduction To achieve a high level of propagation performances for global interconnects such as cross-talk or delay time for the 65 nm technology node and be*
Corresponding author. Tel.: +33 4 76 92 52 41; fax: +33 4 76 92 50 71. E-mail address: [email protected] (S. Chhun).
yond, integration of ultra-low k (ULK) dielectrics may require self-aligned barriers on copper. Indeed, standard plasma enhanced chemical vapor deposition (PECVD) liners have a higher k value than the inter-metal dielectric (IMD), thus degrading the effective dielectric permittivity of the total interconnect stack [1]. In addition, the weak Cu/dielectric capping interface was evidenced to be responsible for electromigration (EM) failure for
0167-9317/$ - see front matter Ó 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2004.07.022
S. Chhun et al. / Microelectronic Engineering 76 (2004) 106–112
narrow Cu lines, which is a major concern for next ICs generations. As an alternative to metal-based self-aligned barriers on copper, founded on selective CVD or electroless process [2–5], a simple process based on copper surface modification control and named CuSiN was proposed [6]. Promising results in terms of barrier efficiency against copper diffusion, EM performances were obtained. In this paper, the key role played by silane (SiH4) on physical and electrical barrier characteristics and its interaction with Ta atoms during CuSiN formation and EM tests was more particularly investigated.
2. Experimental The CuSiN self-aligned barrier formation is based on a sequential treatment using SiH4 flow and NH3 plasma, following process conditions previously described in [6]. Since SiH4 molecules decomposition on Cu surface is responsible for Cu enrichment with Si, silicidation of copper surface can be easily tuned through SiH4 concentration and temperature process conditions. Sheet resistance measurements were carried out prior and after CuSiN barrier formation using 8 in. blanket wafers with Cu/Ta/TaN/SiO2/Si stack. In parallel, non-treated Cu surfaces were also capped with 40 nm thick SiN layers with different process flow conditions. Finally, both splits were further capped with 100 nm thick undopped silicon glass (USG). Atomic depth profiles were measured for Cu, Si, N, and O atoms using secondary ion mass spectroscopy (SIMS) analyses and Cs+ ions bombardment. Three metal-levels of Cu–SiOC interconnect stack with CuSiN barrier processed at metal 2 level were prepared to electrically characterize the selfaligned barrier performances. Line resistance and leakage currents were measured using 7 m long, 0.14 lm wide and 0.14 lm spaced comb/serpentine test structures, before barrier formation and after metal-3 completion. The effect of a 50 min final annealing at 400 °C on electrical characteristics was also investigated. Top view scanning electron microscopy (SEM), transmission electron microscopy (TEM) observa-
107
tions and electron energy loss spectroscopy (EELS) analyses were performed on EM structures previously described [6] to examine failure mechanisms occurring during EM tests.
3. Results and discussion 3.1. Silicidation impact on Cu Current technology nodes integrate dielectric capping layers (SiN, SiC, SiCN,. . .) on copper as a barrier against Cu diffusion. SiH4-based precursors used for these dielectrics may degrade Cu resistivity when process sequence for deposition is not controlled enough to limit Si atoms incorporation inside copper. Fig. 1(a) evidences this behavior for a SiN dielectric with a nonstandard deposition sequence. Hence, Si incorporation control at copper surface is a key point to keep the benefits of both introducing a modification of the copper surface and low resistive copper within the line to address propagation performances requests. CuSiN successful integration within ULK-Cu interconnects must overcome the same issues in addition to fill standard barrier performances (e.g. barrier efficiency to copper diffusion, to limit Cu corrosion, to improve stress-voiding and EM performances. . .). Obviously, such a process could also be implemented in current technologies in addition to standard dielectric deposition to improve EM performances as evidenced in [6]. Finally, Fig. 1(b) illustrates CuSiN integration with an optimized SiH4 process conditions to limit the incorporation inside the Cu at the very-near copper surface region, thus avoiding any degradation of Cu resistance. In Table 1, the dependence of Si incorporation level inside copper with process parameters (silicidation duration, Si concentration, and process temperature) was investigated using an invariable NH3 plasma step. Process temperature is a critical parameter that controls Si diffusion into Cu after SiH4-based precursors have decomposed on Cu surface. Moreover, the amount of available Si atoms at wafer surface, which depends on process temperature, SiH4 concentration and its
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Fig. 1. SIMS profiles for (a) uncontrolled Si incorporation during a SiN deposition step compared to (b) a localised Si incorporation at the copper surface for a CuSiN barrier.
Table 1 Impact of process temperature and Si amount on copper resistance increase Total amount of Si in process chamber
Process temperature
% Resistance increase
Q1 Q1 Q2 > Q1
T1 < T2 T2 T2
0.4 5.4 22
decomposition, will also drive Si incorporation inside copper. Therefore, it is necessary to limit Si atoms concentration at wafer surface so that Si incorporation only occurs at copper surface as evidenced for the CuSiN barrier analyzed by SIMS in Fig. 1(b). Finally, TOF SIMS experiments carried out after self-aligned barrier processing, USG capping and annealing confirmed barrier efficiency against Cu diffusion previously shown using LPD-AAS technique [6]. 3.2. CuSiN integration in multi-level Cu/SiOC interconnects Optimized CuSiN process was implemented in a standard integration process flow instead of SiCN as copper capping at metal 2 level and electrical characteristics such as line resistance and leakage currents were compared. A same gain of one decade on leakage current was measured for both
types of barriers after metal 3 was completed, in addition to a dispersion reduction of leakage current properties for CuSiN barrier (Fig. 2(a)). This result evidences improved CuSiN process control and integration performances since in first experiments [6], only leakage current improvement was observed for SiCN capping using the same integration scheme. However, an improvement of two decades of magnitude for leakage current was measured for SiCN after an additional annealing treatment, whereas only a slight enhancement was detected for CuSiN barrier. Typically, leakage current gain after annealing for SiCN barrier is due to out diffusing species such as H and OH initially incorporated during PECVD. Therefore, CuSiN formation process must lead to slight dielectric contamination with different species from those for SiCN PECVD process. In addition, these contaminating species can be characterized with lower out-diffusion properties. As expected from fullsheet experiments previously described, little impact on line resistance for CuSiN process was measured (Fig. 2(b)), even after annealing, thus confirming first integration experiments [6] and well controlled Si incorporation. Moreover, the lowest leakage currents were also measured for the most limiting Si incorporation CuSiN processes, demonstrating that SiH4 flow is at least partially responsible for leakage current slight degradation.
S. Chhun et al. / Microelectronic Engineering 76 (2004) 106–112
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Fig. 2. Cumulative curves of (a) leakage current and (b) lines resistance for CuSiN barrier (m) and SiCN (j) before barrier processing at metal 2 (bold), after barrier formation and metal 3 completion (grey) and after a 400 °C annealing (blank).
3.3. Electromigration defects analysis Wafer and packaged level EM tests demonstrated the benefits of introducing CuSiN barrier to improve EM performances for advanced interconnects stack. In fact, one order of magnitude in mean time to failure (MTTF) was measured for CuSiN in comparison to SiC dielectric capping [6]. Such promising results clearly opens perspectives for CuSiN integration as a stand-alone process for advanced interconnects as well as a surface preparation for standard dielectric capping in current technology nodes. However, top view SEM observations after line failure corresponding to a 10% line resistance in-
crease revealed that there is no extrusion for CuSiN capped 0.26 lm wide lines contrary to SiC ones (Fig. 3(a)). For wider lines, extrusions were observed, still at a less extend than for SiC (Fig. 3(b)). Since Si incorporation into Cu during silicidation occurs at Cu grain boundaries, CuSiN narrow and wide lines behavior variation can be attributed to the difference of line microstructure. Furthermore, extrusions happened at the end of EM test in the case of CuSiN barriers whereas for SiC ones, extrusions occurred throughout EM tests. Line resistance increase leading to line failure is typically due to voids formation in the middle of Cu lines as illustrated in Fig. 4. In order to
Fig. 3. (a) Extrusion observation for a 1.2 lm SiC barrier capped Cu line and (b) percentage of extrusion during EM tests for CuSiN and SiC barrier for 0.28 and 1.2 lm wide lines.
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S. Chhun et al. / Microelectronic Engineering 76 (2004) 106–112
Fig. 4. Top view void observation of a 1.2 lm wide CuSiN capped tested line by SEM.
understand that difference of trend in terms of time to failure, the atomic composition and the defects around the failing zone for CuSiN was carefully examined. Lengthwise (Fig. 5) and top view SEM cross-sections revealed standard voids formation at the interface between CuSiN and IMD, where adhesion is still weaker than elsewhere between Cu and TaN/Ta metallic barrier [7,8]. In addition to standard voids, the bottom interface is also impacted. That behavior was present neither for non-tested CuSiN structures nor for SiC ones, disapproving any standard integration trouble. Nevertheless, those new defects are not critical in terms of failure but its mechanism has to be understood.
In addition to these new defects, a non-negligible amount of Ta atoms was shown at the surface of CuSiN passivated lines using TEM EELS composition analyses (Fig. 6). On the contrary, nontested lines for both a standard dielectric barrier and for a CuSiN one revealed less than 1% of Ta at the Cu surface using the same analyses technique. Therefore, some tantalum from the TaN/ Ta metallic barrier has diffused through Cu during EM tests. But at the same time, the impact of Ta diffusion through Cu was not detectable using resistance increase detection of the EM structures, which was set to 10% of the nominal value. In fact, Latt et al. [9] reported Ta diffusion at Cu surface in association with a resistance increase by a factor 10, initiated after 30 min annealing at 650 °C for a Cu/Ta/SiO2/Si stack and at 750 °C when a SiNx coating is deposited on Cu. In our experiments, tantalum diffusion from TaN/Ta barrier to Cu surface concerned mainly CuSiN barriers after EM tests, for which a longer time to failure than a standard SiC barrier was demonstrated [6] without noticeable resistance increase before line failure. To evaluate the potential interactions between Si, Cu and Ta atoms, three different SiN process (including process analyzed in Fig. 1(a)) leading to Si incorporation in copper were deposited on blanket Cu wafers. An additional SiO2 layer was further deposited on SiN and accurate atomic depth profiles were obtained using SIMS analyses (Fig. 7). In the case of the highest level
Fig. 5. Lengthwise SEM cross-sections on the same 1.2 lm wide CuSiN capped tested line showing (left) standard voids and (right) new defect shape.
S. Chhun et al. / Microelectronic Engineering 76 (2004) 106–112
Fig. 6. EELS analyses of the top Cu interface on EM tested lines. As the analyzed multilayer is capped by SiO2, Si signal should be as deep as or deeper than O signal which is not the case here, since Ta, which is heavier than Si, hides Si signal. The first Ta peak decrease when O signal decreases can be explained by a TaxOy compound and a TaxSiy compound must be present between 15 and 25 nm.
of Si incorporation, a profound Ta diffusion to Cu is revealed (Fig. 7(a)). On the opposite, Ta diffusion is lowered as Si incorporation becomes weaker (Figs. 7(b) and (c)). Therefore, this
Fig. 7. SIMS profiles of SiO2/SiN/Cu/TaN/Ta/SiO2 multilayer after annealing for different SiN deposition processes.
111
experiment evidenced a strong relation between Si incorporation from surface into Cu and Ta diffusion up to the surface of metal lines. This mechanism should also occur for CuSiN barrier and may explain residual Ta atoms initially detected on patterned structures. Cu–tantalum barrier bottom interface is also of high interest as supported by SIMS profiles. Si detection in this area can be explained by SIMS abrasion effect as in Fig. 7(c), where a bi-modal distribution is observed. As Si incorporation increases at this interface, in association with Ta diffusion through copper, Si distribution is modified. In fact, the first Si peak disappears in the second one due to a higher Si amount at the Cu/Ta interface, evidenced by a Ta signal increase when Si signal increased (Fig. 7(a)). In addition to the controlled introduction of Si at the very-near surface of copper lines, it is also necessary to point out that the mechanisms leading to Ta diffusion through the copper surface for blanket wafers experiments may slightly differ from patterned wafers when self-aligned barriers are processed. In fact, in this latter case, Ta atoms are also present on the edges of lines and direct reaction with Si atoms can occur during CuSiN process. As a consequence, Ta diffusion through Cu surface may participate in strengthening the interface between the metal line and the IMD against EM line failure. As a conclusion, the mechanisms responsible for Ta detection at copper surface for CuSiN barriers are very complex; it is necessary to distinguish the diffusion of Ta to the Cu surface due to Si incorporation in Cu as shown using SiN capping, from specific mechanisms leading to additional Ta diffusion through Cu surface and non-regular voids formation. However, since fewer extrusions are obtained during EM tests when CuSiN process is incorporated, it can also be assumed that a stronger interface at the top of side walls, between TaN/Ta barrier, Cu and IMD is formed because of interactions between Cu, Si and Ta atoms. Additional experiments and characterizations are in progress to understand the mechanisms responsible for Ta diffusion towards the surface, in the general case of dielectric as capping layers on copper, and in the more
112
S. Chhun et al. / Microelectronic Engineering 76 (2004) 106–112
particular case of the CuSiN self-aligned barrier. However, Ta diffusion through Cu surface does not seem to be an issue, but on the opposite may participate in electrical and EM performances when CuSiN self-aligned barrier is integrated on copper.
Acknowledgement The authors would like to thank F. Pico (ST) from characterization group for FIB SEM observations.
References 4. Conclusion The crucial silicidation control of copper during SiH4 flow exposure to form CuSiN self-aligned barrier on copper was demonstrated. The barrier was integrated in a three metal level Cu–SiOC interconnect stack at metal two and excellent electrical performances in terms of line resistance and leakage current were obtained. Finally, the mechanisms responsible for tantalum diffusion to Cu surface observed after EM tests and its relation with Si incorporation in copper were investigated. As a consequence, CuSiN self-aligned barrier on copper is a promising technique either as a first step process before dielectric liners deposition to enhance reliability performances and as a standalone process to improve signal propagation performances for the 65 nm technology node and beyond.
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