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Lifetime estimation of analog circuits from the electrical characteristics of stressed MOSFETs
Microelectronics Reliability 47 (2007) 1349–1352 www.elsevier.com/locate/microrel
Lifetime estimation of analog circuits from the electrical characteristics of stressed MOSFETs J. Martı´n-Martı´nez a
a,*
, S. Gerardin b, R. Rodrı´guez a, M. Nafrı´a a, X. Aymerich a, A. Cester b, A. Paccagnella b, G. Ghidini c
Dept. Eng. Electro´nica, Universitat Auto´noma de Barcelona, Bellaterra, 08193 Barcelona, Spain b DEI Universita´ di Padova, via Gradenigo 6/B Padova, Italy c ST Microelectronics, via C. Olivetti 2, 20041 Agrate Brianza, Italy Received 18 July 2007 Available online 4 September 2007
Abstract In this work, the impact of dielectric degradation in the MOSFET electrical characteristics after different levels of Fowler-Nordheim (FN) stress has been studied. A decrease in ISAT and an increase of VT have been observed. The interface trap density has been extracted from the sub-threshold slope of ID–VGS curves. The results show a direct relation between the generated interfacial traps and the observed changes in saturation current and threshold voltage. The wear out effects in the devices have been extrapolated to operation voltages, pointing out that the transistors can fulfill the reliability criteria, even when working in analog applications. 2007 Elsevier Ltd. All rights reserved.
1. Introduction
2. Experimental
With the continuous scaling of MOSFET devices the gate oxide thickness has decreased drastically in the last years [1]. Unfortunately, some reliability problems appear due to this scaling, such as the degradation and dielectric breakdown (BD) of the gate oxide as a consequence of the higher electrical fields in the device. Several studies have been already presented about the gate reliability impact on the circuit performance, mostly on the impact of BD on digital circuits [2,3]. However, the degradation effects [4], which could be specially harmful in analog circuits, have been much less studied. In this work, the impact of electrical stress on NMOS transistors characteristics has been analyzed, and the interface trap generation due to the electrical stress has been studied. A reliability criterion for the devices has been defined when working in analog circuits. From the experimental data, an estimation of the circuit lifetime operating at operation voltages has been done.
The devices used in this work were NMOS transistors with SiON as gate dielectric (EOT = 2 lnm) and W/L = 0.3 lm/0.13 m. The transistors were electrically stressed during 10,000 s with different gate voltages (from 3.5 V to 4.1 V) and the other terminals grounded. The stress was stopped to measure the degraded ID–VDS, ID–VGS and IG–VGS curves, to analyze the effect of dielectric damage on the transistors characteristics as a function of stress time and stress voltage.
*
Corresponding author. Tel.: +34 93 581 3524; fax: +34 93 581 2600. E-mail address: [email protected] (J. Martı´n-Martı´nez).
0026-2714/$ - see front matter 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2007.07.088
3. Electrical characteristics of stressed MOSFETs The evolution of the saturation current (ISAT) and threshold voltage (VT) with the stress time has been analyzed, for different stress voltages. The relative variations of ISAT (DISAT/ISAT_FRESH) and VT (DVT/VT_FRESH) have been evaluated, where DISAT and DVT are the ISAT and VT variations, respectively, and ISAT_FRESH and VT_FRESH the corresponding values measured on the fresh (nonstressed) devices. The results show that the dielectric
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degradation leads to an ISAT decrease (Fig. 1a) and a VT increase (Fig. 1b). As expected, these effects are more evident for higher stress voltages. Note that the variation of both magnitudes takes place mainly during the first stages of the stress, showing a saturating behaviour afterwards. Concerning the gate current, Fig. 2 shows the IG–VGS curves measured at different stress times on a device. As can be observed in the figure, the oxide degradation has a negligible influence in the gate current. These results suggest that most of the degradation takes place at the SiON/ Si interface: charged traps near the interface have a small effect in the gate current, because they cannot assist the tunnel current through the gate dielectric, but they can affect the channel current. To study the relation between interfacial traps generation and the changes observed in Fig. 1, the variation of interface trap density (DDit) has been extracted from the sub-threshold slope in the ID–VGS characteristics, following the procedure described in [5]. Fig. 3 shows the evolution of DDit with the stress time for three stress voltages. As observed for DISAT and DVT, the trap generation rate is lar-
Fig. 2. IG–VGS curves of a fresh transistor and after a CVS stress of 5.600 s and 10.000 s (VGS = 3.9 V). No remarkable effects are observed in the gate current.
Fig. 3. Calculated interfacial trap density variation for several stress voltages. The trap generation increases with the stress voltage and the generation rate decreases with stress time.
Fig. 1. Relative variations of ISAT (a) and VT (b) as a function of the stress time for different stress voltages. The degradation is more evident for higher voltages. Degradation takes place mainly during the first stages of the stress.
ger during the first stages of the stress and decreases with the stress time. DISAT/ISAT_FRESH and DVT/VT_FRESH have been represented as a function of DDit (Fig. 4a and b). As can be observed, there exists a linear dependence between the changes in ISAT and VT and the interface traps. On the other hand, no dependence is observed with the stress voltage. The slopes of the linear fittings shown in Fig. 4 are very similar, so that we can conclude that the impact of Dit is approximately the same for ISAT and VT. These results seem to indicate that VT and ISAT variations are strongly related to the interfacial traps. The ISAT decrease could be due to two factors: (i) the VT increase provokes a reduction in ISAT and/or (ii) carriers in the channel would be affected by scattering processes with the interfacial trapped charge, leading to a mobility reduction, and therefore to a channel current decrease.
J. Martı´n-Martı´nez et al. / Microelectronics Reliability 47 (2007) 1349–1352
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Fig. 5. ISAT variation as a function of the stress voltage for different stress times.
DV T ¼ K VT expðbVT V stress Þ V T FRESH
Fig. 4. Relation between DDit and ISAT (a) and VT (b) relative variations. A linear dependence is observed in both cases.
ð2Þ
As in the case of Eq. (1), KVT and bVT are empirical parameters. To fit the data, constant KISAT and KVT values have been considered (KSAT = 2 · 108 and KVT = 3 · 107), independently of the stress time, so that the degradation time dependence is included in the bISAT and bVT parameters. Fig. 6 shows the bISAT and bVT evolution with the stress time. As can be observed in the figure, both parameters show a power-law dependence on time. For extrapolation purposes, Eq. (1) can be rewritten as aISAT ¼ bISAT V stress
ð3Þ
4. Extrapolation to operation voltages An extrapolation of the experimental data to estimate the ISAT and VT variations at operation voltages has been done. To do so, it has been taken into account that an exponential dependence between trap generation probability and stress voltage has been proved [6]. Then, since Fig. 4a shows a linear dependence between changes in ISAT and DDit, the ISAT variations could be described using Eq. (1) DI SAT ¼ K ISAT expðbISAT V stress Þ I SAT FRESH
ð1Þ
where KISAT and bISBAT are empirical fitting parameters. In Fig. 5 it is shown the relative ISAT variation as a function of the stress voltage for different stress times (symbols) and their fittings to Eq. (1) (lines). Also the relative variation of VT with the stress voltage has been described with an exponential law (Eq. (2)) and good fittings were obtained too (not shown here).
Fig. 6. Evolution with the stress time of bISAT and bVT. Both parameters can be described with a power-law.
J. Martı´n-Martı´nez et al. / Microelectronics Reliability 47 (2007) 1349–1352
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Note that a large increase in lifetime only leads to a small reduction of the maximum voltage, since the degradation of the devices takes place mainly at the beginning of the stress. For the considered times, all voltage values are far above from the usual operation voltages, and, therefore the analyzed devices satisfy all reliability targets. 5. Conclusions
Fig. 7. Dependence of aISAT on the stress voltage for several stress times. Inset: aISAT experimental values (dots) can be fitted to Eq. (3) (continuous lines). Table 1 Maximum operation voltage allowed to reach the failure criterion in ISAT or VT (1% variation) for different times ISAT failure VT failure
1 year
10 years
20 years
2.65 V 2.32 V
2.46 V 2.12 V
2.40 V 2.06 V
In this work the impact of dielectric degradation in nMOSFETs characteristics has been analyzed. The results show that the electrical stress degrades the ISAT and VT values. As expected, these effects are more important at higher stress voltages. The absence of SILC suggests that dielectric degradation takes place especially at the Si/SiON interface. This has been corroborated through the estimation of DDit, which shows that ISAT and VT are strongly related to the interfacial traps generated during the stress. The experimental data obtained at accelerated voltages has been extrapolated to operation conditions. Due to the observed decrease of the degradation rate with the stress time, the analyzed devices fulfilled our reliability criterion, even for analog applications, at least due to FN injection wear out. Acknowledgements
where aISAT
DI SAT =I SAT FRESH ¼ ln K ISAT
ð4Þ
aISAT is a figure of merit that takes into account the aISAT variation provoked by the dielectric wear out. Fig. 7 (inset) shows the aISAT linear dependence with the stress voltage, for different times, for the experimental data measured at high voltages (Fig. 1a). For lower operation voltages or larger operation times, a straight line has been plotted (Fig. 7), whose slope, bISAT, can be determined from the empirical law shown in Fig. 6. This graph can be used to estimate the lifetime of analog circuits whose performance depends on the ISAT value. Although a typical failure criterion could be a 10% change in ISAT [7], small variations in transistor characteristics lead to a large impact in analog circuit response, so that we have chosen a more restrictive failure criterion (1% decrease in ISAT). The dotted line indicates the aISAT value corresponding to our failure criterion. From the intersection of the dotted line with the straight continuous lines, the maximum allowed operation voltage for a given operation time can be calculated. In a similar way to aISAT, aVT has been defined to estimate the VT variations for operation conditions. Table 1 summarizes the values of the maximum voltages allowed for the analyzed devices for different failure times.
This work has been partially supported by the Spanish MCyT (TEC2004-00798/MIC) and the DURSI of the Generalitat de Catalunya (2005SGR-00061). References [1] International technology roadmap for semiconductor. Semiconductor industry association., Website:
Lifetime estimation of analog circuits from the electrical characteristics of stressed MOSFETs J. Martı´n-Martı´nez a
a,*
, S. Gerardin b, R. Rodrı´guez a, M. Nafrı´a a, X. Aymerich a, A. Cester b, A. Paccagnella b, G. Ghidini c
Dept. Eng. Electro´nica, Universitat Auto´noma de Barcelona, Bellaterra, 08193 Barcelona, Spain b DEI Universita´ di Padova, via Gradenigo 6/B Padova, Italy c ST Microelectronics, via C. Olivetti 2, 20041 Agrate Brianza, Italy Received 18 July 2007 Available online 4 September 2007
Abstract In this work, the impact of dielectric degradation in the MOSFET electrical characteristics after different levels of Fowler-Nordheim (FN) stress has been studied. A decrease in ISAT and an increase of VT have been observed. The interface trap density has been extracted from the sub-threshold slope of ID–VGS curves. The results show a direct relation between the generated interfacial traps and the observed changes in saturation current and threshold voltage. The wear out effects in the devices have been extrapolated to operation voltages, pointing out that the transistors can fulfill the reliability criteria, even when working in analog applications. 2007 Elsevier Ltd. All rights reserved.
1. Introduction
2. Experimental
With the continuous scaling of MOSFET devices the gate oxide thickness has decreased drastically in the last years [1]. Unfortunately, some reliability problems appear due to this scaling, such as the degradation and dielectric breakdown (BD) of the gate oxide as a consequence of the higher electrical fields in the device. Several studies have been already presented about the gate reliability impact on the circuit performance, mostly on the impact of BD on digital circuits [2,3]. However, the degradation effects [4], which could be specially harmful in analog circuits, have been much less studied. In this work, the impact of electrical stress on NMOS transistors characteristics has been analyzed, and the interface trap generation due to the electrical stress has been studied. A reliability criterion for the devices has been defined when working in analog circuits. From the experimental data, an estimation of the circuit lifetime operating at operation voltages has been done.
The devices used in this work were NMOS transistors with SiON as gate dielectric (EOT = 2 lnm) and W/L = 0.3 lm/0.13 m. The transistors were electrically stressed during 10,000 s with different gate voltages (from 3.5 V to 4.1 V) and the other terminals grounded. The stress was stopped to measure the degraded ID–VDS, ID–VGS and IG–VGS curves, to analyze the effect of dielectric damage on the transistors characteristics as a function of stress time and stress voltage.
*
Corresponding author. Tel.: +34 93 581 3524; fax: +34 93 581 2600. E-mail address: [email protected] (J. Martı´n-Martı´nez).
0026-2714/$ - see front matter 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2007.07.088
3. Electrical characteristics of stressed MOSFETs The evolution of the saturation current (ISAT) and threshold voltage (VT) with the stress time has been analyzed, for different stress voltages. The relative variations of ISAT (DISAT/ISAT_FRESH) and VT (DVT/VT_FRESH) have been evaluated, where DISAT and DVT are the ISAT and VT variations, respectively, and ISAT_FRESH and VT_FRESH the corresponding values measured on the fresh (nonstressed) devices. The results show that the dielectric
1350
J. Martı´n-Martı´nez et al. / Microelectronics Reliability 47 (2007) 1349–1352
degradation leads to an ISAT decrease (Fig. 1a) and a VT increase (Fig. 1b). As expected, these effects are more evident for higher stress voltages. Note that the variation of both magnitudes takes place mainly during the first stages of the stress, showing a saturating behaviour afterwards. Concerning the gate current, Fig. 2 shows the IG–VGS curves measured at different stress times on a device. As can be observed in the figure, the oxide degradation has a negligible influence in the gate current. These results suggest that most of the degradation takes place at the SiON/ Si interface: charged traps near the interface have a small effect in the gate current, because they cannot assist the tunnel current through the gate dielectric, but they can affect the channel current. To study the relation between interfacial traps generation and the changes observed in Fig. 1, the variation of interface trap density (DDit) has been extracted from the sub-threshold slope in the ID–VGS characteristics, following the procedure described in [5]. Fig. 3 shows the evolution of DDit with the stress time for three stress voltages. As observed for DISAT and DVT, the trap generation rate is lar-
Fig. 2. IG–VGS curves of a fresh transistor and after a CVS stress of 5.600 s and 10.000 s (VGS = 3.9 V). No remarkable effects are observed in the gate current.
Fig. 3. Calculated interfacial trap density variation for several stress voltages. The trap generation increases with the stress voltage and the generation rate decreases with stress time.
Fig. 1. Relative variations of ISAT (a) and VT (b) as a function of the stress time for different stress voltages. The degradation is more evident for higher voltages. Degradation takes place mainly during the first stages of the stress.
ger during the first stages of the stress and decreases with the stress time. DISAT/ISAT_FRESH and DVT/VT_FRESH have been represented as a function of DDit (Fig. 4a and b). As can be observed, there exists a linear dependence between the changes in ISAT and VT and the interface traps. On the other hand, no dependence is observed with the stress voltage. The slopes of the linear fittings shown in Fig. 4 are very similar, so that we can conclude that the impact of Dit is approximately the same for ISAT and VT. These results seem to indicate that VT and ISAT variations are strongly related to the interfacial traps. The ISAT decrease could be due to two factors: (i) the VT increase provokes a reduction in ISAT and/or (ii) carriers in the channel would be affected by scattering processes with the interfacial trapped charge, leading to a mobility reduction, and therefore to a channel current decrease.
J. Martı´n-Martı´nez et al. / Microelectronics Reliability 47 (2007) 1349–1352
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Fig. 5. ISAT variation as a function of the stress voltage for different stress times.
DV T ¼ K VT expðbVT V stress Þ V T FRESH
Fig. 4. Relation between DDit and ISAT (a) and VT (b) relative variations. A linear dependence is observed in both cases.
ð2Þ
As in the case of Eq. (1), KVT and bVT are empirical parameters. To fit the data, constant KISAT and KVT values have been considered (KSAT = 2 · 108 and KVT = 3 · 107), independently of the stress time, so that the degradation time dependence is included in the bISAT and bVT parameters. Fig. 6 shows the bISAT and bVT evolution with the stress time. As can be observed in the figure, both parameters show a power-law dependence on time. For extrapolation purposes, Eq. (1) can be rewritten as aISAT ¼ bISAT V stress
ð3Þ
4. Extrapolation to operation voltages An extrapolation of the experimental data to estimate the ISAT and VT variations at operation voltages has been done. To do so, it has been taken into account that an exponential dependence between trap generation probability and stress voltage has been proved [6]. Then, since Fig. 4a shows a linear dependence between changes in ISAT and DDit, the ISAT variations could be described using Eq. (1) DI SAT ¼ K ISAT expðbISAT V stress Þ I SAT FRESH
ð1Þ
where KISAT and bISBAT are empirical fitting parameters. In Fig. 5 it is shown the relative ISAT variation as a function of the stress voltage for different stress times (symbols) and their fittings to Eq. (1) (lines). Also the relative variation of VT with the stress voltage has been described with an exponential law (Eq. (2)) and good fittings were obtained too (not shown here).
Fig. 6. Evolution with the stress time of bISAT and bVT. Both parameters can be described with a power-law.
J. Martı´n-Martı´nez et al. / Microelectronics Reliability 47 (2007) 1349–1352
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Note that a large increase in lifetime only leads to a small reduction of the maximum voltage, since the degradation of the devices takes place mainly at the beginning of the stress. For the considered times, all voltage values are far above from the usual operation voltages, and, therefore the analyzed devices satisfy all reliability targets. 5. Conclusions
Fig. 7. Dependence of aISAT on the stress voltage for several stress times. Inset: aISAT experimental values (dots) can be fitted to Eq. (3) (continuous lines). Table 1 Maximum operation voltage allowed to reach the failure criterion in ISAT or VT (1% variation) for different times ISAT failure VT failure
1 year
10 years
20 years
2.65 V 2.32 V
2.46 V 2.12 V
2.40 V 2.06 V
In this work the impact of dielectric degradation in nMOSFETs characteristics has been analyzed. The results show that the electrical stress degrades the ISAT and VT values. As expected, these effects are more important at higher stress voltages. The absence of SILC suggests that dielectric degradation takes place especially at the Si/SiON interface. This has been corroborated through the estimation of DDit, which shows that ISAT and VT are strongly related to the interfacial traps generated during the stress. The experimental data obtained at accelerated voltages has been extrapolated to operation conditions. Due to the observed decrease of the degradation rate with the stress time, the analyzed devices fulfilled our reliability criterion, even for analog applications, at least due to FN injection wear out. Acknowledgements
where aISAT
DI SAT =I SAT FRESH ¼ ln K ISAT
ð4Þ
aISAT is a figure of merit that takes into account the aISAT variation provoked by the dielectric wear out. Fig. 7 (inset) shows the aISAT linear dependence with the stress voltage, for different times, for the experimental data measured at high voltages (Fig. 1a). For lower operation voltages or larger operation times, a straight line has been plotted (Fig. 7), whose slope, bISAT, can be determined from the empirical law shown in Fig. 6. This graph can be used to estimate the lifetime of analog circuits whose performance depends on the ISAT value. Although a typical failure criterion could be a 10% change in ISAT [7], small variations in transistor characteristics lead to a large impact in analog circuit response, so that we have chosen a more restrictive failure criterion (1% decrease in ISAT). The dotted line indicates the aISAT value corresponding to our failure criterion. From the intersection of the dotted line with the straight continuous lines, the maximum allowed operation voltage for a given operation time can be calculated. In a similar way to aISAT, aVT has been defined to estimate the VT variations for operation conditions. Table 1 summarizes the values of the maximum voltages allowed for the analyzed devices for different failure times.
This work has been partially supported by the Spanish MCyT (TEC2004-00798/MIC) and the DURSI of the Generalitat de Catalunya (2005SGR-00061). References [1] International technology roadmap for semiconductor. Semiconductor industry association., Website: