- Email: [email protected]
Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors
Nuclear Instruments and Methods in Physics Research A xx (xxxx) xxxx–xxxx
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors ⁎
Huiming Zeng, Tingcun Wei , Jia Wang School of Computer Science and Engineering, Northwestern Polytechnical University, Xi'an 710072, PR China
A R T I C L E I N F O
A BS T RAC T
Keywords: CdZnTe detector Front-end readout ASIC The linearity of conversion gain High-Z circuit
A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide– semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 µm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e−+16.3e−/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of < 0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is < 0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.
1. Introduction Cadmium zinc telluride (CdZnTe) semiconductors have been regarded as promising materials for constructing X-ray and gamma ray detectors for their superior characteristics in different application areas, such as medical and industrial inspection, homeland security, and space exploration [1]. First, compared to NaI or CsI crystals scintillation and photomultiplier tube (PMT) detectors, CdZnTe detector has these advantages: (1) higher energy resolution and sensitivity because the photons incident to the CdZnTe detector efficiently generate carriers (electrons and holes) in the semiconductor material and (2) higher spatial resolution because of its smaller pixel size. Second, compared to other semiconductor detectors, such as germanium and silicon detectors, the large band gap energy and resultant low-leakage current allows the CdZnTe detector to operate at room temperature. Front-end readout application-specific integrated circuits (ASICs) are used to amplify and process the weak output signal of the CdZnTe detector. The architecture and performances of the readout ASICs for CdZnTe detectors are determined according to the application that generally has specific input energy range, counting rate, and main
⁎
electric (input capacitance and leakage current) detector features [2]. For multichannel imaging applications, the performances of noise, linearity, power consumption, and chip size should be carefully considered in the design of readout ASICs. The low-noise property of readout ASIC is beneficial to the signal-to-noise ratio and the energy resolution of systems. For the given voltage dynamic range of the frontend readout circuit, the higher the linearity, the more incident events can be detected without losing the true signals. Therefore, the good linearity of readout ASIC can improve the energy resolution and energy range of systems. In addition, low-power consumption and small chip size are required for multichannel readout ASICs. Multichannel front-end readout ASICs for CdZnTe detector have been researched and developed considerably in the recent years. In references [3–5], a series of front-end readout ASICs were developed using a 0.35 µm complementary MOS (CMOS) process consisting of a charge-sensitive amplifier, a slow and fast CR-RC shaper, a comparator, and a sample-and-hold circuit, and a typical noise level of 130 e− at 0 pF input capacitance was obtained with a nonlinearity of 5% and a power consumption of 4.125 mW per channel. In references [6,7], a low-noise 32-channel front-end readout ASIC was developed using a 0.35 µm CMOS process; it had a similar circuit architecture as in [3–5]
Corresponding author. E-mail address: [email protected] (T. Wei).
http://dx.doi.org/10.1016/j.nima.2016.11.045 Received 30 June 2016; Received in revised form 31 October 2016; Accepted 21 November 2016 Available online xxxx 0168-9002/ © 2016 Elsevier B.V. All rights reserved.
Please cite this article as: Zeng, H., Nuclear Instruments and Methods in Physics Research A (2016), http://dx.doi.org/10.1016/j.nima.2016.11.045
Nuclear Instruments and Methods in Physics Research A xx (xxxx) xxxx–xxxx
H. Zeng et al.
and achieved a noise level of 39.5 e− at 0 pF input capacitance, but its nonlinearity is as high as 7.5%. In references [8–10], a 36-channel front-end readout ASIC named as RENA-3 was reported; it had a similar circuit architecture as in [3–7] and achieved a noise level of 112 e− at 0 pF input capacitance and a nonlinearity of 10% with a power consumption of 6 mW per channel. The preamplifier gain and the slow shaper shaping time can be adjusted to increase the input energy range. Front-end readout ASICs for CdZnTe detectors have been developed with the focus on low noise, chip size, and power consumption improvements, and not on the linearity performance. Focus was turned to the linearity enhancement design of front-end readout ASIC for CdZnTe detectors in this work without degrading the performances of noise, power consumption, and chip size. A 16-channel front-end readout ASIC with high linearity and low noise is designed and implemented in this paper for use in a multichannel imaging system based on CdZnTe detectors. First, the architecture of the front-end readout ASIC and the circuit topology of one channel are presented. Subsequently, noise reduction is analyzed. The linearity enhancement design follows. Finally, the implementation and test results of the prototype chip are presented.
are sampled and held by a peak detector and are finally outputted in sequence via an analog buffer. The resistors in the slow shaper are realized using a high-impedance (high-Z) circuit to obtain a constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor. Thus, the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved. For the time measurement chain, a discriminator following the fast shaper is used to obtain trigger signals. A monostable circuit is applied to generate the peak-detecting pulse, the width of which is adjusted to match the peaking time of the slow shaper. Thus, the peak values of the voltage signals are correctly sampled and held. To achieve the high linearity of conversion gain in this paper, the resistors illustrated in Fig. 2 as High-Z0 to High-Z3 are all realized by the same high-Z circuits but with different sizes of CMOS transistors instead of only a MOS transistor as practiced. The detailed linearity improvement analysis is provided in Section 4.
2. Architecture of the front-end readout ASIC
Noise optimization technologies include the size matching of input CMOS transistors, optimization of slow shaper (shaping time), layout design, and so on [13]. The noise model for the CdZnTe detector and preamplifier is shown in Fig. 3, where Cin is the sum of the detector (Cd) and parasitic capacitances at the input node of the preamplifier; v2ia and i2ia represent the equivalent input noise voltage and noise current, respectively; and i2d is the current noise caused by the detector leakage current. Supposing I0 is the detector leakage current and the total equivalent capacitance at input could be expressed as Cin’, gm1 is the transconductance of the input MOS transistor of the preamplifier and i2ia, v2ia, and i2d can be expressed as (3-1), (3-2), and (3-3), respectively. The total equivalent input noise voltage in the series, v2eqi, can be calculated as (3−4).
3. Noise optimization
The architecture of the multichannel front-end readout ASIC for CdZnTe detectors is shown in Fig. 1. Each channel includes a gainadjustable preamplifier; an energy measurement chain consisting of a pole-zero cancellation circuit, a slow shaper, and a peak detector; and a time measurement chain consisting of a fast shaper, a discriminator, and a digital buffer. The energy measurement chains of all channels share a common analog buffer via a multiplexer, and the output voltages are sent to an analog to digital converter (ADC) for digitalization [11]. The timing controller generates the timing signals at which the peak voltages of multichannels are captured in a pipelined sequence. When an X-ray or gamma ray radiation event occurs, a trigger signal is generated by the time measurement chain, and then the timing information of the trigger signal is digitalized by a time to digital converter (TDC) [12]. Both the energy and time information are sent to the DSP for further data processing. Finally, the information is used for image reconstruction. The detailed circuit topology for one channel is shown in Fig. 2. A charge-sensitive amplifier (CSA) is used as the preamplifier to convert the charge from CdZnTe detector to voltage signal, the conversion gain of which can be adjusted by trimming the integrating capacitance Cf of CSA, therefore achieving gain uniformity among all channels easily. For the energy measurement chain, a pole-zero cancellation (PZC) circuit is inserted behind the preamplifier to cancel the CSA pole and thus eliminate the undershoot of the output of the fast shaper and allow for a faster counting rate. Then, a CR-RC slow shaper is used as an active bandpass filter to decrease the noise. The peak values of voltage signals
iia2 = jwCin 2 via2 v 2ia ≈
Kf 2 Cox WLf
id2 = 2qI0 +
2 = veqi
(3-1)
+
8 1 kT 3 gm1
4KT Rf
Cin ′ + Cf + Cin
(3-2)
(3-3) 2
Cf
via2
(3−4)
Assuming that the value of the feedback resistor Rf of the CSA is almost infinite, i2d can be simplified as (3−5).
Fig. 1. Architecture of multichannel front-end readout ASIC.
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Fig. 2. Circuit topology for one channel.
convert the charge from CdZnTe detector to voltage signal, and the conversion gain of which can be adjusted by trimming the integrating capacitance Cf. The CSA core is a cascode folded amplifier, which provides high charge-to-voltage conversion gain and large bandwidth. The size of the input PMOS transistor is optimized for minimal 1/f noise with W/L=800 µm/0.5 µm for the detector capacitance of 1 pF. 4. Linearity improvement For the energy measurement chain, if the shaping time of the slow shaper is varied for different amounts of input energies, the linearity of the conversion gain is seriously degraded because the peak detector could not always sample and hold the peak values of the voltage signals in this case. Therefore, to obtain a good linearity of conversion gain, the shaping time of the slow shaper should be kept as constant as possible for different amounts of input energies. In the CR-RC slow shaper, the shaping time is decided by integral and differential time constants. Fig. 5 shows the typical structure of a CR-RC slow shaper, where C0R0 is the differential time constant, C1R1 is the integral time constant, and ts=C0R0=C1R1 is the shaping time (ts) of the slow shaper. In traditional CR-RC slow shapers [3,7,10,16], a single MOS transistor operating at the linear region is usually used as the resistor; the equivalent resistance value of which can be adjusted by changing its gate voltage. However, the shaping time of the slow shaper varies because the equivalent resistance of a single MOS transistor is not constant for different amounts of input energies. Thus, the linearity of conversion gain is seriously degraded. The capacitors in the CR-RC slow shapers are usually realized by the poly–poly capacitor or metal– insulator–metal (MIM) capacitor, which have almost constant capacitances. In this paper, to achieve the high linearity of conversion gain, the resistors in the slow shaper are realized using a high-Z circuit [3–5] instead of a MOS transistor; the schematic of which is shown in Fig. 6. The high-Z circuit is actually a differential amplifier with low gm input transistors and is connected as a buffer when used as a resistor. The equivalent resistance (Re) of the high-Z circuit is nearly constant for large input/output voltage ranges when used as a resistor and can be approximately expressed as Re=m×n(Vin1 – Vin2)/Iout, where m and n are the size ratios between the CMOS transistors and Iout is the static current at the output as illustrated in Fig. 6. In the prototype chip design, the High-Z0–High-Z3 shown in Fig. 2 are all realized using the same circuit structure shown in Fig. 6 but with
Fig. 3. Noise model for detector and preamplifier.
id2 = 2qI0 +
4KT ≈ 2qI0 Rf
(3−5)
Furthermore, the output noise voltage, (3−6). 2 voA (s ) =
Cin ′ + Cf + Cin Cf + 2qI0
1 sCf
2
Kf 2 Cox WLf
+
v2 oA,
could be derived as
Cin ′ + Cf + Cin Cf
2
8 1 kT 3 gm1
2
(3−6)
In (3−6), W and L are the width and length of the input MOS transistors of the preamplifier; the first, second, and last terms represent the 1/f noise of the input MOS transistor [14,15], the channel thermal noise, and the shot noise, respectively. The main factors affecting the noise property are the detector capacitance Cd, integrating capacitor Cf, parameters (W, L, and gm1) of the input MOS transistor, and technology specifications (Kf and Cox). Therefore, the optimal design of the preamplifier is most important for the front-end readout circuit. The width and length of the input MOS transistor are the key points for the given CMOS manufacturing technology. The schematic of the preamplifier is shown in Fig. 4. In this design, a charge-sensitive amplifier (CSA) is adopted for the preamplifier to
Fig. 4. Schematic of CSA.
Fig. 5. Typical structure of CR-RC slow shaper.
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Fig. 6. Schematic of a high-Z circuit.
Fig. 9. ENC with different input load capacitances.
Fig. 7. Simulation results of shaping time deviation.
Fig. 10. Measured results of the conversion gain and linearity.
Fig. 8. Photograph of the prototype chip and the test system.
different m and n size ratios. To confirm the effects using the high-Z circuit, the shaping times of the slow shaper for different amounts of input energies when using a high-Z circuit and a single MOS transistor as resistors are simulated by the Cadence Spectre. The simulation results of the shaping time deviation for the desired shaping time of 1 μs within the input charge range of 11.5 fC to 22.5 fC is shown in Fig. 7. The shaping time is more stable when using a high-Z circuit than when using a single MOS transistor. As a result, the linearity of conversion gain in this design can be improved because of the constant shaping time of the slow shaper.
Fig. 11. Measured time walk with input charge.
5. Implementation and test The prototype chip of a 16-channel front-end readout ASIC was 4
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caused by the chip package on noise performances, the ASIC was directly bonded on the PCB by the chip-on-board package technology. The measured equivalent noise charges (ENCs) for the different input load capacitances is shown in Fig. 9. For a typical channel, the measured ENC is 109.7 e− at 0 F plus 16.3 e− per picofarad with a power consumption of 4 mW per channel. 5.2. Gain and linearity Fig. 10 shows the relationship between the peak value of the output voltage and the input charge for a typical channel. A conversion gain of 87 mV/fC and a nonlinearity error of < 0.4% were achieved. Compared with the traditional approaches [3,7,10,16], the linearity of conversion gain achieved in this work was improved by at least 86.6% using a similar architecture as the front-end readout and manufacture process. 5.3. Time walk The measured time walk for a typical channel within the input charge range of 11.5 fC to 22.5 fC for gamma ray imaging is shown in Fig. 11[17,18]. The maximum time walk was < 4 ns. The time walk decreased with the increase of the input charge because the rising edges of the fast shaper became steeper when the input charge increased.
Fig. 12. Measured consistency among 16 channels.
5.4. Consistency among the channels In the prototype chip design, the analog circuits were separate from the digital circuits to reduce system noise and interference, and the guard rings and dummy units were added in the sensitive circuits and transistors. Consistency was degraded because of the influence of parasitic capacitances and the little differences in power supplies and bias voltages among the 16 channels. The measured consistency among the 16 channels is shown in Fig. 12 and the maximum error was 0.3%. 5.5. Energy spectrum test
Fig. 13. Measured energy spectrum using the
241
The energy spectrum test was completed by combining the ASIC with a 5 mm×5 mm×2 mm CdZnTe detector; 241Am radioactive source was used, and a high-bias voltage of −450 V was added at the CdZnTe detector. The measured energy spectrum is shown in Fig. 13, and an energy resolution of 2.975 keV (FWHM) for 241Am of 59.5 keV was obtained. Moreover, the crosstalk between channels was < 2%. Table 1 provides a comparison of the main performances of the readout ASIC and some similar works. Compared with the traditional approaches, the readout ASIC designed and implemented in this work has achieved outstanding linearity performance without compromising the performances of noise, power consumption, and chip size. The performances of the ASIC developed in this work can satisfy the requirements of the CdZnTe detector imaging system.
Am radioactive source.
implemented using a commercial 0.35 µm CMOS process with a chip size of 2.60 mm×3.53 mm. The photograph of the prototype chip and the test system are shown in Fig. 8. The experimental conditions were set as follows. The power supply of the prototype chip was 3.3 V, the integrating capacitor of CSA was 60 fF (EN0=1 and EN1=1), the shaping time of the slow shaper was about 1 μs in which the best noise performances can be obtained, and all experiments were carried out at room temperature.
6. Conclusion 5.1. Noise performances A linearity enhancement design of the 16-channel frond-end readout ASIC chip for CdZnTe detectors is presented. The resistors in the
To eliminate the effects of the parasitic capacitances and resistances Table 1 Comparison of the main performances of readout ASICs. Performances
This work
Ref [3]
Ref [7]
Ref [10]
Ref [16]
Technology Channel numbers Noise@0 pF Gain nonlinearity Chip size (mm2) Power Con.
0.35 µm CMOS 16 109.7 e− < 0.4% 2.60×3.53 4 mW/Ch
0.35 µm CMOS 8 130 e− 5% 2.95×2.95 4.125 mW/Ch
0.35 µm CMOS 32 39.5 e− 7.5% 5×5 2 mW/Ch
0.35 µm CMOS 36 150 e− 10% 6.905×6.380 6 mW/Ch
0.35 µm CMOS 8 86.5 e− < 3% 2.286×2.282 3 mW/Ch
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[5] Tetsuichi Kishidhita, Goro Sato, Hirokazu Ikeda, Tadayuki Takahashi, Tatsuya Kiyuna, Yoshio Mito, Low-noise analog ASIC for silicon and CdTe sensors, IEEE Trans. Nucl. Sci. 57 (5) (2010) 2971–2977. [6] VA32TA6 Documentation, 〈http://www.ideas.no/〉. [7] Hiroyasu Tajima, Tatsuya Nakamoto, Takaaki Tanaka, et al., Performance of a low noise front-end ASIC for Si/CdTe detectors in compton gamma-ray telescope”, IEEE Trans. Nucl. Sci. 51 (3) (2004) 842–847. [8] RENA-3TM IC User Specifications, 〈http://novarad.com〉. [9] T.Tumer, V.Cajipe, M.Clajus, etc. Multi-Channel Front0end readout IC for position sensitive solid-state detectors, IEEE Nuclear Science Symposium Conference Record, N14-91, pp. 384–388, 2006. [10] V.Cajipe, M.Clajus, S.Hayakawa, etc.Performance of the RENA-3 IC with position sensitive CZT and CaTe Detectors, IEEE Nuclear Science Symposium Conference Record, R12-56, pp. 300–307, 2008. [11] Wu Gao, Deyuan Gao, Christine Hu-Guo, Tingcun Wei, Y. Hu, Design and characteristics of an integrated multichannel ramp ADC using digital DLL techniques for small animal PET imaging, IEEE Trans. Nucl. Sci. 58 (5) (2011) 2161–2168. [12] X.C. Fang, W. Gao, Ch Hu-Guo, D. Brasse, B. Humbert, Y. Hu, Design of a lownoise front-end readout chip integrated with a high-resolution TDC for APD-based small-animal PET imaging, IEEE Trans. Nucl. Sci. 58 (2) (2011) 370–377. [13] Zhongyuan Chang, Willy M.C. Sansen, low-noise, low-distortion CMOS AM wideband amplifiers matching a capacitive source, IEEE J. Solid-State Circuit 25 (3) (1990) 833–840. [14] W. Sasen, Integrated low noise amplifiers in CMOS technology, Nucl. Instrum. Methods Phys. Res. A 253 (1987) 427–433. [15] Z.Y.Chang, W.Sasen, Test structure for evaluation of 1/f noise in CMOS technologies, in: Proceedings of the ISCAS’89, pp. 143–146, 1989. [16] W.Gao, H.Liu, D.Gao, etc. SENSROC4: An multichannel low-noise front-end readout ASIC dedicated to CZT detectors for PET imaging, Proceedings of the 3rd International Conference on ANIMMA, pp. 1–6, June, 2013. [17] Y.Yin, S.Komarov, H.Wu, T.Song, Y.Tai, etc. Characterization of highly CdZnTe detectors for sub-millimeter PET imaging, IEE Nuclear Science Symposium Conference Record, J05-4, pp. 2411–2414, 2009. [18] Jose-Gabriel,, M. Macias-Montero, M.Chmeissani, etc. VIP-PIX: a Low Noise readout ASIC for pixelated CdTe gamma-ray detectors for use in the next generation of PET scanners, IEEE Nuclear Science Symposium and Medical Imaging Conference Record, N16-3, pp. 1452–1459, 2012. [19] W. Liu, T. Wei, L. Yang, Y. Hu, A 12-bit, 1 MS/s SAR-ADC for a CZT-based multichannel gamma-ray imager using a new digital calibration method (P03018)J. Instrum. 11 (3) (2016) 1–17.
slow shaper are realized using a high-Z circuit to obtain a constant resistance value instead of using only a MOS transistor. Thus, the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is significantly improved. The readout ASIC is designed and fabricated in 0.35 µm CMOS process with a die size of 2.6 mm×3.53 mm. The measurement results show that the nonlinearity of conversion gain is < 0.4%, which shows an improvement of at least 86.6% from the traditional approaches using a similar architecture of front-end readout and manufacture process. The front-end readout ASIC developed in this work has an outstanding linearity performance while maintaining the same level of noise, power consumption, and chip size performances. A 12-bit SAR-ADC [19] and a TDC will be integrated with this ASIC on one chip for the applications of CdZnTe detectors in future works. Acknowledgments This work was supported by the National Key Scientific Instrument and Equipment Development Project of China under Grant No. 2011YQ040082. References [1] R.Amrami, G.Shani, Y.Hefetz, etc. PET properties of pixelated CdZnTe detector, in: Proceedings of the 22nd Annual EMBS International Conference, pp. 94–97, 2000 [2] P.Vaska, A.Bolotnikov, G.Carini, G.Camarda, etc. Studies of CZT for PET applications, IEEE Nuclear Science Symposium Conference Record, J03-1, pp. 2799– 2802, 2005. [3] T.Kishishita, H.Ikeda, T.Kiyuna, K.Tamura, etc. Development of a Low-Noise Analog Front-end ASIC for CdTe Detectors, IEEE Nuclear Science Symposium Conference Record, N35-4, pp. 1992–1996, 2007. [4] Ken-ichi Tamura, Tatsuro Hiruta, Hirokazu Ikeda, Hokuto Inoue, Development of ASICs for CdTe pixel and line sensors, IEEE Trans. Nucl. Sci. 52 (5) (2005) 2023–2029.
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Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors ⁎
Huiming Zeng, Tingcun Wei , Jia Wang School of Computer Science and Engineering, Northwestern Polytechnical University, Xi'an 710072, PR China
A R T I C L E I N F O
A BS T RAC T
Keywords: CdZnTe detector Front-end readout ASIC The linearity of conversion gain High-Z circuit
A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide– semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 µm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e−+16.3e−/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of < 0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is < 0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.
1. Introduction Cadmium zinc telluride (CdZnTe) semiconductors have been regarded as promising materials for constructing X-ray and gamma ray detectors for their superior characteristics in different application areas, such as medical and industrial inspection, homeland security, and space exploration [1]. First, compared to NaI or CsI crystals scintillation and photomultiplier tube (PMT) detectors, CdZnTe detector has these advantages: (1) higher energy resolution and sensitivity because the photons incident to the CdZnTe detector efficiently generate carriers (electrons and holes) in the semiconductor material and (2) higher spatial resolution because of its smaller pixel size. Second, compared to other semiconductor detectors, such as germanium and silicon detectors, the large band gap energy and resultant low-leakage current allows the CdZnTe detector to operate at room temperature. Front-end readout application-specific integrated circuits (ASICs) are used to amplify and process the weak output signal of the CdZnTe detector. The architecture and performances of the readout ASICs for CdZnTe detectors are determined according to the application that generally has specific input energy range, counting rate, and main
⁎
electric (input capacitance and leakage current) detector features [2]. For multichannel imaging applications, the performances of noise, linearity, power consumption, and chip size should be carefully considered in the design of readout ASICs. The low-noise property of readout ASIC is beneficial to the signal-to-noise ratio and the energy resolution of systems. For the given voltage dynamic range of the frontend readout circuit, the higher the linearity, the more incident events can be detected without losing the true signals. Therefore, the good linearity of readout ASIC can improve the energy resolution and energy range of systems. In addition, low-power consumption and small chip size are required for multichannel readout ASICs. Multichannel front-end readout ASICs for CdZnTe detector have been researched and developed considerably in the recent years. In references [3–5], a series of front-end readout ASICs were developed using a 0.35 µm complementary MOS (CMOS) process consisting of a charge-sensitive amplifier, a slow and fast CR-RC shaper, a comparator, and a sample-and-hold circuit, and a typical noise level of 130 e− at 0 pF input capacitance was obtained with a nonlinearity of 5% and a power consumption of 4.125 mW per channel. In references [6,7], a low-noise 32-channel front-end readout ASIC was developed using a 0.35 µm CMOS process; it had a similar circuit architecture as in [3–5]
Corresponding author. E-mail address: [email protected] (T. Wei).
http://dx.doi.org/10.1016/j.nima.2016.11.045 Received 30 June 2016; Received in revised form 31 October 2016; Accepted 21 November 2016 Available online xxxx 0168-9002/ © 2016 Elsevier B.V. All rights reserved.
Please cite this article as: Zeng, H., Nuclear Instruments and Methods in Physics Research A (2016), http://dx.doi.org/10.1016/j.nima.2016.11.045
Nuclear Instruments and Methods in Physics Research A xx (xxxx) xxxx–xxxx
H. Zeng et al.
and achieved a noise level of 39.5 e− at 0 pF input capacitance, but its nonlinearity is as high as 7.5%. In references [8–10], a 36-channel front-end readout ASIC named as RENA-3 was reported; it had a similar circuit architecture as in [3–7] and achieved a noise level of 112 e− at 0 pF input capacitance and a nonlinearity of 10% with a power consumption of 6 mW per channel. The preamplifier gain and the slow shaper shaping time can be adjusted to increase the input energy range. Front-end readout ASICs for CdZnTe detectors have been developed with the focus on low noise, chip size, and power consumption improvements, and not on the linearity performance. Focus was turned to the linearity enhancement design of front-end readout ASIC for CdZnTe detectors in this work without degrading the performances of noise, power consumption, and chip size. A 16-channel front-end readout ASIC with high linearity and low noise is designed and implemented in this paper for use in a multichannel imaging system based on CdZnTe detectors. First, the architecture of the front-end readout ASIC and the circuit topology of one channel are presented. Subsequently, noise reduction is analyzed. The linearity enhancement design follows. Finally, the implementation and test results of the prototype chip are presented.
are sampled and held by a peak detector and are finally outputted in sequence via an analog buffer. The resistors in the slow shaper are realized using a high-impedance (high-Z) circuit to obtain a constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor. Thus, the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved. For the time measurement chain, a discriminator following the fast shaper is used to obtain trigger signals. A monostable circuit is applied to generate the peak-detecting pulse, the width of which is adjusted to match the peaking time of the slow shaper. Thus, the peak values of the voltage signals are correctly sampled and held. To achieve the high linearity of conversion gain in this paper, the resistors illustrated in Fig. 2 as High-Z0 to High-Z3 are all realized by the same high-Z circuits but with different sizes of CMOS transistors instead of only a MOS transistor as practiced. The detailed linearity improvement analysis is provided in Section 4.
2. Architecture of the front-end readout ASIC
Noise optimization technologies include the size matching of input CMOS transistors, optimization of slow shaper (shaping time), layout design, and so on [13]. The noise model for the CdZnTe detector and preamplifier is shown in Fig. 3, where Cin is the sum of the detector (Cd) and parasitic capacitances at the input node of the preamplifier; v2ia and i2ia represent the equivalent input noise voltage and noise current, respectively; and i2d is the current noise caused by the detector leakage current. Supposing I0 is the detector leakage current and the total equivalent capacitance at input could be expressed as Cin’, gm1 is the transconductance of the input MOS transistor of the preamplifier and i2ia, v2ia, and i2d can be expressed as (3-1), (3-2), and (3-3), respectively. The total equivalent input noise voltage in the series, v2eqi, can be calculated as (3−4).
3. Noise optimization
The architecture of the multichannel front-end readout ASIC for CdZnTe detectors is shown in Fig. 1. Each channel includes a gainadjustable preamplifier; an energy measurement chain consisting of a pole-zero cancellation circuit, a slow shaper, and a peak detector; and a time measurement chain consisting of a fast shaper, a discriminator, and a digital buffer. The energy measurement chains of all channels share a common analog buffer via a multiplexer, and the output voltages are sent to an analog to digital converter (ADC) for digitalization [11]. The timing controller generates the timing signals at which the peak voltages of multichannels are captured in a pipelined sequence. When an X-ray or gamma ray radiation event occurs, a trigger signal is generated by the time measurement chain, and then the timing information of the trigger signal is digitalized by a time to digital converter (TDC) [12]. Both the energy and time information are sent to the DSP for further data processing. Finally, the information is used for image reconstruction. The detailed circuit topology for one channel is shown in Fig. 2. A charge-sensitive amplifier (CSA) is used as the preamplifier to convert the charge from CdZnTe detector to voltage signal, the conversion gain of which can be adjusted by trimming the integrating capacitance Cf of CSA, therefore achieving gain uniformity among all channels easily. For the energy measurement chain, a pole-zero cancellation (PZC) circuit is inserted behind the preamplifier to cancel the CSA pole and thus eliminate the undershoot of the output of the fast shaper and allow for a faster counting rate. Then, a CR-RC slow shaper is used as an active bandpass filter to decrease the noise. The peak values of voltage signals
iia2 = jwCin 2 via2 v 2ia ≈
Kf 2 Cox WLf
id2 = 2qI0 +
2 = veqi
(3-1)
+
8 1 kT 3 gm1
4KT Rf
Cin ′ + Cf + Cin
(3-2)
(3-3) 2
Cf
via2
(3−4)
Assuming that the value of the feedback resistor Rf of the CSA is almost infinite, i2d can be simplified as (3−5).
Fig. 1. Architecture of multichannel front-end readout ASIC.
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Fig. 2. Circuit topology for one channel.
convert the charge from CdZnTe detector to voltage signal, and the conversion gain of which can be adjusted by trimming the integrating capacitance Cf. The CSA core is a cascode folded amplifier, which provides high charge-to-voltage conversion gain and large bandwidth. The size of the input PMOS transistor is optimized for minimal 1/f noise with W/L=800 µm/0.5 µm for the detector capacitance of 1 pF. 4. Linearity improvement For the energy measurement chain, if the shaping time of the slow shaper is varied for different amounts of input energies, the linearity of the conversion gain is seriously degraded because the peak detector could not always sample and hold the peak values of the voltage signals in this case. Therefore, to obtain a good linearity of conversion gain, the shaping time of the slow shaper should be kept as constant as possible for different amounts of input energies. In the CR-RC slow shaper, the shaping time is decided by integral and differential time constants. Fig. 5 shows the typical structure of a CR-RC slow shaper, where C0R0 is the differential time constant, C1R1 is the integral time constant, and ts=C0R0=C1R1 is the shaping time (ts) of the slow shaper. In traditional CR-RC slow shapers [3,7,10,16], a single MOS transistor operating at the linear region is usually used as the resistor; the equivalent resistance value of which can be adjusted by changing its gate voltage. However, the shaping time of the slow shaper varies because the equivalent resistance of a single MOS transistor is not constant for different amounts of input energies. Thus, the linearity of conversion gain is seriously degraded. The capacitors in the CR-RC slow shapers are usually realized by the poly–poly capacitor or metal– insulator–metal (MIM) capacitor, which have almost constant capacitances. In this paper, to achieve the high linearity of conversion gain, the resistors in the slow shaper are realized using a high-Z circuit [3–5] instead of a MOS transistor; the schematic of which is shown in Fig. 6. The high-Z circuit is actually a differential amplifier with low gm input transistors and is connected as a buffer when used as a resistor. The equivalent resistance (Re) of the high-Z circuit is nearly constant for large input/output voltage ranges when used as a resistor and can be approximately expressed as Re=m×n(Vin1 – Vin2)/Iout, where m and n are the size ratios between the CMOS transistors and Iout is the static current at the output as illustrated in Fig. 6. In the prototype chip design, the High-Z0–High-Z3 shown in Fig. 2 are all realized using the same circuit structure shown in Fig. 6 but with
Fig. 3. Noise model for detector and preamplifier.
id2 = 2qI0 +
4KT ≈ 2qI0 Rf
(3−5)
Furthermore, the output noise voltage, (3−6). 2 voA (s ) =
Cin ′ + Cf + Cin Cf + 2qI0
1 sCf
2
Kf 2 Cox WLf
+
v2 oA,
could be derived as
Cin ′ + Cf + Cin Cf
2
8 1 kT 3 gm1
2
(3−6)
In (3−6), W and L are the width and length of the input MOS transistors of the preamplifier; the first, second, and last terms represent the 1/f noise of the input MOS transistor [14,15], the channel thermal noise, and the shot noise, respectively. The main factors affecting the noise property are the detector capacitance Cd, integrating capacitor Cf, parameters (W, L, and gm1) of the input MOS transistor, and technology specifications (Kf and Cox). Therefore, the optimal design of the preamplifier is most important for the front-end readout circuit. The width and length of the input MOS transistor are the key points for the given CMOS manufacturing technology. The schematic of the preamplifier is shown in Fig. 4. In this design, a charge-sensitive amplifier (CSA) is adopted for the preamplifier to
Fig. 4. Schematic of CSA.
Fig. 5. Typical structure of CR-RC slow shaper.
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Fig. 6. Schematic of a high-Z circuit.
Fig. 9. ENC with different input load capacitances.
Fig. 7. Simulation results of shaping time deviation.
Fig. 10. Measured results of the conversion gain and linearity.
Fig. 8. Photograph of the prototype chip and the test system.
different m and n size ratios. To confirm the effects using the high-Z circuit, the shaping times of the slow shaper for different amounts of input energies when using a high-Z circuit and a single MOS transistor as resistors are simulated by the Cadence Spectre. The simulation results of the shaping time deviation for the desired shaping time of 1 μs within the input charge range of 11.5 fC to 22.5 fC is shown in Fig. 7. The shaping time is more stable when using a high-Z circuit than when using a single MOS transistor. As a result, the linearity of conversion gain in this design can be improved because of the constant shaping time of the slow shaper.
Fig. 11. Measured time walk with input charge.
5. Implementation and test The prototype chip of a 16-channel front-end readout ASIC was 4
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caused by the chip package on noise performances, the ASIC was directly bonded on the PCB by the chip-on-board package technology. The measured equivalent noise charges (ENCs) for the different input load capacitances is shown in Fig. 9. For a typical channel, the measured ENC is 109.7 e− at 0 F plus 16.3 e− per picofarad with a power consumption of 4 mW per channel. 5.2. Gain and linearity Fig. 10 shows the relationship between the peak value of the output voltage and the input charge for a typical channel. A conversion gain of 87 mV/fC and a nonlinearity error of < 0.4% were achieved. Compared with the traditional approaches [3,7,10,16], the linearity of conversion gain achieved in this work was improved by at least 86.6% using a similar architecture as the front-end readout and manufacture process. 5.3. Time walk The measured time walk for a typical channel within the input charge range of 11.5 fC to 22.5 fC for gamma ray imaging is shown in Fig. 11[17,18]. The maximum time walk was < 4 ns. The time walk decreased with the increase of the input charge because the rising edges of the fast shaper became steeper when the input charge increased.
Fig. 12. Measured consistency among 16 channels.
5.4. Consistency among the channels In the prototype chip design, the analog circuits were separate from the digital circuits to reduce system noise and interference, and the guard rings and dummy units were added in the sensitive circuits and transistors. Consistency was degraded because of the influence of parasitic capacitances and the little differences in power supplies and bias voltages among the 16 channels. The measured consistency among the 16 channels is shown in Fig. 12 and the maximum error was 0.3%. 5.5. Energy spectrum test
Fig. 13. Measured energy spectrum using the
241
The energy spectrum test was completed by combining the ASIC with a 5 mm×5 mm×2 mm CdZnTe detector; 241Am radioactive source was used, and a high-bias voltage of −450 V was added at the CdZnTe detector. The measured energy spectrum is shown in Fig. 13, and an energy resolution of 2.975 keV (FWHM) for 241Am of 59.5 keV was obtained. Moreover, the crosstalk between channels was < 2%. Table 1 provides a comparison of the main performances of the readout ASIC and some similar works. Compared with the traditional approaches, the readout ASIC designed and implemented in this work has achieved outstanding linearity performance without compromising the performances of noise, power consumption, and chip size. The performances of the ASIC developed in this work can satisfy the requirements of the CdZnTe detector imaging system.
Am radioactive source.
implemented using a commercial 0.35 µm CMOS process with a chip size of 2.60 mm×3.53 mm. The photograph of the prototype chip and the test system are shown in Fig. 8. The experimental conditions were set as follows. The power supply of the prototype chip was 3.3 V, the integrating capacitor of CSA was 60 fF (EN0=1 and EN1=1), the shaping time of the slow shaper was about 1 μs in which the best noise performances can be obtained, and all experiments were carried out at room temperature.
6. Conclusion 5.1. Noise performances A linearity enhancement design of the 16-channel frond-end readout ASIC chip for CdZnTe detectors is presented. The resistors in the
To eliminate the effects of the parasitic capacitances and resistances Table 1 Comparison of the main performances of readout ASICs. Performances
This work
Ref [3]
Ref [7]
Ref [10]
Ref [16]
Technology Channel numbers Noise@0 pF Gain nonlinearity Chip size (mm2) Power Con.
0.35 µm CMOS 16 109.7 e− < 0.4% 2.60×3.53 4 mW/Ch
0.35 µm CMOS 8 130 e− 5% 2.95×2.95 4.125 mW/Ch
0.35 µm CMOS 32 39.5 e− 7.5% 5×5 2 mW/Ch
0.35 µm CMOS 36 150 e− 10% 6.905×6.380 6 mW/Ch
0.35 µm CMOS 8 86.5 e− < 3% 2.286×2.282 3 mW/Ch
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[5] Tetsuichi Kishidhita, Goro Sato, Hirokazu Ikeda, Tadayuki Takahashi, Tatsuya Kiyuna, Yoshio Mito, Low-noise analog ASIC for silicon and CdTe sensors, IEEE Trans. Nucl. Sci. 57 (5) (2010) 2971–2977. [6] VA32TA6 Documentation, 〈http://www.ideas.no/〉. [7] Hiroyasu Tajima, Tatsuya Nakamoto, Takaaki Tanaka, et al., Performance of a low noise front-end ASIC for Si/CdTe detectors in compton gamma-ray telescope”, IEEE Trans. Nucl. Sci. 51 (3) (2004) 842–847. [8] RENA-3TM IC User Specifications, 〈http://novarad.com〉. [9] T.Tumer, V.Cajipe, M.Clajus, etc. Multi-Channel Front0end readout IC for position sensitive solid-state detectors, IEEE Nuclear Science Symposium Conference Record, N14-91, pp. 384–388, 2006. [10] V.Cajipe, M.Clajus, S.Hayakawa, etc.Performance of the RENA-3 IC with position sensitive CZT and CaTe Detectors, IEEE Nuclear Science Symposium Conference Record, R12-56, pp. 300–307, 2008. [11] Wu Gao, Deyuan Gao, Christine Hu-Guo, Tingcun Wei, Y. Hu, Design and characteristics of an integrated multichannel ramp ADC using digital DLL techniques for small animal PET imaging, IEEE Trans. Nucl. Sci. 58 (5) (2011) 2161–2168. [12] X.C. Fang, W. Gao, Ch Hu-Guo, D. Brasse, B. Humbert, Y. Hu, Design of a lownoise front-end readout chip integrated with a high-resolution TDC for APD-based small-animal PET imaging, IEEE Trans. Nucl. Sci. 58 (2) (2011) 370–377. [13] Zhongyuan Chang, Willy M.C. Sansen, low-noise, low-distortion CMOS AM wideband amplifiers matching a capacitive source, IEEE J. Solid-State Circuit 25 (3) (1990) 833–840. [14] W. Sasen, Integrated low noise amplifiers in CMOS technology, Nucl. Instrum. Methods Phys. Res. A 253 (1987) 427–433. [15] Z.Y.Chang, W.Sasen, Test structure for evaluation of 1/f noise in CMOS technologies, in: Proceedings of the ISCAS’89, pp. 143–146, 1989. [16] W.Gao, H.Liu, D.Gao, etc. SENSROC4: An multichannel low-noise front-end readout ASIC dedicated to CZT detectors for PET imaging, Proceedings of the 3rd International Conference on ANIMMA, pp. 1–6, June, 2013. [17] Y.Yin, S.Komarov, H.Wu, T.Song, Y.Tai, etc. Characterization of highly CdZnTe detectors for sub-millimeter PET imaging, IEE Nuclear Science Symposium Conference Record, J05-4, pp. 2411–2414, 2009. [18] Jose-Gabriel,, M. Macias-Montero, M.Chmeissani, etc. VIP-PIX: a Low Noise readout ASIC for pixelated CdTe gamma-ray detectors for use in the next generation of PET scanners, IEEE Nuclear Science Symposium and Medical Imaging Conference Record, N16-3, pp. 1452–1459, 2012. [19] W. Liu, T. Wei, L. Yang, Y. Hu, A 12-bit, 1 MS/s SAR-ADC for a CZT-based multichannel gamma-ray imager using a new digital calibration method (P03018)J. Instrum. 11 (3) (2016) 1–17.
slow shaper are realized using a high-Z circuit to obtain a constant resistance value instead of using only a MOS transistor. Thus, the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is significantly improved. The readout ASIC is designed and fabricated in 0.35 µm CMOS process with a die size of 2.6 mm×3.53 mm. The measurement results show that the nonlinearity of conversion gain is < 0.4%, which shows an improvement of at least 86.6% from the traditional approaches using a similar architecture of front-end readout and manufacture process. The front-end readout ASIC developed in this work has an outstanding linearity performance while maintaining the same level of noise, power consumption, and chip size performances. A 12-bit SAR-ADC [19] and a TDC will be integrated with this ASIC on one chip for the applications of CdZnTe detectors in future works. Acknowledgments This work was supported by the National Key Scientific Instrument and Equipment Development Project of China under Grant No. 2011YQ040082. References [1] R.Amrami, G.Shani, Y.Hefetz, etc. PET properties of pixelated CdZnTe detector, in: Proceedings of the 22nd Annual EMBS International Conference, pp. 94–97, 2000 [2] P.Vaska, A.Bolotnikov, G.Carini, G.Camarda, etc. Studies of CZT for PET applications, IEEE Nuclear Science Symposium Conference Record, J03-1, pp. 2799– 2802, 2005. [3] T.Kishishita, H.Ikeda, T.Kiyuna, K.Tamura, etc. Development of a Low-Noise Analog Front-end ASIC for CdTe Detectors, IEEE Nuclear Science Symposium Conference Record, N35-4, pp. 1992–1996, 2007. [4] Ken-ichi Tamura, Tatsuro Hiruta, Hirokazu Ikeda, Hokuto Inoue, Development of ASICs for CdTe pixel and line sensors, IEEE Trans. Nucl. Sci. 52 (5) (2005) 2023–2029.
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