Low-frequency generation–recombination noise in fully overlapped lightly doped drain MOSFETs

Microelectronics Journal Microelectronics Journal 32 (2001) 43–47 www.elsevier.com/locate/mejo

Low-frequency generation–recombination noise in fully overlapped lightly doped drain MOSFETs A. Kumar a, E. Kalra a, S. Haldar b, R.S. Gupta a,* a

Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi 110 021, India b Department of Physics, Motilal Nehru College, Benito Juarez Road, New Delhi 110 021, India Received 1 June 2000; revised 10 July 2000; accepted 18 July 2000

Abstract A model for generation–recombination (g–r) noise in FOLD MOSFETs is presented incorporating the field dependent mobility and the bias dependent series resistance. The g–r noise is due to the emission and capture of carriers in the space charge region in the bulk-channel junction. It is observed that noise power increases with increasing drain voltage and decreases with decreasing gate voltage. The results so obtained are compared with the experimental data. 䉷 2000 Elsevier Science Ltd. All rights reserved. Keywords: Generation–recombination noise; Drain MOSFETs; Bulk-channel junction

1. Introduction Noise is an undesirable effect that obscures the information contained in devices and limits its performance. Nevertheless, it is always present in MOSFETs due to local random events, like scattering mechanisms. These produces fluctuations of their velocity or of their number, which in turn produces fluctuations of the current flow, and hence fluctuations of the voltage at the output. The hot carrier effects have specific influence on noise, since most of the noise source expressions actually depend on electric field, involved in hot carrier regime [1,2]. There are three major noise sources in MOSFETs: i.e. the thermal noise in the channel, 1/f noise at the oxide–semiconductor interface, and the generation–recombination noise (g–r noise) due to random emission of electrons and holes at the defect centers in the depletion region of the semiconductor and have direct importance to MOS analog applications. A g–r noise study has been hindered by its low value compared to 1/f noise. Very little work has been done on the g–r noise [3,4] for conventional and LDD MOSFETs. In fully overlapped lightly doped drain MOSFETs, developed for reliability improvement, there is report of 1/f noise only [5–8]. In this paper, we present an analytical model for the g–r noise of FOLD MOSFET (shown in Fig. 1) incorporating * Corresponding author. Tel.: ⫹91-11-688-6606; fax: ⫹91-11-688-6606/ 64271. E-mail address: [email protected] (R.S. Gupta).

the series resistance of n ⫺ region. The theoretical predictions are compared with experimental data of LDD MOSFETs since most results for FOLD structure are not available in the literature. 2. Model development The drain current in the linear region can be written as   dV…y† …1† Ids ˆ mn WQn ⫺ dy where W is the effective channel width. Qn is the electron density per unit area given by Qn ˆ ⫺Cox …V 0gs ⫺ VFB ⫺ fss ⫺ 兩QB 兩=Cox †

…2†

and the electron mobility m n in the surface inversion layer can be expressed as [9]

mn ˆ

mn0   aCox Q dV…y† 兩 1⫹ V 0gs ⫺ VFB ⫺ fs ⫹ B ⫹ b兩 21si Cox dy …3†

where a is an empirical fitting parameter. b ˆ mn0 =nsl ; n sl is the scattering-limited velocity, m n0 the maximum electron mobility in the inversion layer, V(y) the inversion channel potential relative to the n ⫺ source voltage, 1 si the dielectric permittivity of the bulk semiconductor, VFB the flat band voltage, f ss the surface potential along the channel with

0026-2692/00/$ - see front matter 䉷 2000 Elsevier Science Ltd. All rights reserved. PII: S0026-269 2(00)00077-X

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A. Kumar et al. / Microelectronics Journal 32 (2001) 43–47

Fig. 1. (a) Schematic diagram of the LDD structure. (b) Equivalent circuit of the FOLD MOSFET.

respect to the n ⫺ source, Cox the gate oxide capacitance per unit area. V 0gs …V 0ds † is the intrinsic gate (drain)-source voltage defined elsewhere [10]. QB, the surface depletion charge density per unit area under the gate, is given by p QB ˆ ⫺ 2q1si Na fss

…4†

where Na is the shallow acceptor concentration. Here we assume that the bulk is uniformly doped and the surface potential is then given as

fss ˆ 2fF ⫹ V…y†

…5†

where f F is the Fermi potential. Using Eq. (1) and Eqs. (3)–(5), we get   aCox Ids 兩Q 兩 V 0gs ⫺ VFB ⫺ fss ⫹ B dV…y† C 21 ˆ   si  ox  dy 兩Q 兩 B mn0 WCox V 0gs ⫺ VFB ⫺ fss ⫺ ⫺ bIds Cox …6† Ids ⫹

Using Eqs. (1), (2) and (6), m n can be approximated as   bIds mn0 V 00gs ⫺ V…y† ⫺ mn0 WCox mn ˆ   …7† a 兩Q 兩 aCox 00 B 00 ⫹ …V gs ⫺ V…y†† …V gs ⫺ V…y†† 1 ⫹ 1si 21si

where Vt0 ˆ VFB ⫹ 2fF ⫹

兩QB 兩 Cox

…8†

and V 00gs ˆ V 0gs ⫺ Vt0

…9†

We assume that the drain current spectral density contributed by the n ⫺ regions is negligible compared with that produced in the intrinsic channel. Accounting field dependent mobility and bias dependent series resistance, the low-frequency g–r noise derived by Yau and Sah [3] is modified and drain current spectral density due to the g–r process in the depletion region of a FOLD MOSFET can be written as

SIgr

0 4q2 Ids Nt ZV ds mn dV…y† ˆ 2 V 00gs ⫺ V…y† Cox L 0 ! ZWd f …1 ⫺ f †t x t t gr 1⫺ dx  2 Wd 1 ⫹ v2 tgr 0

…10†

where Nt is the trap density, Ids the drain current in the linear region, ft the fraction of occupied defect centers and tgr the fluctuation constant given in Ref. [11]. If we assume the depletion approximation, then ft and tgr can

A. Kumar et al. / Microelectronics Journal 32 (2001) 43–47

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Fig. 2. I–V characteristics of FOLD and LDD MOSFETs for different gate voltages. ‰mn0 ˆ 597:3 cm2 =V ⫺ s; a ˆ 0:72 × 10⫺6 cm=V; b ˆ 4:9 × 10⫺5 cm=V; h ˆ 4:459 × 10⫺2 V⫺1 ; Vfb ˆ ⫺:745 V; Rs ˆ Rd ˆ 8 V , N a ˆ 6:9 × 1014 cm⫺3 ; Nd ˆ 2:3 × 1016 cm⫺3 Š:

be approximately taken as constant and we get SIgr ˆ where

4q2 Ids Nt ft …1 ⫺ ft †tgr Z 2 L 2 3Cox 1 ⫹ v2 tgr 0

s 21si …2fF ⫹ V…y†† Wd ˆ qNa

V 0ds

mn W dV…y† …11† V 00gs ⫺ V…y† d

Substituting Eq. (7) into (11) and on integrating, we get the g–r noise as a function of device terminal voltages ÿ
 s 4q2 Ids Nt ft 1 ⫺ ft tgr 21si 21si SIgr ˆ mn0 X …12† 2 L 2 aCox qNa 3Cox 1 ⫹ v2 tgr where X ˆ X1 ⫺ X2 ⫹ X3 ⫺ X4

…13a†

Fig. 3. Variation (Svd) due to g–r noise and (Svd1) due to1/f noise with Vds. ‰mn0 ˆ 597:3 cm2 =V ⫺ s; Nt ˆ 7:99 × 1011 cm⫺3 ; h ˆ 4:459 × 10⫺2 V⫺1 ; a ˆ 0:72 × 10⫺6 cm V⫺1 ; b ˆ 4:9 × 10⫺6 cm V⫺1 Š:

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A. Kumar et al. / Microelectronics Journal 32 (2001) 43–47

Fig. 4. Variation of Svd due to g–r noise with Vgs. ‰mn0 ˆ 597:3 cm2 =V ⫺ s; Nt ˆ 7:99 × 1011 cm⫺3 ; h ˆ 4:459 × 10⫺2 V⫺1 ; a ˆ 0:72 × 10⫺6 cm V⫺1 ; b ˆ 4:9 × 10⫺6 cm V⫺1 ; Vds ˆ 0:5 VŠ:

P X1 ˆ ⫺ 1 ⫺ 2 Y

!

P11=2 Y

! X3 ˆ

00 0 P1=2 1 ⫹ …P1 ⫺ V gs 00 ⫹ V ds † 00 0 1=2 P1=2 1 ⫺ …P1 ⫺ V gs 00 ⫹ V ds †

P11=2 ⫹ …P1 ⫺ V 00gs 00 †1=2 ⫺ln 1=2 P1 ⫺ …P1 ⫺ V 00gs 00 †1=2



P X2 ˆ 1 ⫺ 2 Y



…P1 ⫹ Y†1=2 Y



!! (13b)

P ⫺ 1⫺ 2 Y



…P1 ⫹ Y† Y

X4 ˆ

P2 Y

P1 ˆ 2fF ⫹ V 00gs

…P1 ⫹ Y† ⫹ …P1 ⫺ …P1 ⫹ Y†1=2 ⫺ …P1 ⫺ 1=2

ln

! (13d)

!

…P1 ⫺ V 00gs 00 †1=2 ⫺ V 00gs 00

!

…13e†

!!

P2 ˆ

bIds mn0 WCox

…13f† …13g†

and   21si a兩QB 兩 1⫹ Yˆ aCox 1si

!

!



!



1=2

P11=2 ⫹ …P1 ⫺ V 00gs 00 ⫹ V 0ds †1=2 1 ln P11=2 ⫺ …P1 ⫺ V 00gs 00 ⫹ V 0ds †1=2 2P1=2 1

00 1=2 P1=2 1 1 ⫹ …P1 ⫺ V gs 00 † ln × 00 1=2 P1=2 2P11=2 1 ⫺ …P1 ⫺ V gs 00 †

…P1 ⫹ Y†1=2 ⫹ …P1 ⫺ V 00gs 00 ⫹ V 0ds †1=2  ln …P1 ⫹ Y†1=2 ⫺ …P1 ⫺ V 00gs 00 ⫹ V 0ds †1=2 

!

…P1 ⫺ V 00gs 00 ⫹ V 0ds †1=2 ⫺ …V 00gs 00 ⫺ V 0ds †

! 1=2

 ln

P2 Y

V 00gs 00 †1=2 V 00gs 00 †1=2

!

…13c†

…13h†

The drain voltage spectral density due to 1/f noise and g–r noise in the intrinsic channel can be written as SVd ˆ

…SI1=f ⫹ SIgr † g2d

…14†

A. Kumar et al. / Microelectronics Journal 32 (2001) 43–47

where gd is the drain conductance [10]. SI1/f is the 1/f current noise derived in Ref. [5]. 3. Results and discussion Fig. 2 shows the variation of drain current for FOLD and LDD MOSFETs with drain voltage at the different gate voltages. The modeled results for LDD structure show the close proximity with the experimental data [12]. The comparison of drain currents for LDD and FOLD structures is also shown. It is observed that FOLD structure can achieve higher drivability than the LDD owing to less parasitic resistance of the n ⫺ region. In Fig. 3, the variation of g–r noise and 1/f noise with drain voltage is shown. It is found that the noises increase with increasing the drain voltage. The variation of g–r noise with gate voltage is shown in Fig. 4. It is clear from the figure that g–r noise decreases with increase in gate voltage. It is also observed that noise in FOLD structure is less than that in LDD MOSFET. 4. Conclusion An improved theoretical model for the g–r noise of fully overlapped lightly doped drain MOSFET has been developed in the linear region at strong inversion. The model takes into account the longitudinal and transverse field dependent mobility and the series resistance of the n ⫺ region. It is observed that FOLD MOSFET has less g–r noise than that of LDD MOSFET. The model compares favorably with the experimental results. Acknowledgements The authors are thankful to the Defense Research and Development Organization, Ministry of Defense, Government of India for providing financial support to carry out this work.

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