D converters

Measurement 32 (2002) 231–239 www.elsevier.com / locate / measurement

Measuring the static characteristic of dithered A / D converters Francesco Adamo, Filippo Attivissimo, Nicola Giaquinto, Mario Savino* Laboratory for Electric and Electronic Measurements, Department of Electrics and Electronics ( DEE) –Polytechnic of Bari, Via E. Orabona 4, 70125 Bari, Italy Received 12 September 2001; received in revised form 1 December 2001; accepted 17 January 2002

Abstract Dithering is a useful technique that removes quantization error and part of the linearity error in A / D converters. Removing the remaining static error requires a periodical fast measurement of the characteristic, which is a rather difficult task because of the intrinsic very high resolution of the dithered device. Focusing on this issue, the paper examines three possible test methods: statistical analysis, time domain analysis, and, with more detail, frequency domain analysis. The peculiar nature of the static characteristic of dithered converters makes the third method particularly attractive. The frequency domain technique is proposed, therefore, as a good practical tool for implementing linearization in A / D converters with dither.  2002 Elsevier Science Ltd. All rights reserved. Keywords: Analog-to-digital conversion; Dithering; ADC testing; Frequency domain analysis; Chebyshev polynomials

1. Introduction Dithering is a common and well-known technique more and more employed with modern analog-todigital converters (ADCs) for measurement applications [1,2]. In dithered converters the input is added to a small ‘noise’ (dither signal) before the digitization. More specifically (Fig. 1), in the subtractive topology a pseudorandom dither signal is synchronously added to the analog input and subtracted from the digital output; in the non-subtractive topology the dither signal is only added at the input. In both cases, effective resolution improvement is obtained by *Corresponding author. Tel.: 139-080-596-3318; fax: 139080-596-3410. E-mail addresses: [email protected] (F. Adamo), [email protected] (F. Attivissimo), [email protected] (N. Giaquinto), [email protected] (M. Savino).

filtering or averaging, at the cost of bandwidth or speed reduction. Non-subtractive dither is especially appealing and more common in practice, because it does not need costly hardware for generating a precisely known signal and perform synchronous analog and digital additions. Besides, it can be sometimes implemented by simply exploiting the intrinsic analog noise of the converter, or other small stable signals inherently present in the digitizing hardware. In this paper we will refer always to the non-subtractive dither, but the final results apply without substantial differences also to the subtractive topology. The dither technique is essentially aimed at reducing systematic conversion errors, including quantization, but there are not standard techniques to measure the static characteristic of the converter for this particular case. The problem lies mainly in the very high (theoretically infinite) resolution of the ADC,

0263-2241 / 02 / $ – see front matter  2002 Elsevier Science Ltd. All rights reserved. PII: S0263-2241( 02 )00030-1

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Fig. 1. Signal digitization with dither: subtractive topology (a) and non-subtractive topology (b).

and is therefore caused just by the main advantage provided by the dither. An accurate measurement of the characteristic is useful to assess the uncertainty of the device, and is necessary when the aim is to obtain a highly linear converter by further linearization, for example implementing a look-up linearization table like suggested in Ref. [3]. The present paper is therefore focused on this measurement, with special attention to the problem of its velocity: this is indeed a critical point when one must use its results for the periodical automatic recalibration of a lookup table. Section 2 of the paper deals, under a theoretical viewpoint, with linearity errors in ADCs and effect of dither on them. In Section 3 three possible methods for measuring the static characteristic of an ADC with dither are examined, i.e. the statistical analysis (histogram test), the time-domain analysis, and the much faster frequency-domain analysis. Theoretical considerations suggest that the frequency domain approach, usually too imprecise for ordinary converters, is well suited for use with dithered converters. Section 4 reports experimental results that show the practical advantages and drawbacks of each test method with dithered converters, and demonstrates the special effectiveness of the frequency-domain approach.

2. Effect of dither on the static characteristic of an ADC In order to examine in detail the effect of dither on

the characteristic, it is worthwhile to recall some simple but often misunderstood aspects of linearity error in ADCs, with or without dither. The integral nonlinearity (INL) of a converter is defined (without considering gain and offset errors that are inessential in this analysis) as the difference inl k 5 t kid 2 t k

(1)

where t id k are the ideal (equispaced) threshold levels and t k the actual threshold levels of the quantizing characteristic. The servo-loop based test (static) or the histogram test (dynamic) are the standard methods to obtain the INL [4], which is usually represented by a plot of inl k versus the index k or, equivalently, versus the equispaced threshold levels t id k . Although useful and very common, this plot should never be understood as a representation of the true ‘linearity error’ of the ADC, for reasons briefly explained in the following. The static characteristic of the converter can be represented as g((x) 5 quant( gs (x))

(2)

where quant( ? ) stands for ideal quantization and gs (x) is an arbitrary function such that gs (t k ) 5 t kid and ug(x) 2 gs (x)u # 0.5 LSB (least significant bit, or quantization step width). This equation expresses the decomposition (Fig. 2) of the nonlinear quantization characteristic in the cascade of a smoother nonlinear characteristic gs (x) and an ideal quantizing characteristic. The actual ‘linearity error’ is therefore the

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Fig. 2. Decomposition of a nonlinear quantizer g(x) in an ideal (linear) quantizer quant( ? ) preceded by a smoother nonlinearity gs (x).

sum of that introduced by the first block gs (x) 2 x, and that introduced by the second, quant( gs (x)) 2 gs (x). Due to the nature of the function gs (x), in particular to its property gs (t k ) 5 t id k , the error introduced by the first block is correctly represented by a plot of inl k vs. t k , which is different (even if only slightly in practice) from the usual plot of inl k vs. t id k (Fig. 3a). The second term is quantization error, which is a sawtooth function of x, with irregularly

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spaced jumps and ranging in 60.5 LSB, a quantity usually of the same order of magnitude as inl k (Fig. 3b). In the remainder of the paper, therefore, we will use plots of inl k versus the irregularly spaced t k , instead of the usual plots of inl k vs. k or t id k ; besides, it must be kept in mind that the linearity error is a far more erratic function that includes quick oscillations of 60.5 LSB around this plot. As briefly recalled in the Introduction, the dither technique is aimed at reducing the linearity error. i.e. smoothing the static characteristic making it nearer to a straight line. In early works about this subject (e.g. [5,6]) the INL error (1) is not considered and the ADC nonlinearity is therefore pure quantization error. These theoretical analyses, mainly based on the sophisticated quantization-theoretic tools originally developed by Widrow [7], have shown that a proper dither signal is able to make the quantization error exactly uncorrelated with the input, even with a constant one, so that it can be completely eliminated by a digital filter or by averaging. Dither is therefore able, in principle, to transform an ideal quantization characteristic in a perfect straight line. Afterwards other authors have studied more deeply the dithered ideal quantizer, but the true next step has been considering a more practical model of ADC, i.e. the dithered quantizer with INL errors [8,9]. These

Fig. 3. (a) Comparison between a plot of inl k vs. t id k ( . . . ) and a plot of inl k vs. t k (—). The latter is the true nonlinearity of the block gs (x). (b) Comparison between the nonlinearity of the block gs (x) and the nonlinearity of the converter ( g(x) 2 x), that includes quantization error.

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analyses are mainly based on decomposing the static characteristic in the sum of an ideal quantization characteristic and a ‘bit error’ function. The results are derived by extending typical methods of probability theory and quantization theory, and can be summarized saying that dither ‘smears’ the linearity error, at least if examined at the quantization step scale, and improves the effective resolution. Although the mentioned works provide excellent mathematical studies of dithering in general, the effect of dither on an actual ADC can be satisfactorily described by a quite simple formula. From the scheme of Fig. 1a it is clear, indeed, that the mean value of the output y 5 g(x 1 n) is given by 1`

y5

E g(x 1 n) ? f(n) dn 5 g*f(2x) 5 g (x) d

(3)

2`

where f(n) is the probability density function (pdf) of the dither signal n(t). From a quantitative viewpoint, this formula describes exactly the transformation of the static characteristic (and therefore the linearity error reduction); from a qualitative viewpoint, it allows one a good intuitive understanding of the linearization mechanism. As the original characteristic g(x) becomes the dithered characteristic gd (x) via a convolution operation, dithering is basically a lowpass filtering of g(x). This improvement, of course, is not priceless, as gd (x) is only the average characteristic that describes systematic errors; as regard random errors, the variance of n(t) will be added to that of the converter analog noise. Therefore, systematic errors are traded for random errors: improving the effective resolution implies use of averaging or filtering, and consequent speed or bandwidth reduction. Eq. (3) makes it clear that the dither technique, originally designed for improving the resolution of ideal quantizers, is more generally useful to remove small-scale linearity errors, i.e. errors that present large variations in a small interval (few LSBs). Quantization error is indeed a special case of this kind of error. Eq. (3) makes also clear that, as dither must be reasonably small in order to avoid too large random errors, it is not possible to linearize completely an actual ADC using this technique: largescale errors survive and can be actually quite large.

A highly linear converter can be obtained, therefore, only by coupling the dither technique with a largescale error correction, that can consist of a look-up table or any algorithm implementing the inverse transformation 21 z 5 g 21 d ( y) 5 g d ( gd (x)) 5 x

(4)

that, in principle, completely zeroes systematic errors if gd (x) is invertible. As Eq. (4) seems to demonstrate that a ‘perfect’ converter is obtainable by combining dithering with an inverse nonlinear transformation, it is worth commenting on it with more mathematical rigour. The input–output relationship in a dithered converter is y 5 g(x 1 n) 5 gd (x) 1 n9, where gd and g are related by Eq. (3) and both n and n9 are zero-mean random variables. Averaging the results of a finite number m of measurements with the same input x reduces, but does not nullify, the error n9. As the averaged result y¯ 5 o i y i /m is prone to a residual ] error n9 5 o i n 9i /m, using the inverse transformation (4) means adopting a least square (LS) estimator ¯ ) indeed [10] of the unknown ‘parameter’ x: g 21 d (y minimizes the sum squared error o i ( y i 2 gd (x))2 . With a sufficient number of averages the zero-mean ] error n9 is normally distributed, regardless of the ¯ ) can be considered a density of n9, and g 21 d (y maximum likelihood (ML) estimator: if y¯ 5 yo , than x 0 5 g d21s y 0d is the number x that maximizes ]s y 2 g (x)d. f(y¯ ux 0 ) 5 fn9 LS and ML estimators, d besides being of course not ‘perfect’, are not the best choice in all possible situations, because they do not use the possibly available information about the input. When, on the contrary, a narrow probability density function f(x) of the input is known, Bayesian estimators perform far better: for example x 0 5 E[xuy¯ ], or x 0 5 o i E[xuy i ] /m, or E[xuy 1 , y 2 , . . . , y m ]. Formulae for these estimators in the case at hand are derivable with some calculus, but discussing them more deeply goes beyond the scope of this work. It must be highlighted that the estimator (4) is very well-suited for many practical situations, not only because f(x) is often large or unknown, but also because deriving the estimate does not require the burdensome computations usually implied by the Bayesian approach. Of course a direct lookup table is

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¯) hardly a good choice for implementing g 21 d (y (averaging m values multiplies by m the number of possible output values), and therefore some kind of interpolation is necessary [3]. The function gd (x), however, deriving from the low-pass filtering of a staircase, is very likely to be monotonic and continuous, and therefore actually invertible. On the contrary, the original transfer characteristic g(x) is never invertible, due to quantization and also to small-scale errors. It can be demonstrated, indeed, that for an ADC without dither with quantization step Q and differential nonlinearity inl k 2 inl k21 5 dnl k (a wellknown measure of small-scale errors), the optimal linearizing look-up table leaves ] a systematic error with power P(Q 2 / 12(1 1dnl 2k / 3) [11]. This formula shows clearly that all small-scale errors, not only quantization, cannot be reduced by a look-up table. Using the estimator (4) implies the knowledge of gd (x), which brings to attention the problem of measuring the static characteristic of a dithered nonlinear quantizer. The first impression of having a simple and already solved problem is in fact deceptive, and indeed comparatively few works exist on the specific topic of dithered ADC testing (one example is Ref. [12]). In the following, possible solutions of the problem will be examined, with special regard to the most interesting one—frequency domain analysis with Chebyshev polynomials.

3. Measuring the characteristic of dithered ADCs—theory Measuring the static characteristic means of course comparing the average output with the input, for all possible values of the input. The servo-loop method [4] is simple and direct, but requires a great amount of time (usually many hours). As long as the ADC can be considered a static system even with a dynamic input (a condition commonly met by modern devices, provided that the signal frequency is not too high), an equivalent but much faster method is the histogram test [4]. In the case of ADC with dither, however, direct use of this test is totally unpractical, because of the big increment in the number of output codes achieved after averaging

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(using the test without averaging yields simply the characteristic g(x) of the converter without dither). A possible method is therefore instead turning off the dither, measuring g(x), then obtaining gd (x) indirectly by Eq. (3). The drawbacks of this approach are that it can be very time-consuming (hundreds of samples per each ADC code bin are needed), and that it requires accurate knowledge of the pdf of the dither, which is not always available (especially if inherent noisy signals of the acquisition board are used). Therefore, even if a histogram test is applicable in a laboratory situation, it is not very feasible for a quick on-the-field recalibration of the system. A direct nonlinearity measurement on the dithered ADC, not involving a convolution with an estimated pdf, would also be useful as a diagnostic tool about the actual effectiveness of the dithering in the practical situation. A straightforward approach to obtain such a direct measurement is the simple comparison of the averaged output with the (known) input of the converter. Of course this ‘brute force’ method requires that random errors are practically zeroed by a very large number of averages (which is not usual in the normal use of the ADC), as the measured error must be actually the systematic one and no more. The steps of this method can be as follows: acquire N records y i (t) of half a period in the phase interval f 2 p / 2, p / 2 g of a full-scale spectrally pure sine wave x(t) 5 V sin v t (this waveform spans monotonically the whole range of the ADC); calculate the average y(t) 5 1 /N o y i (t); find the best-fit sine wave x(t) of the averaged signal y(t) [4]; find the static characteristic as gd (x) 5 y(t) 2 x(t) (or by gd (x) 5 y(t) 2 Gx(t) 2 O, where G and O are gain and offset errors). The number of samples per record determines the number of discrete points x i in which the characteristic gd (x) will be measured. The number N of records, instead, must be fixed according to the desired measurement uncertainty, which can be quantified simply by the standard deviation of the measurement error given by ]]]] ] stot 5œs 2d 1 Q 2 / 12 /ŒN

(5)

where sd is the standard deviation of the dither and

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Q the quantization bin. This formula allows one to derive easily the value of N needed to obtain a fixed confidence interval for gd (x). This time-domain method is undoubtedly very reliable, as it deals directly with the physical input and output of the ADC, and does not require complicated computations, or any knowledge of the dither signal (this is useful for deriving the uncertainty, not the measurement). On the other hand, it can be even more time-consuming than the histogram test, as the required number of averages N may be very large, especially if a comparatively wide dither signal is used. The third possibility for measuring gd (x) consists in using FFT analysis that the authors have already used in former works [13,14] for testing conventional ADCs without dither. This technique is based on the Chebyshev polynomials expansion of a generic memoryless transfer characteristic g(x). If at the input of g(x) is applied the sinusoidal signal x(t) 5V cos v t 1 C, then the output must be in the form:

O

` a0 y(t) 5 ] 1 a cos(nv t) 2 n51 n

(6)

It can be easily demonstrated that the best (in the mean-squared error sense) polynomial approximation of g(x) is the sum

O S

` a0 x2C g(x) 5 ] 1 a n Cn ]] 2 n51 V

D

(7)

where Cn (x) is the nth degree Chebyshev polynomial of the first kind, Cn (x) 5 cossn ? arccos(x)d. In [13] and [14] the possibility of using this theory in standard ADC testing has been investigated. In this case quantization error and differential nonlinearity are a major concern: it is virtually impossible to obtain detailed information about smallscale errors. Nevertheless it is possible, by a proper selection of the harmonics to be accounted for in formula (7), to obtain useful information about largescale errors. In the case of an ADC with dither, where quantization and small-scale nonlinearity errors are usually negligible, the illustrated technique is particularly attractive. Compared with the histogram test, the FFT test does not waste time measuring small-scale

errors, and can be therefore far quicker without much loss in global accuracy. Also compared with the time-domain method the FFT appears to be advantageous, as the operation of selecting the meaningful harmonics in Eq. (7), discarding the noise floor, is an inherent filtering that effectively substitutes averaging. Also in this case the price to pay concerns the accuracy in measuring abrupt variations in the static characteristic, which is a small price when using dither. Experiments in next section compare results obtained with the different techniques, and show that the FFT test is able to give accurate results in a fraction of the time required by the other tests, thanks to the dither capability of removing quantization and small-scale nonlinearities. Besides velocity and reliability, there are other advantages, related to the problem of ADC linearization, which will be briefly discussed in the conclusions.

4. Experimental results The theoretical conclusion that the FFT method can give very good performance needs of course practical demonstrations. A meaningful validation has been obtained by means of experiments involving an 8-bit flash converter embedded in a digital oscilloscope. It must be considered that the low resolution goes in advantage of histogram and timedomain analysis, as the frequency domain test relies on a low level of quantization and small-scale errors. All the results reported below have been obtained using a coherently sampled sinusoidal test signal at about 1500 Hz. The choice of a comparatively slow test signal assures that dynamic nonlinearities that arise at higher frequencies do not pollute the results. The performed tests must be considered therefore substantially static, and the measured nonlinearity is truly the static part of the ADC characteristic. It is not useless to stress that measuring the integral nonlinearity at ‘high’ frequencies (i.e. when also meaningful dynamic errors are present) can give a gross qualitative idea of the performance deterioration in dynamic conditions, but the obtained results can by no means be regarded as the ADC characteristic. In the first experiment the actual threshold levels of the converter have been accurately measured by performing a histogram test with an overdriving sine

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wave, according all the prescriptions in [4]. A very high number of samples have been acquired (many thousands per code bin) so that random errors on the measured nonlinearity are certainly negligible. Of course also systematic errors have been made very small using a sine wave with very high purity compared with the ADC resolution. The result of the histogram test is represented, in Fig. 4 (thin line), as a plot of inl k vs. t k , as stated and explained in Section 2. It is important to note the typical appearance of the nonlinearity in an actual ADC: it can be seen as the superposition of a slowly varying function with greater amplitude (large-scale errors), and smaller components with much faster variations (small-scale errors). It is clear, from the briefly recalled theory of Chebyshev polynomials, that the first component generates distortion power concentrated in few spurious harmonics, whereas the latter components are responsible for distortion power spread in many small harmonics, in a way similar to quantization error. In the second test the ADC has been employed with a non-subtractive dither, approximately Gaussian with standard deviation sd ¯ 1.5 LSB rms. The aim of this test, as explained in the previous Section,

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is to measure directly the nonlinearity of the dithered converter, without resorting to simulations or numerical evaluation of (3), that require accurate knowledge of the dither pdf. We have taken N5 10,000 records of 4,000 samples, obtaining an uncertainty of about 0.05 LSB with a confidence level of 99.7%, according to (5). This simple test has been, of course, no less time-consuming than the histogram. The result, reported in Fig. 4 (thick line) compared with that of the histogram test, shows that the dither, besides removing the quantization error, has also eliminated most small-scale errors of the converter. Finally, we have performed the FFT test on the dithered ADC. As the device was embedded in a digital oscilloscope allowing the acquisition of 4,000 samples per record as a maximum, four records have been acquired and averaged, so utilizing 16,000 samples for the estimate. Fig. 5 represents the normalized power spectral density of the output of the converter; the first 35 harmonics are highlighted, as they have been used to reconstruct the characteristic of the dithered converter. As pointed out in previous works [13,14], the optimum number of harmonics to consider is a critical point, as it

Fig. 4. Linearity of the 8-bit ADC: without dither, measured by the histogram test (thin line), and with dithered, measured via sine wave fit on the average of 10,000 records of 2,000 samples (thick line). It is apparent that, besides quantization errors, also small-scale nonlinearity errors are dramatically reduced by the dither.

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Fig. 5. Normalized power spectral density of the output of the undithered ADC under test (16,000 samples) when stimulated by a sinusoidal input. The plot shows the first 35 harmonics, that have been employed to obtain the Chebyshev polynomial approximation of the nonlinearity of the dithered converter.

Fig. 6. Plot of the overall nonlinearity of the dithered ADC measured via FFT (thick line), compared with the ‘true’ nonlinearity measured via sine wave fit on the average of 10,000 records (thin line). The FFT test has required only 16,000 samples and the result is a sum of 35 Chebyshev polynomial terms.

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depends on the actual noise level inherently present in the digitizer, and on the number of acquired samples [15]. Providing a simple formula yielding, on the basis of the measured spectrum, the harmonic orders to include in (7), is one of the still open questions of this research; however, a rule of thumb that has been found to work well in many practical cases is the following: find the index h such that all the harmonics of order h11, . . . are below the expected quantization noise level (supposed white); consider in (7) all the harmonics from order 0 to order h, including those below the expected quantization noise level. Besides this empiric general rule, it can be said that for an 8-bit converter, tested with 8,000–16,000 samples, considering from 30 to 50 harmonics is almost always adequate to obtain a good evaluation of large-scale errors. The nonlinearity derived from the application of formula (7) is compared, in Fig. 6, with the ‘true’ nonlinearity of the dithered converter as measured by the direct comparison of the input with the averaged output. It is apparent that the test results are quite satisfactory: the maximum deviation between the two estimates is below 0.1 LSB, and the typical deviation is 5–10 times smaller. On the other hand, the test is practically instantaneous, if compared with the histogram test, or with the time domain test on the averaged output.

5. Conclusions Measuring the static characteristic of an ADC with dither is a non-trivial task that cannot be accomplished directly with a standard histogram test. Theory of dithering shows that one can use a histogram test on the ADC without dither and then derive the characteristic by convolution; an alternative is performing a straightforward time-domain analysis. Theory of dithering, however, teaches also that the nonlinearity of a dithered ADC is mainly made of large-scale errors without sharp variations, and therefore the characteristic can be accurately measured as a Chebyshev polynomials summation by FFT test. This test is much faster than the two alternative methods and is therefore particularly convenient, especially if it must be done periodically and automatically to recalibrate a linearizing function

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for removing large-scale static errors. Speaking about linearization, it should be kept in careful consideration that the static characteristic derived by the FFT test are expressed by very few coefficients (35 in the reported experiment), instead of hundreds or thousands of function values. Therefore, also the form of the static characteristic provided by the FFT test is advantageous, and could be used to obtain a computationally cheaper linearization algorithm. This issue, however, goes beyond the scope of this work.

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