Modeling of kink effect in polycrystalline silicon thin-film transistors

Solid-State Electronics 53 (2009) 669–673

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Solid-State Electronics journal homepage: www.elsevier.com/locate/sse

Modeling of kink effect in polycrystalline silicon thin-film transistors Wanling Deng a,*, Xueren Zheng b a b

Department of Electronic Engineering, College of Information Science and Technology, Jinan University, Guangzhou 510630, China Institute of Microelectronics, South China University of Technology, Guangzhou 510640, China

a r t i c l e

i n f o

Article history: Received 2 February 2009 Received in revised form 17 March 2009 Accepted 21 March 2009 Available online 25 April 2009 The review of this paper was arranged by Prof. A. Zaslavsky

a b s t r a c t A new analytical DC model accounting for the kink effect of polycrystalline silicon thin-film transistors (poly-Si TFTs) is presented in this paper. When considering the exponential density of trap states in the film, a quasi-two-dimensional approach is used to give an analytic expression for avalanche multiplication factor. Compared with the available experimental data, the proposed model provides accurate description of the output characteristics over a wide range of bias voltages. Based on the kink model, higher drain voltages or higher trap states density leads to higher avalanche multiplication factors. Ó 2009 Elsevier Ltd. All rights reserved.

Keywords: Polycrystalline silicon thin-film transistors Kink Surface potential

1. Introduction Polycrystalline silicon thin-film transistors (poly-Si TFTs) are getting more and more attractive for active-matrix liquid–crystal display (AMLCD) [1]. The polysilicon grain boundary traps and intra-grain defects introduce many significant differences and complicated characteristics, including kink effects in saturation region. As a result, it is important to accurately model their characteristics to determine their precise circuit behaviors. When the drain voltage is high enough, due to the impact ionization occurring in the high electric field near the drain end, anomalous increasing drain current in saturation has been observed, known as kink effect [2]. Some existing models for kink effects in poly-Si TFTs are built on the MOSFET substrate current model with slight modifications [3,4]. Several other authors have taken floating body effect into account, but the derived models for kink effect in poly-Si TFTs are very similar to the SOI kink models [5,6]. Chen et al. [7] used a quasi-two-dimensional approach to explain the kink effect. This kink model is physical-based and extremely valuable. However, the model of Chen relies on a simplifying assumption such as the use of a single effective trap energy level. An exponential density of states (DOS) continuous in energy was determined by various experiments [8]. Thus, monoenergetic traps model is invalid. To better understand the physical effects which influence the kink effect, several authors [2,9,10] have performed two-dimen-

sional numerical simulations. However, analytical formulas are not given in their models. Several other authors [11] have investigated the influence of trap states on the kink effect. In fact, there are only a few models of kink effect in poly-Si TFTs are presented in the literature accounting for the high density of trap states. In this paper, we studied the kink effect on the electrical characteristics. A quasi-two-dimensional approach and an impact ionization model are used in modeling. An exponential trap state density has been taken into account when modeling the kink effect. Finally, an accurate and analytical drain current model is developed and compared with experimental data.

2. Kink effect The kink effect is caused by impact ionization in the pinch-off region of length DL. Kink effect is much more pronounced in poly-Si TFTs. Due to the high electric field region at the drain end of the channel, electron–hole pairs are generated by impact ionization and result in anomalous increasing drain current in post-saturation region. To derive the expression for the electric field calculation in pinch-off region, our model makes use of a quasitwo-dimensional approach [7,12,13]. Applying Gauss’s law to a rectangular box in the depleted region near the drain, as shown in Fig. 1, we get [7]

q * Corresponding author. Tel.: +86 020 85222481; fax: +86 020 85220231. E-mail address: [email protected] (W. Deng). 0038-1101/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2009.03.011

Z 0

y

Z 0

tf

ðNTA þ nÞdxdy ¼

Z 0

tf

ðep Ey  ep Ey0 Þdx 

Z

y

eOX EOX dy

0

ð1Þ

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W. Deng, X. Zheng / Solid-State Electronics 53 (2009) 669–673

where VT is the threshold voltage of poly-Si TFT. The value of VT can be extracted as described in Appendix A. Consequently, differentiating both sides of Eq. (4), one obtains

NTA0 E1 exp





ws E1 =q

tf gC OX ðV G  V fb  ws Þ 2

¼

d ws dy

2

þ

þ

C OX

ep tf

ðV G  V T  V sat Þ

C OX ðV G  V fb  ws Þ ep tf 

2

ð9Þ 



2

d ws d dws s ¼ dy Using the formula 2 dw and Eq. (9), the electric dy dy dy2 field in the y direction near the drain becomes

Fig. 1. Cross section of an n-channel poly-Si TFT biased in the saturation region. The kink effect occurs through the length DL.

where ep is the polysilicon permittivity, tf is the thin film thickness, Ey0 is the y direction electric field at the saturation point (y = 0), where the channel potential reaches the saturation voltage Vsat, Ey is the lateral electric field at location y, eOX is the oxide permittivity, EOX is the vertical electric field at the surface, n is the free charge density, and N  TA is the density of ionized trapped charge. In Eq. (1), we have assumed that the electric field flux flowing from the Gauss box to the substrate is negligible. EOX can be written as

EOX ¼

C OX ðV G  V fb  ws Þ

ð2Þ

eOX

where COX is the unit area gate oxide capacitance, Vfb is the flat-band voltage, and ws is the surface potential. Assuming Ey is constant over the depth of the channel [13], Ey can be expressed as

dw dw ¼ s dy dy

Ey ¼ 

ð3Þ

Substituting Eqs. (2) and (3) into Eq. (1), yields

Z

q

ep tf

y

0

  Z y dws 1 ðN T þ Nn Þdy ¼ C ðV  V fb  ws Þdy þ Ey0 þ dy ep tf 0 OX G

i 2q C OX h ðwsy  V 0 Þ2  ðwsat  V 0 Þ2 þ ep tf ep tf

E2y ¼

Z

wsy

NT dws þ E2y0

where wsy is the surface potential at location y, wsat is the surface potential at the saturation point, and V0 = VT + Vsat  Vfb . Analogous to Eq. (10), lateral electric field at the drain end EyL can be obtained as

E2yL ¼

i 2q C OX h ðwsL  V 0 Þ2  ðwsat  V 0 Þ2 þ ep tf ep tf

Z

wsL

NT dws þ E2y0

where wsL is the surface potential at the drain. The integral in Eq. (11) is rewritten as

Z

wsL

wsat

NTA0 E1 =q NT dws ¼ gC OX =ep

Z

wsL

wsat

exp



ws E1 =q



V G  V fb  ws

dws

NT ¼

0



NTA dx ¼

Z

ws

0

1

NTA dw dw=dx Z ws

gC OX ðV G  V fb  ws Þ=ep

0

NTA dw

Z

     NTA0 ðE1 =qÞ2 wsL wsat exp  exp gC OX -=ep E1 =q E1 =q      NTA0 ðE1 =qÞ2 wsat þ V D  V sat wsat exp   exp gC OX -=ep E1 =q E1 =q

wsL

N T dws 

wsat

ð13Þ

ð5Þ

In Eq. (5), when estimating NT, we have assumed that the vertical electric field in depth of the channel is constant and equals to gCOX(VG  Vfb  ws)/ep, where g is a fitting parameter (g < 1). When considering a single exponential DOS distribution in the upper half of the gap, the N  TA expression [14] was substituted into Eq. (5) and integrated, we get

NTA0 E1 =q







 1

ws exp E1 =q   NTA0 E1 =q ws  exp gC OX ðV G  V fb  ws Þ=ep E1 =q   pkT EF0  q/n  EC exp NTA0 ¼ g c1 sinðpkT=E1 Þ E1 NT ¼

gC OX ðV G  V fb  ws Þ=ep

ð6Þ ð7Þ

where gc1 is the states density, and E1 is the inverse slope of states. These two parameters determine the value of DOS in polysilicon film. The physical meanings of other parameters in Eqs. (6) and (7) can be found in Ref. [14]. Nn in the left-hand side of Eq. (4) means the free charges in the Gauss box. Nn can be described as [7]

Nn ¼

C OX ðV G  V T  V sat Þ q

ð12Þ

We used numerical integration to evaluate Eq. (12), and found that the logarithm of the result of Eq. (12) versus ws could be approximated by a linear function. The results of Eq. (12) have a strong function of exp [ws/(E1/q)]. Hence, one should expect the following approximation:

ð4Þ tf

ð11Þ

wsat

where NT is the trapped charges. NT can be calculated by

Z

ð10Þ

wsat

ð8Þ

where - is a parameter fitting the magnitude of approximation of Eq. (12). Using Taylor expansion formula, Eq. (13) can be reduced to

Z

wsL

wsat

NT dws 

  NTA0 ðE1 =qÞ2 wsat exp gC OX -=ep E1 =q "  2  3 # V D  V sat 1 V D  V sat 1 V D  V sat  þ þ 2 6 E1 =q E1 =q E1 =q ð14Þ

where the higher order terms in the Taylor’s series have been neglected, and the channel potential used in the calculation of NTA0 is equal to Vsat. The drain current without accounting for the kink effect ID is given by our previous work [15]

W l fRðwsL Þ  Rðwss Þ  /t ½Q i ðwsL Þ  Q i ðwss Þg L eff   2/t /eff ðws Þ 3/ ðw qb2 eff s Þ  ðV  V  w Þ Rðws Þ ¼ G fb s 2/t 2 3/eff ðws Þ  2/t ðb1 Þ /eff ðws Þ  2/ 2/ðwt Þ eff s V G  V fb  ws Q i ðws Þ ¼ qb2 b1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi   2qesi ni /t EF0 =q exp b1 ¼ C OX 2/t ID ¼

ð15Þ ð16Þ

ð17Þ ð18Þ

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W. Deng, X. Zheng / Solid-State Electronics 53 (2009) 669–673

where wss is the surface potential at the source end, /t = kT/q is the thermal voltage, k is Boltzmann constant, and T is the temperature in Kelvin. The effective mobility leff in Eq. (15) has a physical form of [14,16]:

l0  expðV b =/t Þ

ln ¼

1 þ h1 ðV G Þ1=3 þ h2 ðV G Þ2 h i12 V b ¼ ðV G  V i Þ2 þ V 2Q  ðV G  V i Þ

ð19Þ ð20Þ

where Vi and VQ are the fitting potential barrier height parameters, h1 and h2 are mobility degradation parameters caused by phonon scattering and surface roughness scattering, respectively. As explained in Ref. [3], in low gate biases range, an increase of mobility is observed. A smaller value of VQ leads to a steeper increase. Similarly, Vi determines the location of VG where mobility starts to increase significantly. Furthermore, the lateral electric field at the saturation point Ey0 in Eqs. (10) and (11) is expressed as [13]

Ey0 ¼

Idss

ð21Þ

leff Q i ðwss ÞW

where Idss is the drain current at the saturation point which can be calculated using Eq. (15) by replacing wsL with wsat. As a result, from Eqs. (11), (14), and (21), the quasi-two-dimensional model of lateral electric field at the drain end has been described. In the pinch-off region, the current increased due to impact ionization can be modeled by the avalanche multiplication factor M, which is strongly related to the lateral electric field in the device. Using the integral of the impact ionization generation rate through length DL in Fig. 1, M is obtained as [7]

M¼

Z



DL

a exp 

0

 b dy jEy j

ð22Þ

where a and b are called the ionization constants. The one-dimensional (y direction) model for the impact ionization rate is used here, which is actually a two-dimensional variable. However, with the fitting ionization constants a and b, this one-dimensional model of the impact ionization rate can give a representative characterization of the kink current [17]. Eq. (22) can be rewritten as [7]

M¼

Z

VD

V sat

  b dV exp  jEy j jEy j

a

  m1 1=m1 VD V sateff ¼ V D 1 þ V sat

ð30Þ

where parameter m1 controls the transition from VD to Vsat, with Vsat = asatVG. Here asat is an adjustable parameter. 3. Results and discussion As indicated in the previous sections, the kink effect of poly-Si TFTs has been modeled. To verify the proposed models, comparison with available experimental data from different TFTs has been completed. The parameters of these TFTs used in simulation are listed in Table 1. The first validation is achieved by comparing our model with experimental data [18] with W/L = 10 lm/10 lm. As shown in Fig. 2, the model simulation results match well with the experimental data. When the applied VDS is further increased and the device operates at post-saturation region, kink effect becomes significant and the drain current keeps rising with increasing VDS. The corresponding plot of the avalanche multiplication factor Mkink versus gate voltage for different values of VDS is presented in Fig. 3. As shown in the figure, for a constant drain voltage, as the gate voltage increases, Mkink decreases due to reduction of the lateral electric field at the drain EyL. Fig. 4 illuminates Mkink versus drain voltage for various VG. A higher VDS leads to a larger Mkink since the EyL becomes larger. However, in triode region (low VDS), impact ionization level is so low that kink effect can be negligible. Fig. 5 shows Mkink versus VG for various gc1, where gc1 is the trap state density. As indicated in the figure, an exponential DOS strongly affects Mkink, and higher density of traps leads to a higher avalanche multiplication factor. This predicting is consistent with the analysis in Ref. [7]. The second validation of the derived model is employed by a comparison with experimental data from Ref. [19]. From Fig. 6, it

ð23Þ

The above integral has no closed-form solution. However, following the approximation used in Ref. [17], and performing the integration yields

  2 b   1 b 2a jEyL j exp  jEyL j M¼ exp  ¼ S jEyL j jEyL j ðb=jEy jÞ0 jV¼V D b " # 2 ðV D  V sat Þ V D  V sat 1 þ 2k1 ½V D þ wss  V 0  þ þ S ¼ k0 3 2 E 1 =q 2ðE1 =qÞ ðE1 =qÞ   2qN TA0 ðE1 =qÞ2 wsat exp k0 ¼ gtf C OX E1 =q C OX k1 ¼ ep tf

a

ð24Þ ð25Þ ð26Þ ð27Þ

To guarantee that M only has an effect on the electrical characteristic in saturation region and can be negligible in the triode region, a smoothing function is employed. Therefore, the total drain current considering kink effect is given by

IDS ¼ ðM kink þ 1ÞID 2

where f is a fitting parameter. wsL and wss are the surface potentials at the drain and the source, respectively, which are calculated using the approach we proposed in Ref. [15]. Similarly, wsat can be solved using the same approach by replacing the channel potential with Vsateff, which is given by

Table 1 Parameters for simulationa. Symbol (units)

TFTs in Figs. 2–5

TFTs in Fig. 6

W (lm) L (lm) tf (lm) COX (F/cm2) gc1 (cm3 eV1) E1 (eV) EF0 (eV) Vfb (V) l0 (cm2 V1 s1) h1 (V1/3) h2 (V2) VQ (V) Vi (V) VT (V) a (cm1) b (V/cm) - (V)

10 10 0.2 2.93  107 8  1019 0.12 0.01 2 400 0.1 8  103 0.08 0.4 0.94 106 2.5  106 3 0.5 4 0.01 1

49.5 9.5 0.1 8.78  108 7  1018 0.17 0.05 0 190 0 7  104 0.8 0.2 3.17 1.5  105 2  106 3 0.5 4 0.01 0.7

g

3

V D  V sat 61 7 M kink ¼ M4 þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi5 2 2 ðV D  V sat Þ þ f

ð28Þ ð29Þ

m and m1 f

asat

a The value of the poly-Si thin film thickness tf of Fig. 2 was not stated in Ref. [18], and we preset it to a typical value.

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W. Deng, X. Zheng / Solid-State Electronics 53 (2009) 669–673

Fig. 2. Comparison of drain current between model results and experimental data [18] with W/L = 10 lm/10 lm.

Fig. 5. Variation of Mkink with gate voltage for different values of gc1, obtained using the parameters of Fig. 2.

Fig. 3. Variation of Mkink with gate voltage for different values of drain-to-source voltages, obtained using the parameters of Fig. 2.

Fig. 6. Comparisons of experimental data [19] and modeled I–V characteristics for the W/L = 49.5 lm/9.5 lm poly-Si TFT.

can be clearly seen that the kink effect is perfectly predicted by our model. 4. Conclusions In this paper, by taking the kink effect into account, an extended I–V model for poly-Si TFTs was developed and verified. Our model has distinctive features. First, the analytical approximation for the avalanche multiplication factor is derived by using the quasi-twodimensional approach and considering an exponential trap state density. Second, the obtained avalanche multiplication factor is strongly dependent on the lateral electric field at the drain and the density of trap states. Third, the combined model accurately reproduces the output characteristics of poly-Si TFTs. Fourth, the model is suitable for use in device and circuit simulations. Appendix A. Extraction of VT Fig. 4. Variation of Mkink with drain-to-source voltage for different values of gate voltage, obtained using the parameters of Fig. 2.

For an either undoped or lightly doped poly-Si TFT, one-dimensional Poisson’s equation can be obtained as [14]

W. Deng, X. Zheng / Solid-State Electronics 53 (2009) 669–673 2

d w 2

dx

¼

q

esi

ðn þ NTA Þ

ðA1Þ

Using Gauss’s law application, the surface potential in subthreshold region wsub can be approximated by

V G  V fb  wsub

pffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi     2qesi E1 wsub ¼ NTA0 exp 1 C OX q E1 =q

ðA2Þ

The surface potential in strong inversion region wstr can be approximated by

pffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi    ffi 2qesi wstr n0 /t exp 1 /t C OX   /n þ EF0 =q n0 ¼ ni exp /t V G  V fb  wstr ¼

ðA3Þ ðA4Þ

Parameter VT can be calculated corresponding to the condition of equal values of wsub and wstr, that is, Eqs. (A2) and (A3) intersect at VG = VT. Therefore, when neglecting ‘‘1” term in Eqs. (A2) and (A3), we have

ln½NTA0 ðE1 =qÞ=ðn0 /t Þ 1=/t  q=E1 pffiffiffiffiffiffiffiffiffiffiffi   E1 =q p 2qesi ffiffiffiffiffiffiffiffiffiffi NTA0 E1 =q 2ðE1 =q/t Þ n0 /t þ C OX n0 /t

V T ¼V fb þ

ðA5Þ

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