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Studies on the formation of source and drain in low temperature polycrystalline silicon thin film transistors
Current Applied Physics 13 (2013) S182eS185
Contents lists available at SciVerse ScienceDirect
Current Applied Physics journal homepage: www.elsevier.com/locate/cap
Studies on the formation of source and drain in low temperature polycrystalline silicon thin film transistors Yong Woo Lee, Gui Fu Yang, A. Mallikarjuna Reddy, Chang Woo Byun, Se wan Son, Seung Jae Yun, Seung Ki Joo* Research Institute of Advanced Materials (RIAM), Department of Materials Science and Engineering, Seoul National University, Seoul 151-744, Republic of Korea
a r t i c l e i n f o
a b s t r a c t
Article history: Received 5 November 2012 Accepted 24 December 2012 Available online 19 January 2013
The source and drain regions were formed successfully by dopant induced crystallization method for top gate poly silicon thin film transistors. It was found that the resistance of source and drain varies with respect to dopant concentration and the grain boundary influence on resistance at different doses was intensively studied in this work. In the present study, boron was doped by ion mass doping (IMD) and PECVD and the resistance of 230 U was the doping condition of 2 keV 1 min and 17 keV 10 min in ion mass doping method. Thin film transistor by DIC exhibited a field effect mobility of 56 cm2/V s, leakage current of 4.1 1011 A, slope of 0.84 V/dec, Ion of 2.7 104 A, Vth of 6.5 V at Vd ¼ 10 V In crystallization of in situ A. N type poly Si of 1000 A has 270 U in in-situ boron doped a-Si, 80 U in resistance was obtained at 1000 doping method. In-situ doped a-Si deposited by PECVD was further doped by using IMD. And the resistance was lowered by 10e20 U. Bottom gate thin film transistors fabricated by metal induced lateral crystallization (MILC) exhibits a field effect mobility of 26 cm2/V s, leakage current of 1.34 1010 A, slope of 0.7 V/dec, Ion of 1.02 104 A, Vth of 4.5 V at Vd ¼ 10 V. Ó 2013 Elsevier B.V. All rights reserved.
Keywords: Dopant induced crystallization Ion mass doping PECVD Grain boundary TFTs Source and drain MILC
1. Introduction Recently display market was moved from active-matrix liquid crystal display (AMLCD) to active-matrix organic light-emitting diodes (AMOLEDs) due to low driving voltage, large viewing angle, high definition, fast response time. Due to low mobility a-Si TFTs are not suitable for driving TFTs in AMOLED. The Polycrystalline silicon (Poly-Si) TFTs [1e4] having high mobility are suitable for AMOLED. a-Si thin film can be crystallized by many kinds of methods, such as solid phase crystallization (SPC), direct deposition, rapid thermal annealing (RTA), liquid phase re-crystallization, excimer laser annealing (ELA) and so on. Among the various crystallization methods, ELA method is much more preferable for fabricating low temperature poly-Si TFTs on a glass substrate. However, it still has many unsolved problems, such as uniformity and manufacturing cost. Scientifically speaking, however, since it involves melting and freezing of silicon the poly silicon by a laser scanning should have the physical properties of a high temperature poly. Although solid-phase crystallization is a relatively inexpensive process, the processing temperature of around 600 C
* Corresponding author. E-mail address: [email protected] (S.K. Joo). 1567-1739/$ e see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.cap.2012.12.030
still exceeds an upper temperature limit of low-cost glass substrate. Hence, we cannot find many research works on the electrical and physical properties of LTPS. One of the important factors in determining the electrical performance of TFT is formation of source and drain. In this paper, source and drain were formed by ion mass doping and PECVD. We have investigated minimum doping condition for crystallization and methods for reducing resistance in source and drain by ion mass doping (IMD). P-type top gate TFTs were fabricated by dopant induced crystallization (DIC) [5]. In PECVD, resistance in P type and N type was investigated by MILC. Also Petype bottom gate TFTs were fabricated by MILC. 2. Experiment In this study, thin film transistors were successfully fabricated on corning 7059 glass substrate by dopant induced crystallization. A-3000 A thick SiO2 thin film was deposited as a buffer layer by plasma enhanced chemical vapor deposition (PECVD). A-1000 A thick a-Si thin film was deposited by low pressure chemical vapor deposition at 550 C using SiH4 as the precursor. a-Si thin film was doped by ion mass doping (IMD). Resistance and crystallization was studied in various doping conditions. After patterning the a-Si film to form active islands, 1000 A thick SiNx film was deposited as a gate insulator and 2000 A thick MoW film was deposited as
Y.W. Lee et al. / Current Applied Physics 13 (2013) S182eS185 Table 1 Minimum doping condition for crystallization.
S183
doping
DC voltage
Resistance
Crystallization
15 keV 1 min 13 keV 1 min 10 keV 1 min 5 keV 1 min 2 keV 1 min
573 682 750 1224 Over range
B B B B B
Symbol B means crystallization occured.
a gate electrode by PECVD and sputtering, respectively. Lightly doping was applied to crystallization S/D region. And heavily doping was used for electrical behavior of thin film transistor. After individual doping process, annealing process was followed each time. Annealing was processed in H2 ambient at 550 C for 2 h. And a 300 nm thick SiO2 layer was deposited in glass. The samples were then deposited with 100 nm thick a-Si layer with SiH4 gas. The dopant gases used were PH3 for n-type and B2H6 for P-type. In our work, the flow rate of SIH4 was kept at 100 sccm and the flow rates of PH3 and B2H6 were kept at 1 sccm and 2 sccm. The RF power, substrate temperature and total pressure during deposition of a-Si were 100 W, 350 C and 300 m Torr, respectively. P type-Bottom gate TFT was fabricated with dual layers. Pþ layer was deposited by PECVD. Intrinsic layer was deposited by LPCVD. 3. Result and discussion In Table 1, crystallization and resistance was checked. In 5 keV of 1 min, a-Si was crystallized. And in 2 keV 1 min and 1 keV of 8 min, a-Si was crystallized. Resistance wasn’t measured in 1 keV 8 min and 2 keV 1 min due to over range to measure resistance. We know minimum condition of boron doping for crystallization. Fig. 1 shows resistance of S/D region by DIC (dopant induced crystallization). In first doping, 10 keV 1 min condition is not adequate to activate electrically. After second heavy doping, resistance in 10 keV 1 min drastically increased. It is deduced that grain boundary scattering has role in increasing resistance due to captured dopant in G.B. To form S/D region, S/D resistance must be low for good electrical performance in TFT. It is not good condition to form S/D of more doping. Because of dopant segregation and G.B scattering, these prevent carrier from moving electrically. So heavy doping is not necessary to form S/D region [6]. Fig. 2 shows schematics about thin film transistor. Here we apply the minimum doping condition at 2 keV 1 min. In this case,
doping
Gate metal
Gate insulator
a-Si
Glass
Fig. 2. Schematics about thin film transistor by DIC (dopant induced crystallization).
channel region also was crystallized without Ni. It was deduced that channel region was crystallized by thermal stress. Like SPC, crystallization of a-Si was generated by heating. Stress has an important role in lateral crystallization speed. It is reported MILC rate is different by two type stresses [7]. It is thought crystallization of channel region was related to stress. Also it is necessary to study mechanism in crystallization of channel without Ni in 550 C annealing. Fig. 3 shows characteristics in TFT by DIC. In this work, DIC was used for crystallization of S/D region in poly Si TFT. Improvement in leakage current was showed due to no Ni in channel region. And Slope is similar to conventional MILC TFT. Thin film transistor (W/ L ¼ 10/10) by DIC exhibits a field effect mobility of 56 cm2/V s, leakage current of 4.1 1011 A, slope of 0.84 V/dec, Ion of 2.7 104 A at Vd ¼ 10 V, and Vth of 6.5 V. As Drain voltage increase, leakage current also increases. In DIC TFT, more electrical filed between gate voltage and drain voltage induce to generate captured hole for increasing leakage current [8]. DIC TFT has 231 U in S/ D region. 1st doping condition is 2 keV 1 min to crystallize S/D. 2nd doping condition is 17 keV 10 min to reduce resistance of S/D. Thorough the experiment, we knows 2 times doping has reduction in resistance. It is natural to reduce resistance in additional doping due to more dopant concentration. And S/D resistance is important to operate TFT. S/D resistance is related to slope and on current in TFT performance. So S/D region is applicable to condition of 2 keV 1 min and 17 keV 10 min. In comparison with MILC TFT, S/D region’s resistance DIC is higher than resistance by MILC. In MILC, S/D region
Fig. 1. After minimum doping for crystallization, resistance was changed (1 keV 8 min, 2 keV 1 min, 5 keV 1 min, 10 keV 1 min).
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Fig. 3. Performance in TFT by DIC (W/L ¼ 10/10, W/L ¼ 10/20).
resistance has 180e200 U by ion mass doping. In that point, it is necessary to study reduction of resistance in S/D region. Off current and on current were reduced due to increments in length like conventional TFT. Fig. 4 shows experiments about checking lateral crystallization by DIC. Nitride 1000 Å was used as blocking layer of doping in ion mass doping. We check lateral crystallization was not generated like Figs. 5 and 6. Figs. 5 and 6 show crystallization by DIC. It is reported by Guifu Yang at EML. Crystallization by DIC has needle shape. In Figs. 5 and 6 blue color region means crystallization of a-Si by DIC. Orange color region means a-Si region. Regardless of doping level, crystallization behavior is similar.
In Table 2, In-situ boron doped poly Si has 80 U in resistance. With additional heavy doping of ion mass doping, resistance in P type poly Si of 1000 Å has 60 U. N-type poly Si of 1000 Å has 270 U and 260 U. Like Table 1, in situ doped poly Si has lower resistance than poly Si in ion mass doping method. Due to this reason, in situ
Nitride
Fig. 4. Schematics of confirmation in lateral crystallization by DIC. Fig. 6. Crystallization by DIC in microscope (doping condition ¼ 5 keV 2 min).
Table 2 Resistance in in situ doped poly Si (P type/N type).
Resistance (1000 A)
Fig. 5. Crystallization by DIC in microscope (doping condition ¼ 3 keV 2 min).
Pþ layer/Pþ layer þ IMD
Nþ layer/Nþ layer þ IMD
80e100 U/60 U
270 U/260 U
Fig. 7. Schematics of P type bottom gate poly Si TFT.
Y.W. Lee et al. / Current Applied Physics 13 (2013) S182eS185 -3
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Fig. 8. Electrical characteristics of P type bottom gate TFT by MILC (W/L ¼ 10/10).
doping was applicable to S/D in Poly TFT. Without Ni, P-type and N type Si has unlimited resistance and was not crystallized. In RTA annealing of 570 C 10 min, Resistance has 130 U to that in furnace annealing. It is thought high temperature in N type Si has role in reducing resistance. But in RTA annealing, glass was shrinkaged. Set value in temperature was higher than expected due to glass deformation. Unlike DIC, in situ doped a-Si in PECVD was not crystallizes at 550 C of 2 h. Intensive study was needed for mechanism of DIC phenomenon in low temperature. Fig. 7 shows bottom gate structure. Fig. 8 shows characteristics of bottom gate TFT. Bottom gate TFT has LDD structure [9e12]. Doping method is in situ doping of PECVD. In the left figure, Pþ region of Drain region is overlapped. In the right figure, drain region is not overlapped. The phenomenon was generated in the same sample due to misalignment. Intrinsic layer is deposited by LPCVD. a-Si deposited by PECVD was not crystallized than that by LPCVD. Thin film transistor exhibits a field effect mobility of 26 cm2/V s, leakage current of 1.34 1010 A, slope of 0.7 V/dec, Ion of 1.02 104 A at Vd ¼ 10 V, and Vth of 4.5 V. 4. Conclusions Condition of doping was investigated for formation of source and drain (S/D) in TFT. The condition is 2 keV 1 min to crystallize a-Si thin film. The lower concentration of doping in 1st doping, the lower resistance in source and drain (S/D) in additional heavy doping. The excessive doping has role in disturbance of carrier in movement due to G.B scattering. Without Ni, poly-Si TFT was fabricated by dopant induced crystallization. The field effect mobility was obtained at 56 cm2/Vs. With more electrical fields between gate voltage and drain voltage, there was pinning phenomenon like MILC-TFT. In deposition of PECVD, in situ
doped poly Si was obtained by MILC, P type and N type in resistance has 80 U and 270 U respectively. In situ doping method is applicable to form S/D region in poly TFT due to low resistance. With additional doping in ion mass doping, resistance was lowered in P type and N type. Also bottom gate TFT was fabricated with in-situ doping method instead of ion mass doping (IMD). We confirmed LDD structure is needed in bottom gate poly Si TFT. Off set in drain region reduce the leakage due to reduction in lateral field. Acknowledgments The authors would like to thank the National Foundation of Korea (Grant RIAMI- AM37-11), NeoePoly Inc., and Eui-San Research Center at Seoul National University for the process support. References [1] F. Oki, Y. Ogawa, Y. Fujiki, Japanese Journal of Applied Physics 8 (1969) 1056. [2] S.W. Lee, S.K. Joo, IEEE Electron Device Letters 17 (4) (April.1996) 160e162. [3] C.W. Byun, S.W. Son, Y.W. Lee, S.K. Joo, Electronic Materials Letters 8 (3) (2012) 251e258. [4] C.W. Byun, S.W. Son, Y.W. Lee, H.M. Kang, S.A. Park, W.C. Lim, T. Li, S.K. Joo, Electronic Materials Letters 8 (2) (2012) 107e110. [5] G.F. Yang, Y.W. Lee, S.K. Joo, Electronic Materials Letters 8 (2) (2012) 191e196. [6] Y.W. Lee, S.J. LEE, S.J. Yun, S.K. Joo, Current Applied Physics 11 (2011) S158e S162. [7] N.K. Song, M.S. Kim, S.H. Han, Y.S. Kim, S.K. Joo, Journal of Electrochemical Society 154 (5) (2007) H370eH373. [8] Y. Kuo, Thin Film Transistors Material and Processes, vol. 2, p. 41. [9] L. Jung, J. Damiano Jr., J.R. Zaman, S. Batra, M. Manning, S.K. Banerjee, Solid-State Electronics 38 (12) (1995) 2069e2073. [10] Shengdong Zhang, Ruqi Han, Mansun J. Chan, IEEE Electron Device Letters 22 (8) (AUGUST 2001). [11] I.C. Lee, T.Y. Ma, Thin Solid Films 461 (2004) 336e339. [12] S.W. Son, C.W. Byun, S.J. Lee, S.J. Yoon, S.K. Joo, Journal of Nanoscience and Nanotechnology 12 (2012) 3195e3199.
Contents lists available at SciVerse ScienceDirect
Current Applied Physics journal homepage: www.elsevier.com/locate/cap
Studies on the formation of source and drain in low temperature polycrystalline silicon thin film transistors Yong Woo Lee, Gui Fu Yang, A. Mallikarjuna Reddy, Chang Woo Byun, Se wan Son, Seung Jae Yun, Seung Ki Joo* Research Institute of Advanced Materials (RIAM), Department of Materials Science and Engineering, Seoul National University, Seoul 151-744, Republic of Korea
a r t i c l e i n f o
a b s t r a c t
Article history: Received 5 November 2012 Accepted 24 December 2012 Available online 19 January 2013
The source and drain regions were formed successfully by dopant induced crystallization method for top gate poly silicon thin film transistors. It was found that the resistance of source and drain varies with respect to dopant concentration and the grain boundary influence on resistance at different doses was intensively studied in this work. In the present study, boron was doped by ion mass doping (IMD) and PECVD and the resistance of 230 U was the doping condition of 2 keV 1 min and 17 keV 10 min in ion mass doping method. Thin film transistor by DIC exhibited a field effect mobility of 56 cm2/V s, leakage current of 4.1 1011 A, slope of 0.84 V/dec, Ion of 2.7 104 A, Vth of 6.5 V at Vd ¼ 10 V In crystallization of in situ A. N type poly Si of 1000 A has 270 U in in-situ boron doped a-Si, 80 U in resistance was obtained at 1000 doping method. In-situ doped a-Si deposited by PECVD was further doped by using IMD. And the resistance was lowered by 10e20 U. Bottom gate thin film transistors fabricated by metal induced lateral crystallization (MILC) exhibits a field effect mobility of 26 cm2/V s, leakage current of 1.34 1010 A, slope of 0.7 V/dec, Ion of 1.02 104 A, Vth of 4.5 V at Vd ¼ 10 V. Ó 2013 Elsevier B.V. All rights reserved.
Keywords: Dopant induced crystallization Ion mass doping PECVD Grain boundary TFTs Source and drain MILC
1. Introduction Recently display market was moved from active-matrix liquid crystal display (AMLCD) to active-matrix organic light-emitting diodes (AMOLEDs) due to low driving voltage, large viewing angle, high definition, fast response time. Due to low mobility a-Si TFTs are not suitable for driving TFTs in AMOLED. The Polycrystalline silicon (Poly-Si) TFTs [1e4] having high mobility are suitable for AMOLED. a-Si thin film can be crystallized by many kinds of methods, such as solid phase crystallization (SPC), direct deposition, rapid thermal annealing (RTA), liquid phase re-crystallization, excimer laser annealing (ELA) and so on. Among the various crystallization methods, ELA method is much more preferable for fabricating low temperature poly-Si TFTs on a glass substrate. However, it still has many unsolved problems, such as uniformity and manufacturing cost. Scientifically speaking, however, since it involves melting and freezing of silicon the poly silicon by a laser scanning should have the physical properties of a high temperature poly. Although solid-phase crystallization is a relatively inexpensive process, the processing temperature of around 600 C
* Corresponding author. E-mail address: [email protected] (S.K. Joo). 1567-1739/$ e see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.cap.2012.12.030
still exceeds an upper temperature limit of low-cost glass substrate. Hence, we cannot find many research works on the electrical and physical properties of LTPS. One of the important factors in determining the electrical performance of TFT is formation of source and drain. In this paper, source and drain were formed by ion mass doping and PECVD. We have investigated minimum doping condition for crystallization and methods for reducing resistance in source and drain by ion mass doping (IMD). P-type top gate TFTs were fabricated by dopant induced crystallization (DIC) [5]. In PECVD, resistance in P type and N type was investigated by MILC. Also Petype bottom gate TFTs were fabricated by MILC. 2. Experiment In this study, thin film transistors were successfully fabricated on corning 7059 glass substrate by dopant induced crystallization. A-3000 A thick SiO2 thin film was deposited as a buffer layer by plasma enhanced chemical vapor deposition (PECVD). A-1000 A thick a-Si thin film was deposited by low pressure chemical vapor deposition at 550 C using SiH4 as the precursor. a-Si thin film was doped by ion mass doping (IMD). Resistance and crystallization was studied in various doping conditions. After patterning the a-Si film to form active islands, 1000 A thick SiNx film was deposited as a gate insulator and 2000 A thick MoW film was deposited as
Y.W. Lee et al. / Current Applied Physics 13 (2013) S182eS185 Table 1 Minimum doping condition for crystallization.
S183
doping
DC voltage
Resistance
Crystallization
15 keV 1 min 13 keV 1 min 10 keV 1 min 5 keV 1 min 2 keV 1 min
573 682 750 1224 Over range
B B B B B
Symbol B means crystallization occured.
a gate electrode by PECVD and sputtering, respectively. Lightly doping was applied to crystallization S/D region. And heavily doping was used for electrical behavior of thin film transistor. After individual doping process, annealing process was followed each time. Annealing was processed in H2 ambient at 550 C for 2 h. And a 300 nm thick SiO2 layer was deposited in glass. The samples were then deposited with 100 nm thick a-Si layer with SiH4 gas. The dopant gases used were PH3 for n-type and B2H6 for P-type. In our work, the flow rate of SIH4 was kept at 100 sccm and the flow rates of PH3 and B2H6 were kept at 1 sccm and 2 sccm. The RF power, substrate temperature and total pressure during deposition of a-Si were 100 W, 350 C and 300 m Torr, respectively. P type-Bottom gate TFT was fabricated with dual layers. Pþ layer was deposited by PECVD. Intrinsic layer was deposited by LPCVD. 3. Result and discussion In Table 1, crystallization and resistance was checked. In 5 keV of 1 min, a-Si was crystallized. And in 2 keV 1 min and 1 keV of 8 min, a-Si was crystallized. Resistance wasn’t measured in 1 keV 8 min and 2 keV 1 min due to over range to measure resistance. We know minimum condition of boron doping for crystallization. Fig. 1 shows resistance of S/D region by DIC (dopant induced crystallization). In first doping, 10 keV 1 min condition is not adequate to activate electrically. After second heavy doping, resistance in 10 keV 1 min drastically increased. It is deduced that grain boundary scattering has role in increasing resistance due to captured dopant in G.B. To form S/D region, S/D resistance must be low for good electrical performance in TFT. It is not good condition to form S/D of more doping. Because of dopant segregation and G.B scattering, these prevent carrier from moving electrically. So heavy doping is not necessary to form S/D region [6]. Fig. 2 shows schematics about thin film transistor. Here we apply the minimum doping condition at 2 keV 1 min. In this case,
doping
Gate metal
Gate insulator
a-Si
Glass
Fig. 2. Schematics about thin film transistor by DIC (dopant induced crystallization).
channel region also was crystallized without Ni. It was deduced that channel region was crystallized by thermal stress. Like SPC, crystallization of a-Si was generated by heating. Stress has an important role in lateral crystallization speed. It is reported MILC rate is different by two type stresses [7]. It is thought crystallization of channel region was related to stress. Also it is necessary to study mechanism in crystallization of channel without Ni in 550 C annealing. Fig. 3 shows characteristics in TFT by DIC. In this work, DIC was used for crystallization of S/D region in poly Si TFT. Improvement in leakage current was showed due to no Ni in channel region. And Slope is similar to conventional MILC TFT. Thin film transistor (W/ L ¼ 10/10) by DIC exhibits a field effect mobility of 56 cm2/V s, leakage current of 4.1 1011 A, slope of 0.84 V/dec, Ion of 2.7 104 A at Vd ¼ 10 V, and Vth of 6.5 V. As Drain voltage increase, leakage current also increases. In DIC TFT, more electrical filed between gate voltage and drain voltage induce to generate captured hole for increasing leakage current [8]. DIC TFT has 231 U in S/ D region. 1st doping condition is 2 keV 1 min to crystallize S/D. 2nd doping condition is 17 keV 10 min to reduce resistance of S/D. Thorough the experiment, we knows 2 times doping has reduction in resistance. It is natural to reduce resistance in additional doping due to more dopant concentration. And S/D resistance is important to operate TFT. S/D resistance is related to slope and on current in TFT performance. So S/D region is applicable to condition of 2 keV 1 min and 17 keV 10 min. In comparison with MILC TFT, S/D region’s resistance DIC is higher than resistance by MILC. In MILC, S/D region
Fig. 1. After minimum doping for crystallization, resistance was changed (1 keV 8 min, 2 keV 1 min, 5 keV 1 min, 10 keV 1 min).
S184
Y.W. Lee et al. / Current Applied Physics 13 (2013) S182eS185 -3
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Fig. 3. Performance in TFT by DIC (W/L ¼ 10/10, W/L ¼ 10/20).
resistance has 180e200 U by ion mass doping. In that point, it is necessary to study reduction of resistance in S/D region. Off current and on current were reduced due to increments in length like conventional TFT. Fig. 4 shows experiments about checking lateral crystallization by DIC. Nitride 1000 Å was used as blocking layer of doping in ion mass doping. We check lateral crystallization was not generated like Figs. 5 and 6. Figs. 5 and 6 show crystallization by DIC. It is reported by Guifu Yang at EML. Crystallization by DIC has needle shape. In Figs. 5 and 6 blue color region means crystallization of a-Si by DIC. Orange color region means a-Si region. Regardless of doping level, crystallization behavior is similar.
In Table 2, In-situ boron doped poly Si has 80 U in resistance. With additional heavy doping of ion mass doping, resistance in P type poly Si of 1000 Å has 60 U. N-type poly Si of 1000 Å has 270 U and 260 U. Like Table 1, in situ doped poly Si has lower resistance than poly Si in ion mass doping method. Due to this reason, in situ
Nitride
Fig. 4. Schematics of confirmation in lateral crystallization by DIC. Fig. 6. Crystallization by DIC in microscope (doping condition ¼ 5 keV 2 min).
Table 2 Resistance in in situ doped poly Si (P type/N type).
Resistance (1000 A)
Fig. 5. Crystallization by DIC in microscope (doping condition ¼ 3 keV 2 min).
Pþ layer/Pþ layer þ IMD
Nþ layer/Nþ layer þ IMD
80e100 U/60 U
270 U/260 U
Fig. 7. Schematics of P type bottom gate poly Si TFT.
Y.W. Lee et al. / Current Applied Physics 13 (2013) S182eS185 -3
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Fig. 8. Electrical characteristics of P type bottom gate TFT by MILC (W/L ¼ 10/10).
doping was applicable to S/D in Poly TFT. Without Ni, P-type and N type Si has unlimited resistance and was not crystallized. In RTA annealing of 570 C 10 min, Resistance has 130 U to that in furnace annealing. It is thought high temperature in N type Si has role in reducing resistance. But in RTA annealing, glass was shrinkaged. Set value in temperature was higher than expected due to glass deformation. Unlike DIC, in situ doped a-Si in PECVD was not crystallizes at 550 C of 2 h. Intensive study was needed for mechanism of DIC phenomenon in low temperature. Fig. 7 shows bottom gate structure. Fig. 8 shows characteristics of bottom gate TFT. Bottom gate TFT has LDD structure [9e12]. Doping method is in situ doping of PECVD. In the left figure, Pþ region of Drain region is overlapped. In the right figure, drain region is not overlapped. The phenomenon was generated in the same sample due to misalignment. Intrinsic layer is deposited by LPCVD. a-Si deposited by PECVD was not crystallized than that by LPCVD. Thin film transistor exhibits a field effect mobility of 26 cm2/V s, leakage current of 1.34 1010 A, slope of 0.7 V/dec, Ion of 1.02 104 A at Vd ¼ 10 V, and Vth of 4.5 V. 4. Conclusions Condition of doping was investigated for formation of source and drain (S/D) in TFT. The condition is 2 keV 1 min to crystallize a-Si thin film. The lower concentration of doping in 1st doping, the lower resistance in source and drain (S/D) in additional heavy doping. The excessive doping has role in disturbance of carrier in movement due to G.B scattering. Without Ni, poly-Si TFT was fabricated by dopant induced crystallization. The field effect mobility was obtained at 56 cm2/Vs. With more electrical fields between gate voltage and drain voltage, there was pinning phenomenon like MILC-TFT. In deposition of PECVD, in situ
doped poly Si was obtained by MILC, P type and N type in resistance has 80 U and 270 U respectively. In situ doping method is applicable to form S/D region in poly TFT due to low resistance. With additional doping in ion mass doping, resistance was lowered in P type and N type. Also bottom gate TFT was fabricated with in-situ doping method instead of ion mass doping (IMD). We confirmed LDD structure is needed in bottom gate poly Si TFT. Off set in drain region reduce the leakage due to reduction in lateral field. Acknowledgments The authors would like to thank the National Foundation of Korea (Grant RIAMI- AM37-11), NeoePoly Inc., and Eui-San Research Center at Seoul National University for the process support. References [1] F. Oki, Y. Ogawa, Y. Fujiki, Japanese Journal of Applied Physics 8 (1969) 1056. [2] S.W. Lee, S.K. Joo, IEEE Electron Device Letters 17 (4) (April.1996) 160e162. [3] C.W. Byun, S.W. Son, Y.W. Lee, S.K. Joo, Electronic Materials Letters 8 (3) (2012) 251e258. [4] C.W. Byun, S.W. Son, Y.W. Lee, H.M. Kang, S.A. Park, W.C. Lim, T. Li, S.K. Joo, Electronic Materials Letters 8 (2) (2012) 107e110. [5] G.F. Yang, Y.W. Lee, S.K. Joo, Electronic Materials Letters 8 (2) (2012) 191e196. [6] Y.W. Lee, S.J. LEE, S.J. Yun, S.K. Joo, Current Applied Physics 11 (2011) S158e S162. [7] N.K. Song, M.S. Kim, S.H. Han, Y.S. Kim, S.K. Joo, Journal of Electrochemical Society 154 (5) (2007) H370eH373. [8] Y. Kuo, Thin Film Transistors Material and Processes, vol. 2, p. 41. [9] L. Jung, J. Damiano Jr., J.R. Zaman, S. Batra, M. Manning, S.K. Banerjee, Solid-State Electronics 38 (12) (1995) 2069e2073. [10] Shengdong Zhang, Ruqi Han, Mansun J. Chan, IEEE Electron Device Letters 22 (8) (AUGUST 2001). [11] I.C. Lee, T.Y. Ma, Thin Solid Films 461 (2004) 336e339. [12] S.W. Son, C.W. Byun, S.J. Lee, S.J. Yoon, S.K. Joo, Journal of Nanoscience and Nanotechnology 12 (2012) 3195e3199.