An investigation of drain pulse induced hot carrier degradation in n-type low temperature polycrystalline silicon thin film transistors

Microelectronics Reliability 50 (2010) 713–716

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An investigation of drain pulse induced hot carrier degradation in n-type low temperature polycrystalline silicon thin film transistors Meng Zhang, Mingxiang Wang * Department of Microelectronics, Soochow University, Suzhou 215006, PR China

a r t i c l e

i n f o

Article history: Received 1 December 2009 Received in revised form 31 December 2009 Available online 9 February 2010

a b s t r a c t Degradation of n-type low temperature polycrystalline silicon thin film transistors under drain pulse stress is first investigated. Stress parameters are pulse amplitude, frequency and transition time. Device degradation is found to be dominated by a dynamic hot carrier effect, which is independent of pulse falling time but depends on pulse rising time. Shorter rising time brings larger device degradation. Based on experimental results and device simulation, a PN junction degradation model taking trap related carrier emission and trapping into account is proposed. Crown Copyright Ó 2010 Published by Elsevier Ltd. All rights reserved.

1. Introduction Low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) have attracted much attention for integrated active matrix displays due to their higher mobility. TFTs in driver circuits, unlike those in the pixels, are subjected to high frequency voltage pulses. Such application would require devices to withstand dynamic stress on both gate and drain electrodes [1]. Therefore, related dynamic degradation phenomena should be carefully examined. Most previous dynamic degradation studies focused on device instability under gate pulse stress with the drain electrode either grounded [2,3] or DC biased [4,5], where the degradation was controlled by a dynamic hot carrier (HC) effect related to pulse transition time [2–5]. Others focused on device reliability under synchronized gate and drain pulses, where AC self-heating (SH) effect [6] or combined AC SH and HC effect [7] was involved. However, dynamic device degradation under drain pulse stress has not been reported yet. In this work, degradation behaviors of n-type LTPS TFTs under drain pulse stress is first studied at various pulse parameters such as amplitude, frequency (f) and transition time. It is found that a dynamic HC effect dominates the device degradation. Such degradation strongly depends on pulse rising time (tr) but is independent of falling time (tf). Based on experimental and simulation results, a PN junction degradation mechanism considering carrier emission and trapping is discussed. As a comparison, the same stress test is also performed on high temperature polycrystalline

* Corresponding author. Address: Department of Microelectronics, Soochow University, PO Box 125, No.1 Shizi Street, Suzhou 215006, PR China. Fax: +86 512 6787 1211. E-mail address: [email protected] (M. Wang).

silicon (HTPS) TFTs. The observation is consistent with the proposed degradation mechanism. 2. Experimental TFTs used in this study were in conventional self-aligned topgate structure. First, a 50 nm amorphous-Si (a-Si) was deposited on an oxidized silicon wafer by low-pressure chemical vapor deposition (LPCVD). After patterning of a-Si active islands and LPCVD of an 80 nm low temperature oxide (LTO), crystallization inducing window was opened through the LTO and 5 nm Ni was evaporated by electron beam at room temperature. The wafers were subsequently annealed for metal-induced unilateral crystallization of active islands at 550 °C for 24 h in N2 ambient. After Ni removal, another extended anneal was done at 550 °C for 72 h. Then LTO was removed and another 100 nm LTO layer was deposited as gate oxide, followed by LPCVD of 300 nm poly-Si as gate. After gate patterning, a self-aligned phosphorous implantation with a dose of 4  1015 cm 2 was done to form the source and drain, and subsequently activated at 620 °C for 3 h. Contact holes were then opened before aluminum layer sputtering and patterning. Finally, wafers were sintered in Forming gas. For HTPS TFTs, 100 nm active layer was formed by solution based metal-induced crystallization of a-Si film at 550 °C for 3 h. Later it is recrystallized at 900 °C for 1 h in N2. by poly-Si oxidation at 950 °C for 48 min in dry O2. n-type LTPS TFTs subjected to the drain pulse stress have a device width (W) 10 15 lm and length (L) 10 lm. Shown in Fig. 1 is the pulse waveform applied to the drain electrode. The pulse swings from zero to a high voltage level (Vdh) at a fixed pulse duty ratio of 50%. Stress parameters are pulse amplitude, f, tr and tf. For comparison, degradation of HTPS TFTs under the same stress condition is also examined. Devices are measured before and after

0026-2714/$ - see front matter Crown Copyright Ó 2010 Published by Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.01.024

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140

Vdh

S

D

0V

tf

tr

Fig. 1. Waveform of voltage pulse applied to the TFT drain electrode with gate and source grounded. The low voltage level and the pulse duty ratio are fixed at zero and 50%, respectively. Vdh, tr and tf are the pulse high voltage level, rising time and falling time, respectively.

Drain Current (μ A)

G

stress by using Agilent 4156C semiconductor parameter analyzer and Vector MX-1100B prober. Device degradation is characterized by analyzing variation on-current (Ion) defined in transfer curve measured at Vds = 0.1 V and Vg = 12 V. Finally, device simulation is preformed by using Silvaco ATLAS.

Vg=12V

W/L=15/10μ m Vdh=15V 120 f=500kHz tr=tf=0.1μ s 100

Vdsat

80

Initial 1s 10s 100s 1000s 3000s

60 40 20 0 0

5

10

15

20

Drain Voltage (V) Fig. 3. Output curve degradation with stress time under drain pulse stress for an ntype LTPS TFT, measured at Vg = 12 V.

3. Results and discussion 3.1. Degradation phenomena

-9

10

-10

10

-11

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10

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Vdh 35V 25V 20V 15V W/L=15/10μ m f=500kHz tr=tf=0.1μ s -2

10

-1

10

0

10

1

10

2

10

3

Stress Time (s) Fig. 4. Pulse amplitude dependence of Ion degradation plotted in logarithmic scale. The average degradation slope is 1.0.

DC Vd=15V 500kHz 100s

Gate Voltage (V) -6

-4

-2

Vds=5V -9

10

-10

-12

10

-40

N 3

10

20

30

Gate Voltage (V) Fig. 2. Typical time evolution of transfer characteristic under drain pulse stress condition for an n-type LTPS TFT, measured at Vds = 0.1 V. The inset is the off-state current degradation measured at Vds = 5 V.

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0 -30

500kHz 50kHz 5kHz 500Hz

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10 10 10 10 10 10 10

-60 -90

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W/L=15/10μm Vdh=15V -20 tr=tf=0.1μs

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-14 -12 -10 -8

Initial 10s 30s 100s 300s 1000s 3000s

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1

Slope=1.0

Δ Ion (%)

Drain Current (A)

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10

Δ Ion (%)

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10

W/L=15/10μ m Vds=0.1V Vdh=15V f=500kHz tr=tf=0.1μ s

Off-state Current (A)

-5

10

10

−Δ Ion (%)

For n-type LTPS TFTs, device instability is first examined at a DC drain voltage stress of Vd = 15 V with the gate and source grounded. Up to stress time of 105 s, no HC degradation is observed. Then drain pulse stress test is performed on the same kind of TFTs with the same Vdh = 15 V. Shown in Fig. 2 is the typical time evolution of transfer characteristic measured at Vds = 0.1 V. The inset is the offstate leakage current degradation measured at Vds = 5 V. Clearly, Ion degrades with stress time while the subthreshold region is almost unaffected. For the off-state characteristic, the GIDL current [8] markedly decreases with stress time as shown in the inset. Shown in Fig. 3 is the output characteristic degradation. The drain saturation current keeps almost constant while the drain saturation voltage increases with stress time significantly. Clearly, both transfer and output characteristic degradation features are consistent with typical HC degradation behaviors [9,10], implying that a HC mechanism should be involved. To determine the key factors controlling the device degradation, stress test is performed at various pulse amplitudes, fs, and transition times. Fig. 4 is the Ion degradation dependent on stress time

1

10

2

10

3

10

4

10

Stress Time (s) Fig. 5. Ion degradation dependent on stress time under various pulse fs. Solid symbol is the Ion degradation under drain DC stress and the pentagram is the Ion degradation under 500 kHz stress for 100 s after the DC stress. The inset is Ion degradation dependent on pulse number under various pulse fs.

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0

1

10

2

15V 1

10

100ns

(a) (b)

0V

-3

tf=1μ s

tr

(b) 5

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0.1μ s 0.3μ s 1μ s 3μ s

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100ns

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0V 1

-1

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-2

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9

10

0

10

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60

80

100

120

Fig. 7. Lateral transient electric filed (Ex) and transient current density (Jx) at a selected point in the channel near the drain junction calculated by device simulator during (a) tr transient time and (b) tf transient time. x is the direction from the drain to channel.

2

10

DC Jx 1

10

0

Jx (A/cm )

10 2

under various pulse amplitudes. Obviously, degradation is enhanced at larger pulse amplitude. For all amplitudes, the same degradation slope of 1.0 is obtained, which implies that a reaction limited defect generation mechanism should be involved [11]. Fig. 5 is the Ion degradation dependent on stress time at various pulse fs. Under DC stress condition (f = 0), as mentioned above, no degradation occurs, while under pulsed Vd stress degradation increases with increasing f. In the figure inset, degradation curves are plotted against pulse number (N) rather than stress time. It is found that all degradation curves under different fs actually follow the same trend. It indicates that the degradation is associated with the pulse transition edges. This is the same observation as in dynamic HC degradation under gate pulse stress [2]. To determine the effect of pulse transition edge, dependence of device degradation on transition time tr or tf is investigated. Shown in Fig. 6 is the Ion degradation for various tr or tf. Apparently, Ion degradation is independent of tf (Fig. 6a) but strongly depends on tr (Fig. 6b). Shorter tr brings larger degradation. It indicates that the underlying HC mechanism is related to tr rather than tf. It is different from that in the gate pulse induced HC degradation, in which more emitted carriers are exposed to a higher transient coupling electrical field at shorter tf, inducing more degradation [2–5].

40

Transient Time (ns)

Number of Repetitions Fig. 6. Dependence of Ion degradation on pulse number for various (a) tf at fixed tr = 1 ls and (b) tr with tf = 1 ls.

0

5

-2

15V

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-1

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10

0 -20

10

Ex (10 V/cm)

(a)

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Jx (A/cm )

-30

tf 0.1μ s 0.3μ s 1μ s 3μ s

− Jx (A/cm )

Δ Ion (%)

W/L=10/10μ m -10 Vdh=15V -20 f=100kHz tr=1μ s

-1

10

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10

At the end of tr

-3

10

At 1/3 part of tr At the beginning of tr

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Rising Time (ns) Fig. 8. Simulated Jx dependent on pulse rising time at different part of tr. The pentagram is Jx simulated under DC Vd = 15 V.

3.2. Simulation results A transient simulation is performed at a selected point in the channel near the drain junction. Since the degradation is related to HC effect, two key parameters lateral electric filed (Ex) and current density (Jx) are simulated, in which x is the direction from the drain to channel. The continuous defect model [12] is used for the simulation. Plotted in Fig. 7 are the transient Ex and Jx along the pulse transition edges. As shown in Fig. 7a, in the tr transient, corresponding to the Vd swinging from zero to Vdh, Ex increases to a high electric field. Simultaneously, Jx in the same direction of Ex is observed. A ‘‘tail” current still maintains when Ex increases above 105 V/cm. These carriers will be exposed to the high Ex and become HCs, creating defects near the drain side. As shown in Fig. 7b, in the tf transient Jx is much smaller than that during tr. Furthermore, Jx is in a direction opposite to Ex. Therefore, it cannot be a drift current and does not contribute to HC effect, which explains the tf independence of the degradation (Fig. 6a). Fig. 8 is simulated Jx at various tr. Clearly, shorter tr brings significantly larger Jx and more HCs, leading to larger degradation (Fig. 6b). As for the DC stress of Vd = 15 V,

although Ex is high, Jx is almost zero. Therefore, no degradation can be induced (Fig. 5). 3.3. Degradation mechanism In LTPS TFTs, there are large amount of defects at the interface and grain boundaries. During drain pulse swings from 0 to a high Vdh, drain junction becomes more reversely biased. The channel intrinsic poly-Si adjacent to the drain diffusion edge needs to be depleted through trap ionization therein. After de-trapping, some released carriers are exposed to the high Ex and become HCs, causing defects near the drain side. Since the emission time of deep traps can be as long as ms level [13], shorter tr means more carriers emitted from deep trap states would be exposed to the high Ex, leading to the tr dependent degradation (Fig. 6b). During Vd falling edge, the depletion region is narrowed. Ionized trap states need to be neutralized through carrier trapping from the outer edge of depletion region, where the electric field is low. Thus no HC is generated, leading to the tf independent of degradation (Fig. 6a). This

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larger Vdh. A degradation mechanism taking trap carrier emission and trapping into consideration is discussed.

0

Vds=0.1V

Acknowledgments

Δ Ion (%)

-20 Authors would like to thank Prof. Man Wong in Hong Kong University of Science and Technology for providing us the TFT devices and for valuable discussions. This work was supported by the Natural Science Foundation of Jiangsu Province of China (BK2009112) and the National Natural Science Foundation of China (60406001).

-40

-60

-80

W/L=15/10μ m Vdh=15V f=500kHz tr=tf=0.1μ s 6

10

References

LTPS TFT HTPS TFT 7

10

8

10

Number of Repetitions Fig. 9. Comparison of Ion degradation between LTPS TFT and HTPS TFT under the same stress condition.

PN junction degradation mechanism differs from the gate pulse induced HC degradation mechanism, in which emitted carriers are exposed to the high coupling electric field when the gate pulse swings from inversion region to depletion region [2–5]. In HTPS TFTs, there are much fewer deep traps, thus the above degradation mechanism is greatly suppressed. Within the time interval of rising/falling edge, the channel depletion region can be enlarged/narrowed by shallow traps emission/capture at the outer edge of the depletion region. Thus no HC degradation occurs. Indeed, as shown in Fig. 9 is a comparison of the Ion degradation between LTPS and HTPS TFTs under the same drain pulse stress condition. Little degradation is observed in the HTPS TFT, which accords well with the proposed degradation mechanism.

4. Summary It is observed that drain pulse can induce device degradation in n-type LTPS TFTs, which is controlled by a dynamic HC mechanism associated with tr. Device degradation is enhanced at shorter tr and

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