- Email: [email protected]
Novel δ-doped partially insulated junctionless transistor for mixed signal integrated circuits
Superlattices and Microstructures 90 (2016) 247e256
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Novel d-doped partially insulated junctionless transistor for mixed signal integrated circuits Ganesh C. Patil a, *, Vijaysinh H. Bonge b, Mayur M. Malode c, Rahul G. Jain c a
Center for VLSI and Nanotechnology, Visvesvaraya National Institute of Technology, Nagpur, Maharashtra, India Department of Electronics and Telecommunication Engineering, SVERI's College of Engineering, Pandharpur, Maharashtra, India c Department of Electronics and Telecommunication Engineering, JSPM's Rajarshi Shahu College of Engineering, Savitribai Phule Pune University, Pune, Maharashtra, India b
a r t i c l e i n f o
a b s t r a c t
Article history: Received 27 October 2015 Received in revised form 18 December 2015 Accepted 21 December 2015 Available online 24 December 2015
In this paper, d-doped partially insulated junctionless transistor (d-Pi-OXJLT) has been proposed which shows that, employing highly doped d-region below the channel not only reduces the off-state leakage current (IOFF) and short channel effects (SCEs) but also reduce the requirements of scaling channel thickness of junctionless transistor (JLT). The comparative analysis of digital and analog circuit performance of proposed d-Pi-OXJLT, bulk planar (BP) JLT and silicon-on-insulator (SOI) JLT has also been carried out. The digital parameters analyzed in this work are, on-state drive current (ION), IOFF, ION/IOFF ratio, static power dissipation (PSTAT) whereas the analog parameters analyzed includes, transconductance (GM), transconductance generation factor (GM/IDS), intrinsic gain (GMRO) and cut-off frequency (fT) of the devices. In addition, scaling behavior of the devices is studied for various channel lengths by using the parameters such as drain induced barrier lowering (DIBL) and sub-threshold swing (SS). It has been found that, the proposed d-Pi-OXJLT shows significant reduction in IOFF, DIBL and SS over BPJLT and SOIJLT devices. Further, ION and ION/IOFF ratio in the case of proposed d-Pi-OXJLT also improves over the BPJLT device. Furthermore, the improvement in analog figures of merit, GM, GM/IDS, GMRO and fT in the case of proposed d-Pi-OXJLT clearly shows that the proposed d-Pi-OXJLT is the promising device for mixed signal integrated circuits. © 2015 Elsevier Ltd. All rights reserved.
Keywords: Junctionless transistor Partially insulated Work function Scaling
1. Introduction Recently, the researchers and chipmakers are looking forward to scale down the size of the MOSFET. However, the conventional MOSFET suffer from the challenges of fabrication complexity and short channel effects (SCEs) [1e3]. It has been shown that, the MOSFET named as junctionless transistor (JLT) which does not have junction among drain-to-channel and source-to-channel interfaces has simple fabrication process and reduced SCEs [4e7]. Further, due to junction free uniformly doped source, channel and drain regions, the JLT also known as gated resistor [8,9]. To improve the performance of JLT various device structures have also been reported in the literature. The JLT structures include, single gate, double gate and dual material gate device structures [10e15]. The JLT has also been considered as promising device for static, dynamic and flash
* Corresponding author. E-mail addresses: [email protected] (G.C. Patil), [email protected] (V.H. Bonge), [email protected] (M.M. Malode), rahul. [email protected] (R.G. Jain). http://dx.doi.org/10.1016/j.spmi.2015.12.024 0749-6036/© 2015 Elsevier Ltd. All rights reserved.
248
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
random access memory architectures [16e18]. However, the multiple gate JLTs found some challenges for CMOS logic and analog/mixed-signal circuits [19]. Recently, due to reduced fabrication complexity the planar JLT has attracted the attention of the researchers [20]. In addition, the intrinsic digital and analog parameters of planar JLT have also been analyzed [20e25]. Despite having less fabrication complexity, the planar JLT suffers from larger off-state leakage current [26], aggressive scaling of buried oxide (BOX) layer in silicon-on-insulator (SOI), requirement of high work function [29] and high variability due to random dopant fluctuations [30e32]. In this paper, to overcome the challenges involved in JLT a new JLT device having partially insulated BOX with delta doping below the channel has been proposed. The proposed structure is named as, delta-doped partially insulated junctionless transistor (d-Pi-OXJLT). Although the concept of Pi-OX has been studied in JLT [26e28] and d-doped Pi-OX approach has been studied in dopant-segregated schottky barrier SOI MOSFET [33], the concept of d-doped Pi-OX has not been investigated in JLT. The digital parameters considered in this study are on-state drive current (ION), off-state leakage current (IOFF), ION/IOFF ratio and the static power dissipation (PSTAT). Further, the scaling behavior of d-Pi-OXJLT is studied by using drain induced barrier lowering (DIBL) and sub-threshold swing (SS). The analog parameters such as transconductance (GM), transconductance generation factor (GM/IDS), intrinsic gain (GMRO) and cut-off frequency (fT) have also been analyzed, where IDS is the drain to source current and RO is the output resistance of the devices. In addition to this the digital and analog behavior of proposed d-Pi-OXJLT has been compared with bulk planar (BP) JLT and SOIJLT devices. The rest of the paper is organized in 3 sections. Section 2 presents the device structures and the simulation methodology used and Section 3 presents the detailed results and the discussion on DC performance, short-channel effects and intrinsic device performance of BPJLT, SOIJLT and proposed d-Pi-OXJLT devices. Finally the conclusion is given in Section 4. 2. Device structures and simulation setup Fig. 1 (a)-(c) shows the device structures of proposed d-Pi-OXJLT, BPJLT and SOIJLT devices used in the simulations. The ntype layer below the gate oxide is considered as physical gate length (LG). The carrier transport in the channel is considered mainly because of the drift-diffusion, so drift-diffusion models are incorporated along with the concentration dependent and field dependent mobility models. Further, the band-gap narrowing, Schockly-Read-Hall recombination and Auger recombination models have been included in the simulations. The device parameters used in the simulation are listed in Table 1. For extracting the electrical parameters of the devices linear threshold voltage (VTLIN) has been adjusted to 0.25 V. The VTLIN is adjusted at IDS ¼ 107 A (W/LG) and VDS ¼ 50 mV by using gate wok function engineering [23], where W ¼ 1 mm. In addition to this, the small signal ac analysis is enabled in the simulator at frequency 1 MHz. 3. Fabrication flow of d-pi-OXJLT The proposed fabrication process flow of the d-Pi-OXJLT is shown in Fig. 2. The process steps used in Refs. [33e39] have been used to fabricate the proposed d-Pi-OXJLT structure. The substrate material used in the fabrication process is p-type Si (See Fig. 2(a)). The epitaxial process is used to grow the SiGe and Si which is followed by the deposition of SiO2 oxide and Si3N4 mask (see Fig. 2(b)). In Fig. 2(c) using the photolithography the active area is etched out to expose the substrate. In order to grow Si epitaxially the mask layers are removed from the non-exposed area (See Fig. 2(d)). The SiO2 and Si3N4 masks are again grown to form the partial BOX which is done by trench isolation and oxidation techniques. The formed trenches can be seen in Fig. 2(e). The cavity can be created by removing the SiGe with the help of wet etchant [35] (See Fig. 2(f)). In order to form the partial BOX the oxidation process carried out which fills the cavity formed in previous step (see Fig. 2(g)). The mask layer and SiO2 are removed again to expose the Si followed with the reactive ion etching process to obtain the structure shown in Fig. 2(h). The heavily doped p-type d-region is created under the channel (see Fig. 2(i)) by using the post-low-energy implanting selective epitaxy technique [39]. Further to create the n-type layer the Si is epitaxially grown and the ion implantation of arsenic has been carried out (See Fig. 2(j)-(k)). To create gate stack, the oxidation process can be used followed by the metal deposition as shown in Fig. 2(l). The SiO2 and Si3N4 spacers are formed as shown in Fig. 2(m). After forming the metal contacts the device structure as shown in Fig. 2(n) can be fabricated by using the proposed process steps. 4. Simulation results and discussion 4.1. Potential, electric field and electron velocity Fig. 3 (a)-(b) shows the electric field and electron velocity along drain-to-channel and source-to-channel at VDS ¼ VGS ¼ 1 V Fig. 3 (a) shows the two electric peaks at channel and drain region of BPJLT and d-Pi-OXJLT devices. However, since the channel has not been depleted due to substrate of SOIJLT, the lower electric field is observed in SOIJLT device. The electric peak at channel region of d-Pi-OXJLT is higher due to the more depletion caused by the highly doped d-region than BPJLT and SOIJLT devices. Further, from Fig. 3 (a) it can be observed that, electric field peak at drain region is lower in case of d-Pi-OXJLT which will suppress the SCEs and hot carrier effect [42,43]. The electric field peak at channel region is more in case of d-Pi-OXJLT
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
249
Fig. 1. (a) BPJLT, (b) SOIJLT and (c) proposed d-Pi-OXJLT structures used in the simulations.
which indicates the increase in carrier velocity due to which the drive current of the proposed d-Pi-OXJLT device improves [43] (See Fig. 3 (b)). 4.2. DC characteristics Fig. 4 shows the transfer characteristics (IDS-VGS) of BPJLT, SOIJLT and d-Pi-OXJLT. From the figure, it can be observed that the proposed d-Pi-OXJLT shows the improved subthreshold behavior over the BPJLT and SOIJLT counterparts. The main reason for this improvement is the availability of d-layer which creates the depletion due to which effective device layer thickness reduces and hence the thinner device layer thickness will improve the subthreshold behavior [20]. Further, the marginal improvement in ION is observed in case of d-Pi-OXJLT over the BPJLT due to Pi-OX nature which will reduce the direct drain to substrate current. This improvement in ION is mainly because of the presence of p-type d-layer under the channel which increases the current driving capability of the device. Furthermore the presence of d-layer cuts-off the fringing field lines originating from the drain and reduces the leakage current of the device.
250
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
Table 1 Device Parameters used in simulation. Parameters
Unit
BPJLT
SOIJLT
d-Pi-OXJLT
Channel thickness (TCH) Gate Oxide Thickness (TOX) BOX Thickness (TBOX) n-type Channel Doping (ND) p-type substrate Doping (NA) p-type d-doping (Nd)
nm nm nm cm3 cm3 cm3
10 1 # 1 1018 5 1017 #
10 1 30 1 1018 5 1017 #
10 1 30 1 1018 5 1017 5 1018
(a)
(b)
(c)
(d) (e)
(g)
(f)
(h)
(i)
(j)
(k)
(l)
SiGe Contact
(m)
Arsenic Si3N4
SiO2 PolySi
Boron Si
(n) Fig. 2. Proposed process flow for the fabrication of novel d-Pi-OXJLT.
Fig. 5 shows the output characteristics of the proposed d-Pi-OXJLT, BPJLT and SOIJLT devices. The channel resistance in case of planar JLT is mainly depends on depletion caused due to gate work function and oppositely doped substrate. The depletion due to oppositely doped substrate is more in case of BPJLT and d-Pi-OXJLT which will cause lower IDS (See Fig. 5). The digital characteristics, scaling efficiency and low power circuit performance is mainly depends upon the DIBL and SS which are mainly related to sub threshold leakage current of the device [19], [44]. The DIBL has been calculated by using (VTLIN-VTSAT)/0.95 [37][44], where VTLIN and VTSAT are extracted at VDS ¼ 50 mV and 1 V respectively for IDS ¼ 107 A [45,46]. Further, for better comparison of devices VTLIN is adjusted to 0.25 V at IDS ¼ 107 (W/LG) by work function engineering [23] where W ¼ 1 mm. From Fig. 6 it can be observed that, DIBL in the case of d-Pi-OXJLT is low. This is mainly due to the electric field lines originating from the drain are terminated in the d-region under the channel. The SS has been extracted from the IDS verses VGS characteristics [47,48]. Fig. 7 shows the variation of SS as a function of LG for BPJLT, SOIJLT and d-Pi-OXJLT devices. From the figure it can be seen that, SS in the case of d-Pi-OXJLT is lower for all the LG values. The large depletion due to highly doped d-region causes the improved sub-threshold behavior for d-Pi-OXJLT. The ION is defined at VGS ¼ 1 V and VDS ¼ 1 V whereas IOFF is defined at VGS ¼ 0 V and VDS ¼ 1 V. The ION/IOFF ratio of BPJLT, SOI-JLT and the proposed d-Pi-OX JLT is shown in Fig. 8. From the figure it can be seen that, in comparison to BPJLT and SOI-JLT devices, ION/IOFF ratio in the case of proposed d-Pi-OXJLT is significantly high. Further, from Fig. 9 it can be observed that, PSTAT
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
251
Fig. 3. (a) Electric field, and (b) Electron velocity along the source-channel-drain path of the device.
in the case of proposed d-Pi-OXJLT is low. Here, the static power dissipation is calculated by using PSTAT ¼ VDS.IOFF. The improvement in ION/IOFF ratio and the reduction in PSTAT at lower channel lengths is mainly due to the significant reduction in IOFF of the proposed d-Pi-OXJLT device [21]. 4.3. Analog/RF performance Fig. 10 shows the variation of GM as a function of VGS for proposed d-Pi-OXJLT, BPJLT and SOIJLT devices at VDS ¼ 1 V. From the figure it can be seen that, in comparison to BPJLT and proposed d-Pi-OXJLT, the SOIJLT has lower GM. Further, the proposed d-Pi-OXJLT has higher value of GM over the BPJLT device. The lower value of GM below the threshold voltage has been observed in the case of proposed d-Pi-OXJLT which is desirable for the faster turn-off of the devices in the circuits [50]. Fig. 11 shows the variation of GM/IDS as a function of VGS for proposed d-Pi-OXJLT, BPJLT and SOIJLT at VDS ¼ 1 V. Since the amplification delivered by device is considered by GM and IDS considers the power dissipation, GM/IDS is considered as quality factor for analog integrated circuits [51]. From Fig. 11 it can be seen that, due to improved GM at higher VGS, the GM/IDS in the case of proposed d-Pi-OXJLT improves. Further, due to reduction in IDS at lower VGS, the GM/IDS in the case of proposed d-PiOXJLT improve in comparison to BPJLT and SOI-JLT devices. Since GM/IDS in the weak inversion region is related to the subthreshold swing and in the strong inversion region it decreases quadratically depending upon body-effect factor and the channel mobility, GM/IDS in the case of proposed d-Pi-OXJLT improves [33]. Further, the higher peak value of GM/IDS is desirable for the reduction in SCEs and SS (ln(10)/(GM/IDS)max) [52]. Fig. 12 shows the GMRO for the BPJLT and d-Pi-OXJLT with respect to VGS at VDS ¼ 1 V. It has been observed that GMRO of the d-Pi-OXJLT is higher than BPJLT counterparts due to the higher value of GM and the improvement in RO of the device.
252
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
Fig. 4. ID vs VGS characteristics of BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 5. ID vs VDS characteristics of BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 6. Variation of DIBL with LG for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
Fig. 7. Variation of subthreshold-swing (S) with LG for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 8. Variation of ION/IOFF with LG for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 9. Variation of intrinsic static power dissipation as a function of LG for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
253
254
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
Fig. 10. Variation of GM at VDS ¼ 1 V for LG ¼ 10 nm for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 11. Variation of GM/IDS at VDS ¼ 1 V for LG ¼ 10 nm for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 12. Variation of GMRO at VDS ¼ 1 V for LG ¼ 10 nm for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
255
Fig. 13. Variation of fT at VDS ¼ 1 V for LG ¼ 10 nm for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 13 shows the variation of fT as a function of VGS for BPJLT, SOIJLT and d-Pi-OXJLT. Here, the fT is calculated as [53] fT ¼ GM/ 2pCG. From the figure it can be observed that, due to significant improvement in GM, fT in the case of proposed d-Pi-OXJLT is higher in comparison to BPJLT and SOIJLT devices [54]. 5. Conclusions In this work a novel d-Pi-OXJLT has been proposed for nanoscale mixed signal integrated circuits. The detailed fabrication process flow of the novel d-Pi-OXJLT has also been presented in this paper. The results show that, incorporating partial buried oxide and d-doping in JLT not only reduces the OFF state leakage current but also reduces the short channel effects such as DIBL and SS of the device. Further, the digital and analog characteristics of proposed d-Pi-OXJLT have been investigated using 2-D simulations and compared with BPJLT and SOIJLT counterparts. It has been observed that, the digital parameters such as ION, IOFF, ION/IOFF, and PSTAT in the case of proposed d-Pi-OXJLT improves significantly over the BPJLT and SOIJLT devices. Further, the analog figures of merit such as GM, GM/IDS, GMRO and fT in the case of proposed d-Pi-OXJLT device also improve over the BPJLT and SOIJLT devices. This clearly shows that, in comparison to BPJLT and SOIJLT the proposed d-Pi-OXJLT is the promising device for nanoscale integrated circuits.
References [1] S.J. Choi, D.-I. Moon, S. Kim, J.P. Duarke, Y.K. Choi, Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistor, IEEE Electron Dev. Lett. 32 (02) (2011) 125e127. [2] C. Li, Y. Zhuang, Di Si, R. Han, Subthreshold Behavior Model for Nanoscale Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs, IEEE Trans. Electron Dev. 60 (11) (2013) 3655e3661. [3] H.-B. Chen, C.-Y. Chang, N.-H. Lu, J.-J. Wu, M.-H. Han, Y.-C. Cheng, Y.-C. Wu, Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel, IEEE Electron Dev. Lett. 34 (07) (2013) 897e899. [4] J.P. Duarte, S.J. Choi, D.-I. Moon, Y.K. Choi, Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistor, IEEE Electron Dev. Lett. 32 (06) (2011) 704e706. [5] T.K. Kim, D.H. Kim, Y.G. Yoon, J.M. Moon, B.W. Hwang, Dong-I1 Moon, G.S. Lee, D.W. Lee, D.E. Yoo, H.C. Hwang, J.S. Kim, Y.-K. Choi, B.J. Cho, S.-H. Lee, Frist Demonstration of Junctionless Accumulation-Mode Bulk FinFETs With Robust Junction Isolation, IEEE Electron Dev. Lett. 34 (12) (2013) 1479e1481. [6] Choi J-M. Jong-H, Y.-K. Choi, Analytical Threshold Voltage Model of Junctionless Double-Gate MOSFETs With Localized Charges, IEEE Tran. Electron Dev. 60 (09) (2013) 2951e2955. [7] T. Rudenko, R. Yu, S. Barraud, K. Cherkaoui, A. Nazarov, Method for Extracting Doping Concentration and Flat-Band Voltage in Junctionless Multigate MOSFETs Using 2-D Electrostatic Effects, IEEE Electron Dev. Lett. 34 (08) (2013) 957e959. [8] J.P. Colinge, et al., SOI Gated Register: CMOS without junction, in: SOI Conference, IEEE international, Foster city CA, 2009, pp. 1e2. [9] W. Vitale, et al., Monte Carlo Study Transport Properties in Junctionless transistor, in: Computational Electronic (IWCE), 2010, pp. 1e3. Pisa. [10] Moon D-I1, S.-J. Choi, J.P. Duarte, Y.-K. Choi, Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistor Built on a Bulk Substrate, IEEE Trans. Electron Dev. 60 (04) (2013) 1355e1360. [11] M.-H. Han, C.-Y. Chang, Y.-R. Jhan, J.-J. Wu, H.-B. Chen, Y.-C. Cheng, Y.-C. Wu, Characteristic of p-type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis, IEEE Electron Dev. Lett. 34 (02) (2013) 157e159. [12] D. Ghosh, M.S. Parihar, G.A. Armstrong, A. Kranti, High-Performance Junctionless MOSFETs for Ultralow-Power Analog/RF Applications, IEEE Electron Dev. Lett. 33 (10) (2012) 1477e1479. [13] M.S. Parihar, D. Ghosh, A. Kranti, Ultra Low Power Junctionless MOSFETs for Subthreshold Logic Applications, IEEE Trans. Electron Dev. 60 (05) (2013) 1540e1546. [14] C.-W. Chen, C.-T. Chung, J.-Y. Tzeng, P.-S. Chang, G.-L. Luo, C.-H. Chien, Body-Tied Germanium Tri-Gate Junctionless PMOSFET With In-Situ Boron Doped Channel, IEEE Electron Dev. Lett. 35 (01) (2014) 12e14.
256
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
[15] C.-H. Park, M.-D. Ko, K.-H. Kim, S.-H. Lee, J.-S. Yoon, J.-S. Lee, Y.-H. Jeong, Investigation of Low-Frequency Noise Behavior After Hot-Carrier Stress in an n-Channel Junctionless Nanowire MOSFET, IEEE Electron Dev. Lett. 33 (11) (2012) 1538e1540. [16] C.-W. Lee, R. Yan, I. Ferain, A. Kranti, N. Akhyan, P. Razavi, R. Yu, J. Colinge, Nanowire zero-capacitor DRAM transistor with and without junctions, in: Proc. 10th IEEE-nano, 2010, pp. 242e245. [17] A. Kranti, C. Lee, I. Ferain, R. Yan, N. Akhavan, P. Razavi, R. Yu, G.A. Armstrong, J. Colinge, Junctionless 6T SRAM cell, IET Electron Lett. 46 (22) (2010) 1491e1493. [18] S.-J. Choi, D.-I.1 Mooni, S. Kimi, J.-S. Leei, J.-Y. Kimi, Y.-K. Choii, Nonvolatile memory by all-around-gate junctionless transistor composed of silicon nanowire on bulk substrate, IEEE Electron Dev. Lett. 32 (05) (2011) 602e604. [19] G.C. Patil, S. Qureshi, Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits, Microelectron. J. 43 (05) (2012) 321e328. [20] S. Gundapaneni, M. Bajaj, R.K. Pandey, K.V.R.M. Murali, S. Ganguly, A. Kottantharayil, Effect of Band-to-Band Tunneling on Junctionless Transistor, IEEE Trans. Electron Dev. 59 (04) (2012) 1023e1029. [21] S. Gundapaneni, S. Ganguly, A. Kottantharayil, Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling, IEEE Electron Dev. Lett. 32 (03) (2011) 261e263. [22] S. Gundapaneni, S. Ganguly, A. Kottantharayil, Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor with high-k Spacers, IEEE Electron Dev. Lett. 32 (10) (2011) 1325e1327. [23] R.K. Baruah, R.P. Paily, Analog performance of Bulk Planar Junctionless Transistor, in: 3rd International Conference on Computing Communication and Network Technologies, 2012, pp. 1e4. Coimbatore, Tamilnadu, India. [24] H.-C. Lin, C.-I. Lin, Z.-M. Lin, B.-S. Shie, T.-Y. Huang, Characteristics of Planar Junctionless Poly-Si Thin-Film Transistor With Various Channel Thickness, IEEE Trans. Electron Dev. 60 (03) (2013) 1142e1148. [25] M. Golve, S. Gundapaneni, A. Kottantharayil, Novel Architecture for Zink-Oxide Junctionless Transistor, in: International Conference on Emerging Electronics, 2012, pp. 1e4. Mumbai, Maharashtra, India. [26] S.-H. Syu, J.-T. Lin, Y.-C. Eng, S.-W. Hsu, K.-Y. Chen, Y.-R. Lu, Junction Vs Junctionless Vertical MOSFET by Using Partial SOI Structure: A 2D Simulation Study, in: Junction Technology (IWJT), 2012, pp. 172e175. Shanghai. [27] G.C. Patil, V.H. Bonge, M.M. Malode, R.G. Jain, A Novel Partially Insulated Junctionless Transistor for Low Power Nanoscale Digital Integrated Circuits, in: Junction Technology (IWJT), 2012, pp. 172e175. Shanghai, IEEE 2nd International Conference on Emerging Electronics (ICEE) 2014;Banglore, India, 1-4. [28] U. Khan, B. Ghosh, M.W. Akram, A. Salimath, A comparative study of SELBOX-JLT and SOI-JLT, Appl. Phys. A 117 (4) (2014) 2281e2288. [29] C.-W. Lee, A. Afzalian, N.D. Akhayan, R. Yan, I. Ferain, J.-P. Colinge, Junctionless Multigate Field-Effect Transistor, Appl. Phys. Lett. 94 (05) (2009), 053 511-1e053 511e2. [30] G. Leung, C.O. Chui, Variability impact of random dopant on nanoscale junctionless FinFETs, IEEE Electron Dev. Lett. 33 (06) (2012) 767e769. [31] A. Gnudi, et al., Analysis of threshold voltage variability due to random dopant fluctuation in junctionless FETs, IEEE Electron Dev. Lett. 33 (03) (2012) 336e338. [32] M. Aldegunde, A. Martinez, J.R. Barker, Study of discrete doping induced variability in junctionless nanowire MOSFETs using dissipative quantum transport simulation, IEEE Electron Dev. Lett. 33 (02) (2012) 194e196. [33] G.C. Patil, S. Qureshi, A novel d-doped partially insulated dopant-segregated Schottky barrier SOI MOSFET for analog/RF application, Semicond. Sci. Technol. 26 (08) (2011) 085002e085013. [34] M.J. Kumar, A.A. Orouji, Investigation of a new modified source/drain for diminished self-heating effects in nanoscale MOSFETs using computer simulation, Phys. E 33 (2006) 134e138. [35] K.H. Yeo, et al., A partially insulated field effect transistor (PiFET) as a candidate for scaled transistor, IEEE Electron Dev. Lett. 25 (06) (2004) 387e389. [36] G.C. Patil, S. Qureshi, A Novel Partially Insulated Schottky Source/Drain MOSFET: Short Channel and Self Heating Effects, in: International Conference on Microelectronics, 2010, pp. 252e255. Cairo, Egypt. [37] S.A. Loan, S. Qureshi, S.S.K. Iyer, A Novel Partial-Ground-Plane-Based MOSFET on Selective Buried Oxide: 2-D Simulation Study, IEEE Trans. Electron Dev. 57 (3) (2010) 671e680. [38] F. Bashir, S.A. Loan, M. Rafat, A.R.M. Alamoud, S.A. Abbasi, A High-Performance Source Engineered Charge Plasma-Based Schottky MOSFET on SOI, IEEE Trans. Electron Dev. 62 (10) (2015) 3357e3364. [39] K. Noda, T. Tatsumi, T. Uchida, K. Nakajima, H. Miyamoto, C. Hu, A 0.1-mm delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy, IEEE Trans. Electron Dev. 45 (04) (1998) 809e814. [42] R.K. Baruah, R.P. Paily, A Dual-Material Gate Junctionless Transistor With High-k Spacer for Enhanced Analog Performance, IEEE Trans. Electron Dev. 61 (01) (2014) 123e128. [43] H. Lou, L. Zhang, Y. Zhu, X. Lin, S. Yang, J. He, M. Chan, A Junctionless Nanowire Transistor With a Dual-Material Gate, IEEE Trans. Electron Dev. 59 (07) (2012) 1829e1836. [44] G.C. Patil, S. Qureshi, Engineering spacer in dopant-segregated schottky barrier SOI MOSFET for Nanoscale CMOS circuits, Semicond. Sci. Technol. 27 (04) (2012) 045004. [45] A. Majumdar, X. Wang, A. Kumar, J.R. Holt, D. Dobuzinsky, R. Venigalla, C. Ouyang, S.J. Koester, W. Haensch, Gate length and performance scaling of undoped-body extremely thin SOI MOSFETs, IEEE Electron Dev. Lett. 30 (04) (2009) 413e415. [46] Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chang, P.K. Ko, Y.C. Cheng, Threshold voltage model for deep-submicrometer MOSFETs, IEEE Trans. Electron Dev. 40 (01) (1993) 86e95. [47] C. Li, Y. Zhuang, S. Di, R. Han, Subthreshold Behavior Model for Nanoscale Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs, IEEE Trans. Electron Dev. 60 (11) (2013) 3655e3662. [48] R.K. Baruah, R.P. Paily, Estimation of Process-Induced Variations In Double-Gate Junctionless Transistor, in: 5th International Conference on Computers and Devices for Communication, 2012, pp. 1e4. Kolkata, India. [50] W. Long, H. Ou, J. Kuo, K. Chin, Dual-material gate (DMG) field effect transistor, IEEE Trans. Electron Dev. 46 (05) (1999) 865e870. [51] J.-P. Colinge, Fully-depleted SOI CMOS for analog application, IEEE Trans. Electron Dev. 45 (05) (1998) 1010e1016. [52] D. Ghosh, M.S. Parihar, A. Kranti, Optimizing Nanoscale MOSFET Architecture for Low Power Analog/RF Application, in: 5th International Conference on Nanoelectronics, 2013, pp. 22e23. Singapore. [53] S. Cho, K.R. Kim, B.-G. Park, I.M. Kang, RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs, IEEE Trans. Electron Dev. 58 (05) (2011) 1388e1396. [54] P. Kumar, S. Singh, A. Dixit, P. Kondekar, Digital and Analog Performance of Gate Inside p-type Junctionless Transistor (GI-JLT), in: 5th International Conference on Computational Intelligence, Modelling and Simulation, 2013, pp. 394e397. Seoul, South Korea.
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Novel d-doped partially insulated junctionless transistor for mixed signal integrated circuits Ganesh C. Patil a, *, Vijaysinh H. Bonge b, Mayur M. Malode c, Rahul G. Jain c a
Center for VLSI and Nanotechnology, Visvesvaraya National Institute of Technology, Nagpur, Maharashtra, India Department of Electronics and Telecommunication Engineering, SVERI's College of Engineering, Pandharpur, Maharashtra, India c Department of Electronics and Telecommunication Engineering, JSPM's Rajarshi Shahu College of Engineering, Savitribai Phule Pune University, Pune, Maharashtra, India b
a r t i c l e i n f o
a b s t r a c t
Article history: Received 27 October 2015 Received in revised form 18 December 2015 Accepted 21 December 2015 Available online 24 December 2015
In this paper, d-doped partially insulated junctionless transistor (d-Pi-OXJLT) has been proposed which shows that, employing highly doped d-region below the channel not only reduces the off-state leakage current (IOFF) and short channel effects (SCEs) but also reduce the requirements of scaling channel thickness of junctionless transistor (JLT). The comparative analysis of digital and analog circuit performance of proposed d-Pi-OXJLT, bulk planar (BP) JLT and silicon-on-insulator (SOI) JLT has also been carried out. The digital parameters analyzed in this work are, on-state drive current (ION), IOFF, ION/IOFF ratio, static power dissipation (PSTAT) whereas the analog parameters analyzed includes, transconductance (GM), transconductance generation factor (GM/IDS), intrinsic gain (GMRO) and cut-off frequency (fT) of the devices. In addition, scaling behavior of the devices is studied for various channel lengths by using the parameters such as drain induced barrier lowering (DIBL) and sub-threshold swing (SS). It has been found that, the proposed d-Pi-OXJLT shows significant reduction in IOFF, DIBL and SS over BPJLT and SOIJLT devices. Further, ION and ION/IOFF ratio in the case of proposed d-Pi-OXJLT also improves over the BPJLT device. Furthermore, the improvement in analog figures of merit, GM, GM/IDS, GMRO and fT in the case of proposed d-Pi-OXJLT clearly shows that the proposed d-Pi-OXJLT is the promising device for mixed signal integrated circuits. © 2015 Elsevier Ltd. All rights reserved.
Keywords: Junctionless transistor Partially insulated Work function Scaling
1. Introduction Recently, the researchers and chipmakers are looking forward to scale down the size of the MOSFET. However, the conventional MOSFET suffer from the challenges of fabrication complexity and short channel effects (SCEs) [1e3]. It has been shown that, the MOSFET named as junctionless transistor (JLT) which does not have junction among drain-to-channel and source-to-channel interfaces has simple fabrication process and reduced SCEs [4e7]. Further, due to junction free uniformly doped source, channel and drain regions, the JLT also known as gated resistor [8,9]. To improve the performance of JLT various device structures have also been reported in the literature. The JLT structures include, single gate, double gate and dual material gate device structures [10e15]. The JLT has also been considered as promising device for static, dynamic and flash
* Corresponding author. E-mail addresses: [email protected] (G.C. Patil), [email protected] (V.H. Bonge), [email protected] (M.M. Malode), rahul. [email protected] (R.G. Jain). http://dx.doi.org/10.1016/j.spmi.2015.12.024 0749-6036/© 2015 Elsevier Ltd. All rights reserved.
248
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
random access memory architectures [16e18]. However, the multiple gate JLTs found some challenges for CMOS logic and analog/mixed-signal circuits [19]. Recently, due to reduced fabrication complexity the planar JLT has attracted the attention of the researchers [20]. In addition, the intrinsic digital and analog parameters of planar JLT have also been analyzed [20e25]. Despite having less fabrication complexity, the planar JLT suffers from larger off-state leakage current [26], aggressive scaling of buried oxide (BOX) layer in silicon-on-insulator (SOI), requirement of high work function [29] and high variability due to random dopant fluctuations [30e32]. In this paper, to overcome the challenges involved in JLT a new JLT device having partially insulated BOX with delta doping below the channel has been proposed. The proposed structure is named as, delta-doped partially insulated junctionless transistor (d-Pi-OXJLT). Although the concept of Pi-OX has been studied in JLT [26e28] and d-doped Pi-OX approach has been studied in dopant-segregated schottky barrier SOI MOSFET [33], the concept of d-doped Pi-OX has not been investigated in JLT. The digital parameters considered in this study are on-state drive current (ION), off-state leakage current (IOFF), ION/IOFF ratio and the static power dissipation (PSTAT). Further, the scaling behavior of d-Pi-OXJLT is studied by using drain induced barrier lowering (DIBL) and sub-threshold swing (SS). The analog parameters such as transconductance (GM), transconductance generation factor (GM/IDS), intrinsic gain (GMRO) and cut-off frequency (fT) have also been analyzed, where IDS is the drain to source current and RO is the output resistance of the devices. In addition to this the digital and analog behavior of proposed d-Pi-OXJLT has been compared with bulk planar (BP) JLT and SOIJLT devices. The rest of the paper is organized in 3 sections. Section 2 presents the device structures and the simulation methodology used and Section 3 presents the detailed results and the discussion on DC performance, short-channel effects and intrinsic device performance of BPJLT, SOIJLT and proposed d-Pi-OXJLT devices. Finally the conclusion is given in Section 4. 2. Device structures and simulation setup Fig. 1 (a)-(c) shows the device structures of proposed d-Pi-OXJLT, BPJLT and SOIJLT devices used in the simulations. The ntype layer below the gate oxide is considered as physical gate length (LG). The carrier transport in the channel is considered mainly because of the drift-diffusion, so drift-diffusion models are incorporated along with the concentration dependent and field dependent mobility models. Further, the band-gap narrowing, Schockly-Read-Hall recombination and Auger recombination models have been included in the simulations. The device parameters used in the simulation are listed in Table 1. For extracting the electrical parameters of the devices linear threshold voltage (VTLIN) has been adjusted to 0.25 V. The VTLIN is adjusted at IDS ¼ 107 A (W/LG) and VDS ¼ 50 mV by using gate wok function engineering [23], where W ¼ 1 mm. In addition to this, the small signal ac analysis is enabled in the simulator at frequency 1 MHz. 3. Fabrication flow of d-pi-OXJLT The proposed fabrication process flow of the d-Pi-OXJLT is shown in Fig. 2. The process steps used in Refs. [33e39] have been used to fabricate the proposed d-Pi-OXJLT structure. The substrate material used in the fabrication process is p-type Si (See Fig. 2(a)). The epitaxial process is used to grow the SiGe and Si which is followed by the deposition of SiO2 oxide and Si3N4 mask (see Fig. 2(b)). In Fig. 2(c) using the photolithography the active area is etched out to expose the substrate. In order to grow Si epitaxially the mask layers are removed from the non-exposed area (See Fig. 2(d)). The SiO2 and Si3N4 masks are again grown to form the partial BOX which is done by trench isolation and oxidation techniques. The formed trenches can be seen in Fig. 2(e). The cavity can be created by removing the SiGe with the help of wet etchant [35] (See Fig. 2(f)). In order to form the partial BOX the oxidation process carried out which fills the cavity formed in previous step (see Fig. 2(g)). The mask layer and SiO2 are removed again to expose the Si followed with the reactive ion etching process to obtain the structure shown in Fig. 2(h). The heavily doped p-type d-region is created under the channel (see Fig. 2(i)) by using the post-low-energy implanting selective epitaxy technique [39]. Further to create the n-type layer the Si is epitaxially grown and the ion implantation of arsenic has been carried out (See Fig. 2(j)-(k)). To create gate stack, the oxidation process can be used followed by the metal deposition as shown in Fig. 2(l). The SiO2 and Si3N4 spacers are formed as shown in Fig. 2(m). After forming the metal contacts the device structure as shown in Fig. 2(n) can be fabricated by using the proposed process steps. 4. Simulation results and discussion 4.1. Potential, electric field and electron velocity Fig. 3 (a)-(b) shows the electric field and electron velocity along drain-to-channel and source-to-channel at VDS ¼ VGS ¼ 1 V Fig. 3 (a) shows the two electric peaks at channel and drain region of BPJLT and d-Pi-OXJLT devices. However, since the channel has not been depleted due to substrate of SOIJLT, the lower electric field is observed in SOIJLT device. The electric peak at channel region of d-Pi-OXJLT is higher due to the more depletion caused by the highly doped d-region than BPJLT and SOIJLT devices. Further, from Fig. 3 (a) it can be observed that, electric field peak at drain region is lower in case of d-Pi-OXJLT which will suppress the SCEs and hot carrier effect [42,43]. The electric field peak at channel region is more in case of d-Pi-OXJLT
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
249
Fig. 1. (a) BPJLT, (b) SOIJLT and (c) proposed d-Pi-OXJLT structures used in the simulations.
which indicates the increase in carrier velocity due to which the drive current of the proposed d-Pi-OXJLT device improves [43] (See Fig. 3 (b)). 4.2. DC characteristics Fig. 4 shows the transfer characteristics (IDS-VGS) of BPJLT, SOIJLT and d-Pi-OXJLT. From the figure, it can be observed that the proposed d-Pi-OXJLT shows the improved subthreshold behavior over the BPJLT and SOIJLT counterparts. The main reason for this improvement is the availability of d-layer which creates the depletion due to which effective device layer thickness reduces and hence the thinner device layer thickness will improve the subthreshold behavior [20]. Further, the marginal improvement in ION is observed in case of d-Pi-OXJLT over the BPJLT due to Pi-OX nature which will reduce the direct drain to substrate current. This improvement in ION is mainly because of the presence of p-type d-layer under the channel which increases the current driving capability of the device. Furthermore the presence of d-layer cuts-off the fringing field lines originating from the drain and reduces the leakage current of the device.
250
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
Table 1 Device Parameters used in simulation. Parameters
Unit
BPJLT
SOIJLT
d-Pi-OXJLT
Channel thickness (TCH) Gate Oxide Thickness (TOX) BOX Thickness (TBOX) n-type Channel Doping (ND) p-type substrate Doping (NA) p-type d-doping (Nd)
nm nm nm cm3 cm3 cm3
10 1 # 1 1018 5 1017 #
10 1 30 1 1018 5 1017 #
10 1 30 1 1018 5 1017 5 1018
(a)
(b)
(c)
(d) (e)
(g)
(f)
(h)
(i)
(j)
(k)
(l)
SiGe Contact
(m)
Arsenic Si3N4
SiO2 PolySi
Boron Si
(n) Fig. 2. Proposed process flow for the fabrication of novel d-Pi-OXJLT.
Fig. 5 shows the output characteristics of the proposed d-Pi-OXJLT, BPJLT and SOIJLT devices. The channel resistance in case of planar JLT is mainly depends on depletion caused due to gate work function and oppositely doped substrate. The depletion due to oppositely doped substrate is more in case of BPJLT and d-Pi-OXJLT which will cause lower IDS (See Fig. 5). The digital characteristics, scaling efficiency and low power circuit performance is mainly depends upon the DIBL and SS which are mainly related to sub threshold leakage current of the device [19], [44]. The DIBL has been calculated by using (VTLIN-VTSAT)/0.95 [37][44], where VTLIN and VTSAT are extracted at VDS ¼ 50 mV and 1 V respectively for IDS ¼ 107 A [45,46]. Further, for better comparison of devices VTLIN is adjusted to 0.25 V at IDS ¼ 107 (W/LG) by work function engineering [23] where W ¼ 1 mm. From Fig. 6 it can be observed that, DIBL in the case of d-Pi-OXJLT is low. This is mainly due to the electric field lines originating from the drain are terminated in the d-region under the channel. The SS has been extracted from the IDS verses VGS characteristics [47,48]. Fig. 7 shows the variation of SS as a function of LG for BPJLT, SOIJLT and d-Pi-OXJLT devices. From the figure it can be seen that, SS in the case of d-Pi-OXJLT is lower for all the LG values. The large depletion due to highly doped d-region causes the improved sub-threshold behavior for d-Pi-OXJLT. The ION is defined at VGS ¼ 1 V and VDS ¼ 1 V whereas IOFF is defined at VGS ¼ 0 V and VDS ¼ 1 V. The ION/IOFF ratio of BPJLT, SOI-JLT and the proposed d-Pi-OX JLT is shown in Fig. 8. From the figure it can be seen that, in comparison to BPJLT and SOI-JLT devices, ION/IOFF ratio in the case of proposed d-Pi-OXJLT is significantly high. Further, from Fig. 9 it can be observed that, PSTAT
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
251
Fig. 3. (a) Electric field, and (b) Electron velocity along the source-channel-drain path of the device.
in the case of proposed d-Pi-OXJLT is low. Here, the static power dissipation is calculated by using PSTAT ¼ VDS.IOFF. The improvement in ION/IOFF ratio and the reduction in PSTAT at lower channel lengths is mainly due to the significant reduction in IOFF of the proposed d-Pi-OXJLT device [21]. 4.3. Analog/RF performance Fig. 10 shows the variation of GM as a function of VGS for proposed d-Pi-OXJLT, BPJLT and SOIJLT devices at VDS ¼ 1 V. From the figure it can be seen that, in comparison to BPJLT and proposed d-Pi-OXJLT, the SOIJLT has lower GM. Further, the proposed d-Pi-OXJLT has higher value of GM over the BPJLT device. The lower value of GM below the threshold voltage has been observed in the case of proposed d-Pi-OXJLT which is desirable for the faster turn-off of the devices in the circuits [50]. Fig. 11 shows the variation of GM/IDS as a function of VGS for proposed d-Pi-OXJLT, BPJLT and SOIJLT at VDS ¼ 1 V. Since the amplification delivered by device is considered by GM and IDS considers the power dissipation, GM/IDS is considered as quality factor for analog integrated circuits [51]. From Fig. 11 it can be seen that, due to improved GM at higher VGS, the GM/IDS in the case of proposed d-Pi-OXJLT improves. Further, due to reduction in IDS at lower VGS, the GM/IDS in the case of proposed d-PiOXJLT improve in comparison to BPJLT and SOI-JLT devices. Since GM/IDS in the weak inversion region is related to the subthreshold swing and in the strong inversion region it decreases quadratically depending upon body-effect factor and the channel mobility, GM/IDS in the case of proposed d-Pi-OXJLT improves [33]. Further, the higher peak value of GM/IDS is desirable for the reduction in SCEs and SS (ln(10)/(GM/IDS)max) [52]. Fig. 12 shows the GMRO for the BPJLT and d-Pi-OXJLT with respect to VGS at VDS ¼ 1 V. It has been observed that GMRO of the d-Pi-OXJLT is higher than BPJLT counterparts due to the higher value of GM and the improvement in RO of the device.
252
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
Fig. 4. ID vs VGS characteristics of BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 5. ID vs VDS characteristics of BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 6. Variation of DIBL with LG for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
Fig. 7. Variation of subthreshold-swing (S) with LG for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 8. Variation of ION/IOFF with LG for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 9. Variation of intrinsic static power dissipation as a function of LG for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
253
254
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
Fig. 10. Variation of GM at VDS ¼ 1 V for LG ¼ 10 nm for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 11. Variation of GM/IDS at VDS ¼ 1 V for LG ¼ 10 nm for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 12. Variation of GMRO at VDS ¼ 1 V for LG ¼ 10 nm for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
255
Fig. 13. Variation of fT at VDS ¼ 1 V for LG ¼ 10 nm for BPJLT, SOIJLT and proposed d-Pi-OXJLT devices.
Fig. 13 shows the variation of fT as a function of VGS for BPJLT, SOIJLT and d-Pi-OXJLT. Here, the fT is calculated as [53] fT ¼ GM/ 2pCG. From the figure it can be observed that, due to significant improvement in GM, fT in the case of proposed d-Pi-OXJLT is higher in comparison to BPJLT and SOIJLT devices [54]. 5. Conclusions In this work a novel d-Pi-OXJLT has been proposed for nanoscale mixed signal integrated circuits. The detailed fabrication process flow of the novel d-Pi-OXJLT has also been presented in this paper. The results show that, incorporating partial buried oxide and d-doping in JLT not only reduces the OFF state leakage current but also reduces the short channel effects such as DIBL and SS of the device. Further, the digital and analog characteristics of proposed d-Pi-OXJLT have been investigated using 2-D simulations and compared with BPJLT and SOIJLT counterparts. It has been observed that, the digital parameters such as ION, IOFF, ION/IOFF, and PSTAT in the case of proposed d-Pi-OXJLT improves significantly over the BPJLT and SOIJLT devices. Further, the analog figures of merit such as GM, GM/IDS, GMRO and fT in the case of proposed d-Pi-OXJLT device also improve over the BPJLT and SOIJLT devices. This clearly shows that, in comparison to BPJLT and SOIJLT the proposed d-Pi-OXJLT is the promising device for nanoscale integrated circuits.
References [1] S.J. Choi, D.-I. Moon, S. Kim, J.P. Duarke, Y.K. Choi, Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistor, IEEE Electron Dev. Lett. 32 (02) (2011) 125e127. [2] C. Li, Y. Zhuang, Di Si, R. Han, Subthreshold Behavior Model for Nanoscale Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs, IEEE Trans. Electron Dev. 60 (11) (2013) 3655e3661. [3] H.-B. Chen, C.-Y. Chang, N.-H. Lu, J.-J. Wu, M.-H. Han, Y.-C. Cheng, Y.-C. Wu, Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel, IEEE Electron Dev. Lett. 34 (07) (2013) 897e899. [4] J.P. Duarte, S.J. Choi, D.-I. Moon, Y.K. Choi, Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistor, IEEE Electron Dev. Lett. 32 (06) (2011) 704e706. [5] T.K. Kim, D.H. Kim, Y.G. Yoon, J.M. Moon, B.W. Hwang, Dong-I1 Moon, G.S. Lee, D.W. Lee, D.E. Yoo, H.C. Hwang, J.S. Kim, Y.-K. Choi, B.J. Cho, S.-H. Lee, Frist Demonstration of Junctionless Accumulation-Mode Bulk FinFETs With Robust Junction Isolation, IEEE Electron Dev. Lett. 34 (12) (2013) 1479e1481. [6] Choi J-M. Jong-H, Y.-K. Choi, Analytical Threshold Voltage Model of Junctionless Double-Gate MOSFETs With Localized Charges, IEEE Tran. Electron Dev. 60 (09) (2013) 2951e2955. [7] T. Rudenko, R. Yu, S. Barraud, K. Cherkaoui, A. Nazarov, Method for Extracting Doping Concentration and Flat-Band Voltage in Junctionless Multigate MOSFETs Using 2-D Electrostatic Effects, IEEE Electron Dev. Lett. 34 (08) (2013) 957e959. [8] J.P. Colinge, et al., SOI Gated Register: CMOS without junction, in: SOI Conference, IEEE international, Foster city CA, 2009, pp. 1e2. [9] W. Vitale, et al., Monte Carlo Study Transport Properties in Junctionless transistor, in: Computational Electronic (IWCE), 2010, pp. 1e3. Pisa. [10] Moon D-I1, S.-J. Choi, J.P. Duarte, Y.-K. Choi, Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistor Built on a Bulk Substrate, IEEE Trans. Electron Dev. 60 (04) (2013) 1355e1360. [11] M.-H. Han, C.-Y. Chang, Y.-R. Jhan, J.-J. Wu, H.-B. Chen, Y.-C. Cheng, Y.-C. Wu, Characteristic of p-type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis, IEEE Electron Dev. Lett. 34 (02) (2013) 157e159. [12] D. Ghosh, M.S. Parihar, G.A. Armstrong, A. Kranti, High-Performance Junctionless MOSFETs for Ultralow-Power Analog/RF Applications, IEEE Electron Dev. Lett. 33 (10) (2012) 1477e1479. [13] M.S. Parihar, D. Ghosh, A. Kranti, Ultra Low Power Junctionless MOSFETs for Subthreshold Logic Applications, IEEE Trans. Electron Dev. 60 (05) (2013) 1540e1546. [14] C.-W. Chen, C.-T. Chung, J.-Y. Tzeng, P.-S. Chang, G.-L. Luo, C.-H. Chien, Body-Tied Germanium Tri-Gate Junctionless PMOSFET With In-Situ Boron Doped Channel, IEEE Electron Dev. Lett. 35 (01) (2014) 12e14.
256
G.C. Patil et al. / Superlattices and Microstructures 90 (2016) 247e256
[15] C.-H. Park, M.-D. Ko, K.-H. Kim, S.-H. Lee, J.-S. Yoon, J.-S. Lee, Y.-H. Jeong, Investigation of Low-Frequency Noise Behavior After Hot-Carrier Stress in an n-Channel Junctionless Nanowire MOSFET, IEEE Electron Dev. Lett. 33 (11) (2012) 1538e1540. [16] C.-W. Lee, R. Yan, I. Ferain, A. Kranti, N. Akhyan, P. Razavi, R. Yu, J. Colinge, Nanowire zero-capacitor DRAM transistor with and without junctions, in: Proc. 10th IEEE-nano, 2010, pp. 242e245. [17] A. Kranti, C. Lee, I. Ferain, R. Yan, N. Akhavan, P. Razavi, R. Yu, G.A. Armstrong, J. Colinge, Junctionless 6T SRAM cell, IET Electron Lett. 46 (22) (2010) 1491e1493. [18] S.-J. Choi, D.-I.1 Mooni, S. Kimi, J.-S. Leei, J.-Y. Kimi, Y.-K. Choii, Nonvolatile memory by all-around-gate junctionless transistor composed of silicon nanowire on bulk substrate, IEEE Electron Dev. Lett. 32 (05) (2011) 602e604. [19] G.C. Patil, S. Qureshi, Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits, Microelectron. J. 43 (05) (2012) 321e328. [20] S. Gundapaneni, M. Bajaj, R.K. Pandey, K.V.R.M. Murali, S. Ganguly, A. Kottantharayil, Effect of Band-to-Band Tunneling on Junctionless Transistor, IEEE Trans. Electron Dev. 59 (04) (2012) 1023e1029. [21] S. Gundapaneni, S. Ganguly, A. Kottantharayil, Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling, IEEE Electron Dev. Lett. 32 (03) (2011) 261e263. [22] S. Gundapaneni, S. Ganguly, A. Kottantharayil, Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor with high-k Spacers, IEEE Electron Dev. Lett. 32 (10) (2011) 1325e1327. [23] R.K. Baruah, R.P. Paily, Analog performance of Bulk Planar Junctionless Transistor, in: 3rd International Conference on Computing Communication and Network Technologies, 2012, pp. 1e4. Coimbatore, Tamilnadu, India. [24] H.-C. Lin, C.-I. Lin, Z.-M. Lin, B.-S. Shie, T.-Y. Huang, Characteristics of Planar Junctionless Poly-Si Thin-Film Transistor With Various Channel Thickness, IEEE Trans. Electron Dev. 60 (03) (2013) 1142e1148. [25] M. Golve, S. Gundapaneni, A. Kottantharayil, Novel Architecture for Zink-Oxide Junctionless Transistor, in: International Conference on Emerging Electronics, 2012, pp. 1e4. Mumbai, Maharashtra, India. [26] S.-H. Syu, J.-T. Lin, Y.-C. Eng, S.-W. Hsu, K.-Y. Chen, Y.-R. Lu, Junction Vs Junctionless Vertical MOSFET by Using Partial SOI Structure: A 2D Simulation Study, in: Junction Technology (IWJT), 2012, pp. 172e175. Shanghai. [27] G.C. Patil, V.H. Bonge, M.M. Malode, R.G. Jain, A Novel Partially Insulated Junctionless Transistor for Low Power Nanoscale Digital Integrated Circuits, in: Junction Technology (IWJT), 2012, pp. 172e175. Shanghai, IEEE 2nd International Conference on Emerging Electronics (ICEE) 2014;Banglore, India, 1-4. [28] U. Khan, B. Ghosh, M.W. Akram, A. Salimath, A comparative study of SELBOX-JLT and SOI-JLT, Appl. Phys. A 117 (4) (2014) 2281e2288. [29] C.-W. Lee, A. Afzalian, N.D. Akhayan, R. Yan, I. Ferain, J.-P. Colinge, Junctionless Multigate Field-Effect Transistor, Appl. Phys. Lett. 94 (05) (2009), 053 511-1e053 511e2. [30] G. Leung, C.O. Chui, Variability impact of random dopant on nanoscale junctionless FinFETs, IEEE Electron Dev. Lett. 33 (06) (2012) 767e769. [31] A. Gnudi, et al., Analysis of threshold voltage variability due to random dopant fluctuation in junctionless FETs, IEEE Electron Dev. Lett. 33 (03) (2012) 336e338. [32] M. Aldegunde, A. Martinez, J.R. Barker, Study of discrete doping induced variability in junctionless nanowire MOSFETs using dissipative quantum transport simulation, IEEE Electron Dev. Lett. 33 (02) (2012) 194e196. [33] G.C. Patil, S. Qureshi, A novel d-doped partially insulated dopant-segregated Schottky barrier SOI MOSFET for analog/RF application, Semicond. Sci. Technol. 26 (08) (2011) 085002e085013. [34] M.J. Kumar, A.A. Orouji, Investigation of a new modified source/drain for diminished self-heating effects in nanoscale MOSFETs using computer simulation, Phys. E 33 (2006) 134e138. [35] K.H. Yeo, et al., A partially insulated field effect transistor (PiFET) as a candidate for scaled transistor, IEEE Electron Dev. Lett. 25 (06) (2004) 387e389. [36] G.C. Patil, S. Qureshi, A Novel Partially Insulated Schottky Source/Drain MOSFET: Short Channel and Self Heating Effects, in: International Conference on Microelectronics, 2010, pp. 252e255. Cairo, Egypt. [37] S.A. Loan, S. Qureshi, S.S.K. Iyer, A Novel Partial-Ground-Plane-Based MOSFET on Selective Buried Oxide: 2-D Simulation Study, IEEE Trans. Electron Dev. 57 (3) (2010) 671e680. [38] F. Bashir, S.A. Loan, M. Rafat, A.R.M. Alamoud, S.A. Abbasi, A High-Performance Source Engineered Charge Plasma-Based Schottky MOSFET on SOI, IEEE Trans. Electron Dev. 62 (10) (2015) 3357e3364. [39] K. Noda, T. Tatsumi, T. Uchida, K. Nakajima, H. Miyamoto, C. Hu, A 0.1-mm delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy, IEEE Trans. Electron Dev. 45 (04) (1998) 809e814. [42] R.K. Baruah, R.P. Paily, A Dual-Material Gate Junctionless Transistor With High-k Spacer for Enhanced Analog Performance, IEEE Trans. Electron Dev. 61 (01) (2014) 123e128. [43] H. Lou, L. Zhang, Y. Zhu, X. Lin, S. Yang, J. He, M. Chan, A Junctionless Nanowire Transistor With a Dual-Material Gate, IEEE Trans. Electron Dev. 59 (07) (2012) 1829e1836. [44] G.C. Patil, S. Qureshi, Engineering spacer in dopant-segregated schottky barrier SOI MOSFET for Nanoscale CMOS circuits, Semicond. Sci. Technol. 27 (04) (2012) 045004. [45] A. Majumdar, X. Wang, A. Kumar, J.R. Holt, D. Dobuzinsky, R. Venigalla, C. Ouyang, S.J. Koester, W. Haensch, Gate length and performance scaling of undoped-body extremely thin SOI MOSFETs, IEEE Electron Dev. Lett. 30 (04) (2009) 413e415. [46] Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chang, P.K. Ko, Y.C. Cheng, Threshold voltage model for deep-submicrometer MOSFETs, IEEE Trans. Electron Dev. 40 (01) (1993) 86e95. [47] C. Li, Y. Zhuang, S. Di, R. Han, Subthreshold Behavior Model for Nanoscale Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs, IEEE Trans. Electron Dev. 60 (11) (2013) 3655e3662. [48] R.K. Baruah, R.P. Paily, Estimation of Process-Induced Variations In Double-Gate Junctionless Transistor, in: 5th International Conference on Computers and Devices for Communication, 2012, pp. 1e4. Kolkata, India. [50] W. Long, H. Ou, J. Kuo, K. Chin, Dual-material gate (DMG) field effect transistor, IEEE Trans. Electron Dev. 46 (05) (1999) 865e870. [51] J.-P. Colinge, Fully-depleted SOI CMOS for analog application, IEEE Trans. Electron Dev. 45 (05) (1998) 1010e1016. [52] D. Ghosh, M.S. Parihar, A. Kranti, Optimizing Nanoscale MOSFET Architecture for Low Power Analog/RF Application, in: 5th International Conference on Nanoelectronics, 2013, pp. 22e23. Singapore. [53] S. Cho, K.R. Kim, B.-G. Park, I.M. Kang, RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs, IEEE Trans. Electron Dev. 58 (05) (2011) 1388e1396. [54] P. Kumar, S. Singh, A. Dixit, P. Kondekar, Digital and Analog Performance of Gate Inside p-type Junctionless Transistor (GI-JLT), in: 5th International Conference on Computational Intelligence, Modelling and Simulation, 2013, pp. 394e397. Seoul, South Korea.