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On the robustness of LDD and nMOS transistors subjected to measurement of drain breakdown voltage
286
World Abstracts on Microelectronics and Reliability
testing for days, weeks, or months during which a variety of characteristics should be monitored under perhaps several different operating conditions. Normally this would involve a prohibitive input of manpower, and consequently longterm brush tests tend to be less than satisfactory. In response to this need, an automated testing system has been developed in which a personal computer both controls test parameters for a matched brush pair running on the same rotor according to a pre-selected program, and stores test data. Specifically controlled are the brush forces, brush polarity, and the current. Specifically monitored are the voltage drops across each of the two brushes, their wear, and the rotor temperature. Additionally, "traverses", meaning brief periods of ramping the current up and down between pre-selected limits while measuring the associated voltage drops, can be programmed into the tests. The duration of the various phases in complex testing programs as well as the intervals between data-taking can be varied between seconds and months, but the system is switched off automatically when the voltage across either of the two brushes or the rotor temperature exceeds a pre-selected value. The accumulated data can be recalled in various graphical representations and program changes can be made at any time without interrupting the test.
Dynamic behaviour of SMT chip capacitors during solder reflow. JOHN R. ELLIS and GLENN Y. MASADA.IEEE Trans. Compon. Hybrids mfg Technol. 13(3), 545 (1990). A dynamic model of a surface mount packaging technology (SMT) type 1206 chip capacitor is developed in this paper. The model is used to determine the effects of pad geometry, chip metallization and dimensions, solder volume, and chip displacement on the ability of the chip to lift (tombstone) and to self-align during solder reflow. Both static and dynamic characterizations are shown. The model simulations show that the chip capacitor will begin to lift initially for some geometries but tombstoning does not appear to be a problem. Thus to help the self-alignment capabilities, the simulations show that system configurations with smaller pad lengths, smaller pad gaps, larger solder volume, and smaller metallization are best. These conclusions are supported by existing recommendations based upon experimental tests. The model is a powerful tool that can be used to optimize these system parameters. Electro-optic sampling of high-speed devices and integrated circuits. J. M. WIESENFELD.I B M J. Res. Dev. 34, 141 (1990). The operating speeds of the fastest electronic devices and integrated circuits (ICs) have surpassed the capabilities of conventional electronic measurement instrumentation. Electro-optic sampling is an optical probing technique which has ultrashort temporal resolution and is capable of noninvasively probing ICs at internal nodes. This technique is voltage-sensitive because it relies upon the electric field produced by the signal voltage on the device under test (DUT). The electric field (and hence the voltage) can be sampled because it produces birefringence in an electro-optic crystal which changes the state of polarization of an ultrashort-duration optical probe pulse that propagates through the electro-optic crystal. The electro-optic crystal is the substrate of the DUT for direct probing, is a crystal on a separate test structure for hybrid probing, and is a separate crystal placed above the DUT for external probing, Temporal resolution below 1 ps and a sensitivity below 0.1 mV/x/Hz have been demonstrated (though not in the same experiment). The principles of electro-optic sampling are
3. C I R C U I T
AND
SYSTEMS
RELIABILITY,
Bayes credibility estimation of an exponential parameter for random censoring and incomplete information. T. ELPER1N and I. GERTSBACKH.IEEE Trans. Reliab. 39(2), 204 (1990).
reviewed in this paper. Selected applications for measurement of high-speed waveforms in discrete devices and in ICs are presented.
Hi-Q chip model ceramic capacitors handle high frequencies. TETSUHIRO SH1OTAand SHINICH10HKUBO. JEE (Japan), 44 (March 1991). To reduce attenuation of signals and power loss during passage through high frequency capacitors, the Q value of certain recently developed capacitors is high compared with that of other general-use capacitors. In this report, the advantages of high Q values, the technology to increase the Q value and new products with copper electrodes are introduced. Chip technology now available for aluminum electro-lytic capacitors. YOSHISHIGE IKEDA. JEE (Japan), 36 (March 1991). Communications equipment makers show steady progress in developing miniature, personal products that incorporate multiple functions and offer more attractive performances, compared with conventional models. Behind these advances lie incessant efforts to improve assembly technology, reduce chip component size and enhance performance through the use of surface mount technology (SMT). Adoption ofchip technology was delayed in the field of aluminum electrolytic capacitors, but capacitor manufacturers have progressed rapidly in development and the technology has advanced with significant achievements in the past few years. Thermal breakdown in GaAs MES diodes. A. J. FRANKLIN, V. M. DWYER and D. S. CAMPBELL. Solid-St. Electron. 33(8), 1055 (1990). A thermal breakdown analysis of planar GaAs metal-semiconductor diodes is presented and three models relating failure power (Pf) to corresponding failure times (tf) are compared. The standard Wunsch and Bell model, a modified form of the Tasca model, and a threedimensional model (developed by the authors) are fitted to experimental data. The results indicate that, within given failure time domains, GaAs structures of this kind follow the same general patterns, pfc~: t f q, as those previously reported for silicon semiconductor devices. There is one exception. In the time domain roughly between l and 20 #s, the failure power is given by Pf oc I/loge(tf). Analytic expressions are used to extract three "defect" dimensions from forward bias experimental data. These "defect" dimensions are discussed with reference to the device dimensions and the ambient temperature. Two distinct visible and electrical failure modes have been observed and these are linked to changes in the channel conductance subsequent to an applied pulse.
On the robustness of LDD and nMOS transistors subjected to measurement of drain breakdown voltage. SHIANAUR and AMITAVACHATTERJEE.Solid-St. Electron. 33(8), 1043 (1990). An increase in the subthreshold current of lightly-dopeddrain (LDD) nMOSFETs was observed after drain breakdown voltage measurement with grounded source, gate and substrate (BVdss). A new snapback phenomenon with very low threshold current was found to correlate with the susceptibility of the nMOS to damage during BVdss measurement stress. The threshold current to snapback was found to be as low as 1 nA. This phenomenon cannot be explained by the usual bipolar action model. This paper discusses the related reliability issue and process modifications to improve the device robustness.
MAINTENANCE
AND
REDUNDANCY
A Bayes interval estimation is investigated for an exponential parameter 0 in a model of random censoring with incomplete information. The instant of item failure is
World Abstracts on Microelectronics and Reliability
testing for days, weeks, or months during which a variety of characteristics should be monitored under perhaps several different operating conditions. Normally this would involve a prohibitive input of manpower, and consequently longterm brush tests tend to be less than satisfactory. In response to this need, an automated testing system has been developed in which a personal computer both controls test parameters for a matched brush pair running on the same rotor according to a pre-selected program, and stores test data. Specifically controlled are the brush forces, brush polarity, and the current. Specifically monitored are the voltage drops across each of the two brushes, their wear, and the rotor temperature. Additionally, "traverses", meaning brief periods of ramping the current up and down between pre-selected limits while measuring the associated voltage drops, can be programmed into the tests. The duration of the various phases in complex testing programs as well as the intervals between data-taking can be varied between seconds and months, but the system is switched off automatically when the voltage across either of the two brushes or the rotor temperature exceeds a pre-selected value. The accumulated data can be recalled in various graphical representations and program changes can be made at any time without interrupting the test.
Dynamic behaviour of SMT chip capacitors during solder reflow. JOHN R. ELLIS and GLENN Y. MASADA.IEEE Trans. Compon. Hybrids mfg Technol. 13(3), 545 (1990). A dynamic model of a surface mount packaging technology (SMT) type 1206 chip capacitor is developed in this paper. The model is used to determine the effects of pad geometry, chip metallization and dimensions, solder volume, and chip displacement on the ability of the chip to lift (tombstone) and to self-align during solder reflow. Both static and dynamic characterizations are shown. The model simulations show that the chip capacitor will begin to lift initially for some geometries but tombstoning does not appear to be a problem. Thus to help the self-alignment capabilities, the simulations show that system configurations with smaller pad lengths, smaller pad gaps, larger solder volume, and smaller metallization are best. These conclusions are supported by existing recommendations based upon experimental tests. The model is a powerful tool that can be used to optimize these system parameters. Electro-optic sampling of high-speed devices and integrated circuits. J. M. WIESENFELD.I B M J. Res. Dev. 34, 141 (1990). The operating speeds of the fastest electronic devices and integrated circuits (ICs) have surpassed the capabilities of conventional electronic measurement instrumentation. Electro-optic sampling is an optical probing technique which has ultrashort temporal resolution and is capable of noninvasively probing ICs at internal nodes. This technique is voltage-sensitive because it relies upon the electric field produced by the signal voltage on the device under test (DUT). The electric field (and hence the voltage) can be sampled because it produces birefringence in an electro-optic crystal which changes the state of polarization of an ultrashort-duration optical probe pulse that propagates through the electro-optic crystal. The electro-optic crystal is the substrate of the DUT for direct probing, is a crystal on a separate test structure for hybrid probing, and is a separate crystal placed above the DUT for external probing, Temporal resolution below 1 ps and a sensitivity below 0.1 mV/x/Hz have been demonstrated (though not in the same experiment). The principles of electro-optic sampling are
3. C I R C U I T
AND
SYSTEMS
RELIABILITY,
Bayes credibility estimation of an exponential parameter for random censoring and incomplete information. T. ELPER1N and I. GERTSBACKH.IEEE Trans. Reliab. 39(2), 204 (1990).
reviewed in this paper. Selected applications for measurement of high-speed waveforms in discrete devices and in ICs are presented.
Hi-Q chip model ceramic capacitors handle high frequencies. TETSUHIRO SH1OTAand SHINICH10HKUBO. JEE (Japan), 44 (March 1991). To reduce attenuation of signals and power loss during passage through high frequency capacitors, the Q value of certain recently developed capacitors is high compared with that of other general-use capacitors. In this report, the advantages of high Q values, the technology to increase the Q value and new products with copper electrodes are introduced. Chip technology now available for aluminum electro-lytic capacitors. YOSHISHIGE IKEDA. JEE (Japan), 36 (March 1991). Communications equipment makers show steady progress in developing miniature, personal products that incorporate multiple functions and offer more attractive performances, compared with conventional models. Behind these advances lie incessant efforts to improve assembly technology, reduce chip component size and enhance performance through the use of surface mount technology (SMT). Adoption ofchip technology was delayed in the field of aluminum electrolytic capacitors, but capacitor manufacturers have progressed rapidly in development and the technology has advanced with significant achievements in the past few years. Thermal breakdown in GaAs MES diodes. A. J. FRANKLIN, V. M. DWYER and D. S. CAMPBELL. Solid-St. Electron. 33(8), 1055 (1990). A thermal breakdown analysis of planar GaAs metal-semiconductor diodes is presented and three models relating failure power (Pf) to corresponding failure times (tf) are compared. The standard Wunsch and Bell model, a modified form of the Tasca model, and a threedimensional model (developed by the authors) are fitted to experimental data. The results indicate that, within given failure time domains, GaAs structures of this kind follow the same general patterns, pfc~: t f q, as those previously reported for silicon semiconductor devices. There is one exception. In the time domain roughly between l and 20 #s, the failure power is given by Pf oc I/loge(tf). Analytic expressions are used to extract three "defect" dimensions from forward bias experimental data. These "defect" dimensions are discussed with reference to the device dimensions and the ambient temperature. Two distinct visible and electrical failure modes have been observed and these are linked to changes in the channel conductance subsequent to an applied pulse.
On the robustness of LDD and nMOS transistors subjected to measurement of drain breakdown voltage. SHIANAUR and AMITAVACHATTERJEE.Solid-St. Electron. 33(8), 1043 (1990). An increase in the subthreshold current of lightly-dopeddrain (LDD) nMOSFETs was observed after drain breakdown voltage measurement with grounded source, gate and substrate (BVdss). A new snapback phenomenon with very low threshold current was found to correlate with the susceptibility of the nMOS to damage during BVdss measurement stress. The threshold current to snapback was found to be as low as 1 nA. This phenomenon cannot be explained by the usual bipolar action model. This paper discusses the related reliability issue and process modifications to improve the device robustness.
MAINTENANCE
AND
REDUNDANCY
A Bayes interval estimation is investigated for an exponential parameter 0 in a model of random censoring with incomplete information. The instant of item failure is