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P1396: a proposed standard communications bus
P1396: a proposed standard communications bus Moves by the computer industry towards open systems and by the telecommunications industry towards digital networks of all sizes bring with them the need for an international standard backplane bus for integrated voice-data networks. Gary A Nelson reports the progress on such a standard through the IEEE P1396 working group
P1396 is a standards effort to develop a 'hybrid' backplane bus that combines synchronous time division multiplexing for circuit switching with a scheme that allows multiple users to access the bus for the transfer of variable-length packet data. The bus is intended to operate at speeds up to 20 Mbyte s -7 and to be synchronized either to the telephony rate of 8000 frames or to a video frame for image processing applications. The paper introduces the P1396 specification and reviews the standards work that has been done, and that remains to be done, by the IEEE P1396 working group. Applications such as metropolitan area networks and distributed office communications are discussed, as is the functional design of the bus. microsystems P1396
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The purpose of this paper is to introduce the standards work being done by the P1396 working group of the IEEE Microprocessor Standards Committee (MSC). That group is chartered to define a specification for a combined packet and time-division backplane bus and package for circuit switching, packet switching and multiplexing applications. The bus speed is intended to match that of the new transmission standard for worldwide communications called Synchronous Optical Network (Sonet); as of January 1988, that speed is 51.840 M b i t s -~. Sonet allows multiple signals to be byte interleaved to create higher-rate signals. The Sonet-3 signal (155.520 Mbit s -1) Networksand CommunicationsDivision,NationalSemiconductorCorp., 2900 Semiconductor Drive, PO Box 58090, Santa Clara, CA 95052578090~USA Currentaddress:Ameritech Inc.,Schaumburg,IL, USA Paperrevised:11 January1988
is under consideration by CCITT as an international synchronous transmission signal. (The format of the Sonet signal appears to be under pressure to undergo another revision from 51.84 Mbit s -1 to a speed in the neighbourhood of the Sonet-3 signal, but at the time of writing, no decisions have been reached.) Because some of the primary target applications of P1396 are in Sonet-based communications equipment and, because Sonet is inherently byte oriented~ the P1396 bus is byte wide. To simplify configuration requirements, a bidirectional bus is required (i.e. the clock source can be in any slot). The Sonet-3 speed divided by eight yields a bus speed of 19.44 MHz which is feasible using a 16 inch (40 cm) bus and currently available transceiver technology. The P1396 specification is building upon existing standards wherever possible. For this reason, the IEEE 1101 packaging standard for computer equipment is recommended. Conformance to the Bellcore network equipment building system (NEBS)1 is also required for products that will be used in the public telephone network. A variety of applications are envisaged for the P1396 hybrid communications bus, ranging from multiplexers, remote switching units and digital subscriber carrier modules to private branch exchanges (PBXs). Most communications applications require independent transmit and receive buses. Therefore, P1396 provides multiples of two sub-buses per connector. The original concept embraced by the working group was to use 96-pin DIN connectors as specified in IEEE 1101. However, the requirement to be able to perform live insertion and removal of modules without using any 'precharging' umbilical cable (as is specified in IEEE 896 Futurebus) has caused the selection of a new connector to be the working group's highest-priority work item. Considerable attention is being given to fault tolerance and maintainability. Bus and signal parity lines are used to
01 41-9331/88/031 39-08 $03.00 © 1988 Butterworth & Co. (Publishers) Ltd Vol 12 No 3 April 1988
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provide error detection. Optional bus redundancy ~s provided by allowing bus duplication. Error recovery and maintainability require live insertion and removal of cards, machine readable part or serial numbers for all modules and comprehensive diagnostics. A card-level maintenance history could be held in write-once memory on each card, eliminating tracking errors that occur when the maintenance database gets out of step with reality. In add-drop multiplexer applications, part of the network bandwidth will be dropped onto the receive bus, the same amount of bandwidth being inserted onto the network from the transmit bus and the remainder being 'through connected'. The added and dropped time slots are tagged as active or 'isochronous' by signal lines called ISOCHRONOUS__INDICATION (and ISOCHRONOUS_ INDICATION_INVERSE). The through connected bandwidth also maps onto the bus as 'not isochronous', i.e. the ISOCHRONOUS__INDICATION signal is unasserted; the bus is essentially idle for those time slots. P1396 provides a means to employ this through connected, idle, unused bandwidth for variable-length packet transmission between cards within the 'crate'. As the instantaneous demand for isochronous (through connected) bandwidth changes by 8, the available packet bandwidth changes by - 8; the packet access method merely skips over all bytes (time slots) presently involved in add-drop circuit switched connections. The packet bandwidth can be used for intermodule control information, or for transport of user packet information between modules. Redundant serial buses (under development by the P1394 committee*) may optionally be employed for offcrate communications or for enhancement of fault tolerance. This is a subject for future study. The system speed may be scaled by using multiple sub-buses or multiple connectors or both.
TOWARDS AN OPEN ARCHITECTURE Major trends: standards and distributed systems The telecommunications industry is moving inexorably towards the integration of digital voice, data and image transmission (and processing) in networks of all sizes, from local to worldwide. In addition, the confluence of industry, technical and regulatory forces including VLSI, fibre optics, standards (such as ISDN, LAN standards and the Open Systems Interconnect model), deregulation of the telecommunications industry and Open Network Architecture continues to increase the economic benefits of distributed systems. The computer industry was the first to experience the impact of 'going distributed'. It is now practical to combine distributed computing and telephony technologies to build truly distributed office communications systems that combine the best features of LANs, voice PBXs, data switches and multiplexers in a single unified system. The traditional centralized star PBX architecture is slowly giving way to a distributed architecture that will be composed of many small 'departmental' switching and processing nodes interconnected with a high-speed fibre optic backbone. *Further information is availablefrom Mike Teener, chairman of the P1394 committee. Telephone(USA):(408) 721-5897
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Similarly, the switching and trar~mission elements ot the telephone networks are undergoing a transition towards fibre optic networks that will be populated with intelligent multiplexers, cross connects and remote switches combined with distributed computing machines .... an intelligent network with increasing decentralization of both switching and control 2,
P1396: a market-driven need In this context, there is a clear need for an international standard defining a backplane bus and package for the different functional boxes that will be found in the integrated voice-data local, metropolitan and long-haul networks of the 1990s and beyond. The primary goal of the P1396 effort is to do for the communications systems market what VME has done for [he computer-based systems business. Among the beneficiaries of a standard cabinet wilt be the operating telephone companies who will be able to configure application-specific systems from standard modules. Proprietary systems are no longer acceptable to many operating companies because of the high cost of • maintaining inventories of functionally equivalent but noninterchangeable spares • hiring and training maintenance specialists in eacil of the several functionally identical but operationally and physically different proprietary systems • managing and planning networks based an a vadety of similar but needlessly different proprietary modules. Suppliers that have traditionally benefitted from 'account management' through the exploitation of the proprietary nature of their equipment may initially oppose this level of standardization. In the end, however, such an initiative cannot be stopped. Operating companies may eventually be allowed to operate their own systems integration and software organizations, building up their own product solutions for specific markets from standard modules available from a variety of sources. The established manufacturers can resist the inevitable and lose market share, or take an aggressive leadership role and be the dominant OEMs.
Metropolitan networks Figure 1 depicts a possible intelligent optical metropolitan network for the early 1990s, providing such features as • flexible configuration and reconfiguration of bandwidth for the purpose of load levelling of the network traffic • virtual private networks for the customer • local area network (LAN) interconnection with LAN performance. Universal access m o d u l e
Universal access modules (UAMs) interface to Sonet on the network side (providing add-drop services of almost arbitrary data rates onto the P1396 backplane) and to all economically interesting user access protocols on the other -- analogue, ISDN basic and primary access, DS-2, DS-3, Ethernet, 802.5 token ring, FDDI, 802.9 CO-LAN, X.25 and so forth. The cost effectiveness of providing
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POTS or ISDN basic access from a P1396 box is a controversial subject. One point of view is that the box will be more expensive than a conventional subscriber line carrier and will not be viable. Another point of view is that the real cost of ownership of such equipment is dominated by operational costs and not by the initial cost. Reduction of spares inventories, simplification of maintenance personal training, increased flexibility in delivery of services and related economies may offset a higher initial cost. We must assume that cost studies are in progress to clarify this issue. UAMs conform to the NEBS specification 1 and employ the P1396 backplane bus. UAMs are populated with standard modules to perform both functions that are now done with proprietary equipment, and functions that are still 'on the drawing board'. These standard access modules talk to the P1396 backplane bus and provide a second-level add-drop function to deliver circuit switched connections to the active users connected to those cards. In addition, access cards using packet services will employ the packet capabilities of the P1396 bus to transfer variable-length packets between relevant cards - - a user's Ethemet access card and the MAN multimegabit data service backbone interface card, for example. One specific card size suitable for public switching
Vol 12 No 3 April 1988
applications is 3 U × 2 2 0 m m . To employ IEEE 1101 standard packaging, 19 inch (48 cm) racks are recommended. It may be a recommended practice (but not part of the standard) to put power converters and/or cabling in the spaces available between each end of a card cage and the 23 inch (58 cm) telephone equipment rails. An example of a UAM based on these standards is shown in Figure 2. Taking one example application - - the integrated services digital network (ISDN) - - in many areas the demand for ISDN will not justify the replacement of analogue central office switches that are not yet fully depreciated. In such cases, a UAM can be configured as a remote switch attached to a distant ISDN central office. In another application, the UAM could be populated with analogue line cards to do the job of a subscriber line carrier module. The UAM is not limited to analogue lines, however; ISDN lines can also be supported. In this manner, the UAM concept is not inconsistent with Bellcore's universal digital carrier concept 2, 3 ISDN basic access at 144 kbit s-~ will not be sufficient for personal computer users accustomed to LAN performance. A standard central office LAN (CO-LAN) will therefore evolve that operates on twisted pair wiring and offers over 1 Mbit s-1 performance, probably at the ISDN
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primary rate of 1.544 or 2.048 Mbit s-~, (The IEEE802.9 committee is chartered to work on customer equipment, so this application of 802.9 is not 'official', but the need is real and thus presents an opportunity to apply the technology to intelligent networks to help provide 'centrex knock-offs' of so-called fourth-generation PBXs.) IVD/LAN workstation
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in IEEE802.6 (QPSX). However, voice services can already be provided using add-drop technology, so the real unmet need is for high-speed packet data for interconnecting various user LANs and mainframes. For a considerable time, the DS-3 rate of 44.736 Mbit s -1 will be the only ubiquitous offering. A need exists, therefore, for a DS-3 rate backbone for user LANs.) In the late 1990s and beyond, the author expects to see a migration to an all packet network based on the 'new transfer mode' work being done in the T1D1.1 committee. It is a design goal of P1396 to be able to accommodate 'new-transfer-mode, fast-packet, asynchronous time-division multiplexing' or whatever name becomes permanently attached to the service. The above examples are intended to convey the concepts important to this work, and not any particular embodiment or solution. The number of single- and double-high cards chosen for this example is reasonable, but is not a necessary part of the developing specification. One of the specific advantages of the I EEE1101 packaging standard is that a number of vendors make 'erector sets' that can be configured to practically any requirement. Thus a particular UAM could use the building blocks described here, and still be tailored to the requirements of a specific application.
Distributed office communications A fibre optic voice-and-data 'integrated services local network' (ISLN), known as ANSC X3T9.5 FDDI-II, will most likely become a standard within the next 12-18 months. Figure 3 depicts the types of equipment that can be expected to attach to such systems. Given that the ISLN itself will be a standard, as are practically all the access methods to the ISLN (X.25, ISDN, 802 LANs etc.) it is a natural extrapolation to standardize the node backplane and package.
the public network. For example, no depth or card height restrictions exist except those imposed by the constraints of good design and economics. Rear access is generally acceptable, even preferred. Next-generation 'ISLN-PBXs' will provide considerable computing power, and will therefore require a standard computer bus. Figure 4 shows a possible ISLN node configuration. It would be premature to speculate as to whether the cards from the UAM described below will be usable in ISLN office systems, but it would clearly be a most satisfactory situation if standard modules were available for analogue access, ISDN basic access, ISDN primary access, X.25 access, I_AN access etc.
PACKAGING ISSUES I / O considerations Figure 5 depicts the option of having I/O cabling terminate on the fronts of cards. From a maintainability standpoint, this is undesirable, at least in the USA. At least one major European telecommunications vendor successfully uses the '1/O on the front' approach, however. I/O can be put on the rear using small adapter cards that connect onto the back side of the backplane bus as shown in Figure 6. Surface-mount technology is being considered for this.
P 1 3 9 6 BUS FUNCTIONAL DESIGN Transceiver functional characteristics The P1396 bus will employ the same open collector transceiver technology as defined for I EEE896 Futurebus 4.
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CONTROL__INDICA TION The control indication bit can be viewed as a ninth data bit modifying the meaning of the eight data bits. Control indication will be interpreted in conjunction with isochronous indication. When isochronous indication is unasserted, control indication will determine whether the associated byte is control (asserted) or data (unasserted).
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indication is asserted) or packet switched (when isochronous indication is not asserted). Thus, idle time slots default to packet switched mode. This signal is pipelined one time slot relative to data and control and is sourced by the same card that provides clock and frame synchronization. This implies that cratewide time slot management is a centralized function.
ISOCHRONOUS__INDICA TION_JNVERSE This signal is included solely for error detection. It is effectively an odd-parity indication of ISOCHRONOUS_ SYNC INDICATION. Like isochronous indication, it is pipelined one time slot.
ARBITRATION The arbitration signal is used to control access to the bus for the purpose of packet transfers. The details of the method are described below.
ARBITRA TION__INVERSE As for ISOCH RONOUS_IN DICATION_INVERSE, corruption of the arbitration signal must be detectable instantly to deter multiple masters from erroneously taking control of the bus.
CLOCK__INDICATION The clock indication signal is produced by a master clock source located on a card which, in general, will be redundant. The clock source may be on a card with other functions, such as a network interface, or it may be a single-function card.
SYNC__INDICA T/ON SYNC__INDICATION is also sourced by the master clock module that is providing the timing reference for the entire crate. The signal will normally be high (false) and will be asserted by the source for at least one CLOCK__ INDICATION interval. In Sonet applications, this signal will be asserted for two, four or six clock times to correspond to the two bytes of the frame word for each Sonet synchronous transport signal (STS). The 155.520 Mbit s -1 STS-3 signal for which the P1396 bus is designed will therefore require that SYNC_INDICATION be asserted for six time slots. ISOCHRONOUS__ INDICATION and ISOCHRONOUS__INDICATION__ INVERSE are both ignored duringthe SYNC__INDICATION interval. In telephony applications, this signal will occur at a nominal rate of 8000 Hz.
Isochronous data transfer Conventional time switching will be accomplished by the module which sources data into a time slot for which the corresponding isochronous indication bit is asserted. Allocation of time slots will be accomplished by management entities, the details of which are beyond the scope of the present work. The P1396 working group intends to address this class of issues in a P1396.2 project, which will be aimed at protocols above the physical and media access layers.
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Nonisochronous data transfer Packet or nonisochronous or burst-mode traffic will be transported across the backplane bus using all the bandwidth not presently allocated and labelled as isochronous time slots (ISOCHRONOUS_INDICATION = logic 1). In this manner, the P1396 hybrid bus provides variable allocation between the two types of service at a granularity of one time slot or 64 kbit s-1. Of equal importance to granularity is the ability to label individual bytes. This allows maximum flexibility in allocation and deallocation of isochronous bandwidth.
Minimum channel for management signalling Because packet-mode messages may be used for management of all the modules in a crate, it is imperative that there is no possible case where all the time slots can be designated as isochronous. This would result in a deadlocked bus, because no messages could be sent to deallocate the slots. Accordingly, the P1396 protocol will always treat the time slot(s) associated with SYNC_ INDICATION as nonisochronous regardless of the state of the associated ISOCHRONOUS_INDICATION (and inverse) bits. This guarantees a minimum of 64 kbit s -1 packet bandwidth even if the ISOCHRONOUS__ INDICATION (and inverse) bits become stuck in some illegal state. In Sonet applications, six bytes are occupied by frame synchronization information. In these applications, SYNC_INDICATION can be asserted for six clock periods and provide 384kbits -1 for management signalling.
Packet transfer protocol The packet transfer protocol consists of three phases: the access or arbitration phase, the data transfer phase and the acknowledgement phase.
Access or arbitration phase Slotted serial arbitration has been proposed 5. Arbitration slots of approximately 9 bit are defined. Intent to arbitrate is signalled by assertingthe first bit in a slot; then the 5-bit arbitration address is driven onto the line, least significant bit first. Any module that sent a logic 0 (unasserted) and saw a logic I (asserted) has lost the arbitration and retires from the process. After five bits, the winner continues to assert ARBITRATION until capturing the bus. The master elect monitors the bus for an idle state (data, control and isochronous bits all unasserted) for two slot times. Upon seeing the idle state, the master elect captures the bus by first sending a START__ DELIMITER followed by the rest of the packet, and then releasingARBITRATION to allow the next arbitration to occur. Priority and fairness are provided by assigning priority to all even arbitration slots, and fairness to all odd arbitration slots. In priority mode, the highest numbered competitor wins the bus; in fairness mode, a winner cannot arbitrate again until all other contenders have had use of the bus.
Transfer phase Once the master elect has become the master, a variablelength packet is transferred using a format that is based on the IEEE 802.2 logical link control (LCC) packet data unit
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(PDU) format 6. Media access control protocol constructs are used to delineate the start and end of packets. The acknowledgement phase borrows the 'addressed-copied' concept from the 802.5 and FDDI token rings. The variable-length acknowledgement concept is borrowed from the work being done in the P1394 serial bus committee. The 'null' control character is suggested to handle underrun situations where the transmission of a packet is interrupted because the transmitting processor or DMA logic failed to keep up with the demands of the bus. If nulls are sent, the packet can be sent without error in spite of the underrun. This prevents a heavily loaded bus from experiencing a further increase in demand to handle rejected packets.
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NOUS_INDICATION__INVERSE lines, arbitration will proceed in the normal manner and the only valid time slots for packet data will be those time slots which coincide with SYNC__INDICATION. Depending on the system application, this may be from one to six slot times.
Maintainability Live insertion and removal of modules All equipment built to the P1396 standards will support live insertion and removal of modules without interruption of service, The suitability of the DIN connector specified in IEEE 1101 is in doubt for this requirement. Other IEEE1101-compatible connectors are being studiedl
A variable-length packet format is proposed for use in the acknowledgement phase. This would allow a slave module to return an arbitrary-length packet of information without arbitrating for the bus. The construct will allow a master to poll a collection of slaves and get responses without requiring the slaves to arbitrate. An alternative view is that the master could read a register or block from the slave. This concept affords considerable flexibility by supporting the following.
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• Single-master polling: a single master polls slave cards. • Multimaster polling: two or more bus masters contend for the bus and then poll the slave cards. The population of slave cards could be shared among the masters or specific slaves could be allocated to their own 'master'. A second master could be used for redundancy. • Multiple access: the bus functions as an intracrate LAN. The acknowledgement phase is limited to 'addressedcopied' single-byte transfers. • Dumb slave boards can be controlled by read and write operations; thus there is no requirement for all boards to be 'smart'. • Intelligent boards can use multiple access for normal operations and read/write operations for board-level diagnostics.
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Each pluggable module will provide, as a minimum, a machine readable part number. Machine readable serial numbers, hardware revision levels, firmware revision levels, software applicability codes and other productspecific information can be supported based on this part number. These data may be accessed using the read operation described earlier. Thus even dumb cards can support this function.
Depending upon user and manufacturer preferences, each module may provide sufficient write-once memory to accommodate the entire service history of that module. The format for this data is beyond the scope of the present effort.
CONCLUSIONS At this stage of the P1396 committee work, there are many more questions than conclusions. It seems clear that P1396 is addressing a genuine market need and that timely completion of the standard will benefit the industry. The committee intends to have a draft standard ready for initial working group ballot by July 1988.
Error detection Parity will be used to detect errors on data and control. ISOCH RONOUS__IN DICATION and ARBITRATION errors will be detected by using ISOCHRONOUS_ INDICATION_INVERSE and ARBITRATION_INVERSE (equivalent to odd parity). CLOCIC_INDICATION and SYNC_INDICATION errors will be detected using missing pulse detector logic.
REFERENCES 1
2
Error recovery When errors are detected, it is assumed that appropriate logic will cause a switch over to a back-up bus and/or a back-up card. The details of such algorithms are beyond the scope of the present P1396 effort.
3
4
Signalling during error conditions
5
If a bus is determined to have failed by loss of integrity of the ISOCHRONOUS_INDICATION and ISOCHRO-
6
146
'Network equipment-building system (NEBS), generic equipment requirements' Bell Communications Research Technical Reference TR-EOP-000063, issue 1 (August 1985) 'Network architecture concepts for the 90's -- Intelligent Network/2' Bell Communications Research Technical Requirements and Information Forum (April 1987) 'ISDN, basic access transport' Bell Communications Research Technical Requirements and Information Forum (TRIF), St Louis, MO, USA (July 1987) IEEE896.1 Futurebus, a backplane bus specification for multiprocessor architectures (July 1987) Elderkin, M P1396 contribution, 18 August 1987 ANSI/IEEEStd 802.2-1985, ISO/DIS 8802/2 logical link control IEEE/Wiley, New York, NY, USA
Microprocessors and Microsystems
P1396 is a standards effort to develop a 'hybrid' backplane bus that combines synchronous time division multiplexing for circuit switching with a scheme that allows multiple users to access the bus for the transfer of variable-length packet data. The bus is intended to operate at speeds up to 20 Mbyte s -7 and to be synchronized either to the telephony rate of 8000 frames or to a video frame for image processing applications. The paper introduces the P1396 specification and reviews the standards work that has been done, and that remains to be done, by the IEEE P1396 working group. Applications such as metropolitan area networks and distributed office communications are discussed, as is the functional design of the bus. microsystems P1396
bus standards
distributed systems
networks
The purpose of this paper is to introduce the standards work being done by the P1396 working group of the IEEE Microprocessor Standards Committee (MSC). That group is chartered to define a specification for a combined packet and time-division backplane bus and package for circuit switching, packet switching and multiplexing applications. The bus speed is intended to match that of the new transmission standard for worldwide communications called Synchronous Optical Network (Sonet); as of January 1988, that speed is 51.840 M b i t s -~. Sonet allows multiple signals to be byte interleaved to create higher-rate signals. The Sonet-3 signal (155.520 Mbit s -1) Networksand CommunicationsDivision,NationalSemiconductorCorp., 2900 Semiconductor Drive, PO Box 58090, Santa Clara, CA 95052578090~USA Currentaddress:Ameritech Inc.,Schaumburg,IL, USA Paperrevised:11 January1988
is under consideration by CCITT as an international synchronous transmission signal. (The format of the Sonet signal appears to be under pressure to undergo another revision from 51.84 Mbit s -1 to a speed in the neighbourhood of the Sonet-3 signal, but at the time of writing, no decisions have been reached.) Because some of the primary target applications of P1396 are in Sonet-based communications equipment and, because Sonet is inherently byte oriented~ the P1396 bus is byte wide. To simplify configuration requirements, a bidirectional bus is required (i.e. the clock source can be in any slot). The Sonet-3 speed divided by eight yields a bus speed of 19.44 MHz which is feasible using a 16 inch (40 cm) bus and currently available transceiver technology. The P1396 specification is building upon existing standards wherever possible. For this reason, the IEEE 1101 packaging standard for computer equipment is recommended. Conformance to the Bellcore network equipment building system (NEBS)1 is also required for products that will be used in the public telephone network. A variety of applications are envisaged for the P1396 hybrid communications bus, ranging from multiplexers, remote switching units and digital subscriber carrier modules to private branch exchanges (PBXs). Most communications applications require independent transmit and receive buses. Therefore, P1396 provides multiples of two sub-buses per connector. The original concept embraced by the working group was to use 96-pin DIN connectors as specified in IEEE 1101. However, the requirement to be able to perform live insertion and removal of modules without using any 'precharging' umbilical cable (as is specified in IEEE 896 Futurebus) has caused the selection of a new connector to be the working group's highest-priority work item. Considerable attention is being given to fault tolerance and maintainability. Bus and signal parity lines are used to
01 41-9331/88/031 39-08 $03.00 © 1988 Butterworth & Co. (Publishers) Ltd Vol 12 No 3 April 1988
139
provide error detection. Optional bus redundancy ~s provided by allowing bus duplication. Error recovery and maintainability require live insertion and removal of cards, machine readable part or serial numbers for all modules and comprehensive diagnostics. A card-level maintenance history could be held in write-once memory on each card, eliminating tracking errors that occur when the maintenance database gets out of step with reality. In add-drop multiplexer applications, part of the network bandwidth will be dropped onto the receive bus, the same amount of bandwidth being inserted onto the network from the transmit bus and the remainder being 'through connected'. The added and dropped time slots are tagged as active or 'isochronous' by signal lines called ISOCHRONOUS__INDICATION (and ISOCHRONOUS_ INDICATION_INVERSE). The through connected bandwidth also maps onto the bus as 'not isochronous', i.e. the ISOCHRONOUS__INDICATION signal is unasserted; the bus is essentially idle for those time slots. P1396 provides a means to employ this through connected, idle, unused bandwidth for variable-length packet transmission between cards within the 'crate'. As the instantaneous demand for isochronous (through connected) bandwidth changes by 8, the available packet bandwidth changes by - 8; the packet access method merely skips over all bytes (time slots) presently involved in add-drop circuit switched connections. The packet bandwidth can be used for intermodule control information, or for transport of user packet information between modules. Redundant serial buses (under development by the P1394 committee*) may optionally be employed for offcrate communications or for enhancement of fault tolerance. This is a subject for future study. The system speed may be scaled by using multiple sub-buses or multiple connectors or both.
TOWARDS AN OPEN ARCHITECTURE Major trends: standards and distributed systems The telecommunications industry is moving inexorably towards the integration of digital voice, data and image transmission (and processing) in networks of all sizes, from local to worldwide. In addition, the confluence of industry, technical and regulatory forces including VLSI, fibre optics, standards (such as ISDN, LAN standards and the Open Systems Interconnect model), deregulation of the telecommunications industry and Open Network Architecture continues to increase the economic benefits of distributed systems. The computer industry was the first to experience the impact of 'going distributed'. It is now practical to combine distributed computing and telephony technologies to build truly distributed office communications systems that combine the best features of LANs, voice PBXs, data switches and multiplexers in a single unified system. The traditional centralized star PBX architecture is slowly giving way to a distributed architecture that will be composed of many small 'departmental' switching and processing nodes interconnected with a high-speed fibre optic backbone. *Further information is availablefrom Mike Teener, chairman of the P1394 committee. Telephone(USA):(408) 721-5897
140
Similarly, the switching and trar~mission elements ot the telephone networks are undergoing a transition towards fibre optic networks that will be populated with intelligent multiplexers, cross connects and remote switches combined with distributed computing machines .... an intelligent network with increasing decentralization of both switching and control 2,
P1396: a market-driven need In this context, there is a clear need for an international standard defining a backplane bus and package for the different functional boxes that will be found in the integrated voice-data local, metropolitan and long-haul networks of the 1990s and beyond. The primary goal of the P1396 effort is to do for the communications systems market what VME has done for [he computer-based systems business. Among the beneficiaries of a standard cabinet wilt be the operating telephone companies who will be able to configure application-specific systems from standard modules. Proprietary systems are no longer acceptable to many operating companies because of the high cost of • maintaining inventories of functionally equivalent but noninterchangeable spares • hiring and training maintenance specialists in eacil of the several functionally identical but operationally and physically different proprietary systems • managing and planning networks based an a vadety of similar but needlessly different proprietary modules. Suppliers that have traditionally benefitted from 'account management' through the exploitation of the proprietary nature of their equipment may initially oppose this level of standardization. In the end, however, such an initiative cannot be stopped. Operating companies may eventually be allowed to operate their own systems integration and software organizations, building up their own product solutions for specific markets from standard modules available from a variety of sources. The established manufacturers can resist the inevitable and lose market share, or take an aggressive leadership role and be the dominant OEMs.
Metropolitan networks Figure 1 depicts a possible intelligent optical metropolitan network for the early 1990s, providing such features as • flexible configuration and reconfiguration of bandwidth for the purpose of load levelling of the network traffic • virtual private networks for the customer • local area network (LAN) interconnection with LAN performance. Universal access m o d u l e
Universal access modules (UAMs) interface to Sonet on the network side (providing add-drop services of almost arbitrary data rates onto the P1396 backplane) and to all economically interesting user access protocols on the other -- analogue, ISDN basic and primary access, DS-2, DS-3, Ethernet, 802.5 token ring, FDDI, 802.9 CO-LAN, X.25 and so forth. The cost effectiveness of providing
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POTS or ISDN basic access from a P1396 box is a controversial subject. One point of view is that the box will be more expensive than a conventional subscriber line carrier and will not be viable. Another point of view is that the real cost of ownership of such equipment is dominated by operational costs and not by the initial cost. Reduction of spares inventories, simplification of maintenance personal training, increased flexibility in delivery of services and related economies may offset a higher initial cost. We must assume that cost studies are in progress to clarify this issue. UAMs conform to the NEBS specification 1 and employ the P1396 backplane bus. UAMs are populated with standard modules to perform both functions that are now done with proprietary equipment, and functions that are still 'on the drawing board'. These standard access modules talk to the P1396 backplane bus and provide a second-level add-drop function to deliver circuit switched connections to the active users connected to those cards. In addition, access cards using packet services will employ the packet capabilities of the P1396 bus to transfer variable-length packets between relevant cards - - a user's Ethemet access card and the MAN multimegabit data service backbone interface card, for example. One specific card size suitable for public switching
Vol 12 No 3 April 1988
applications is 3 U × 2 2 0 m m . To employ IEEE 1101 standard packaging, 19 inch (48 cm) racks are recommended. It may be a recommended practice (but not part of the standard) to put power converters and/or cabling in the spaces available between each end of a card cage and the 23 inch (58 cm) telephone equipment rails. An example of a UAM based on these standards is shown in Figure 2. Taking one example application - - the integrated services digital network (ISDN) - - in many areas the demand for ISDN will not justify the replacement of analogue central office switches that are not yet fully depreciated. In such cases, a UAM can be configured as a remote switch attached to a distant ISDN central office. In another application, the UAM could be populated with analogue line cards to do the job of a subscriber line carrier module. The UAM is not limited to analogue lines, however; ISDN lines can also be supported. In this manner, the UAM concept is not inconsistent with Bellcore's universal digital carrier concept 2, 3 ISDN basic access at 144 kbit s-~ will not be sufficient for personal computer users accustomed to LAN performance. A standard central office LAN (CO-LAN) will therefore evolve that operates on twisted pair wiring and offers over 1 Mbit s-1 performance, probably at the ISDN
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primary rate of 1.544 or 2.048 Mbit s-~, (The IEEE802.9 committee is chartered to work on customer equipment, so this application of 802.9 is not 'official', but the need is real and thus presents an opportunity to apply the technology to intelligent networks to help provide 'centrex knock-offs' of so-called fourth-generation PBXs.) IVD/LAN workstation
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in IEEE802.6 (QPSX). However, voice services can already be provided using add-drop technology, so the real unmet need is for high-speed packet data for interconnecting various user LANs and mainframes. For a considerable time, the DS-3 rate of 44.736 Mbit s -1 will be the only ubiquitous offering. A need exists, therefore, for a DS-3 rate backbone for user LANs.) In the late 1990s and beyond, the author expects to see a migration to an all packet network based on the 'new transfer mode' work being done in the T1D1.1 committee. It is a design goal of P1396 to be able to accommodate 'new-transfer-mode, fast-packet, asynchronous time-division multiplexing' or whatever name becomes permanently attached to the service. The above examples are intended to convey the concepts important to this work, and not any particular embodiment or solution. The number of single- and double-high cards chosen for this example is reasonable, but is not a necessary part of the developing specification. One of the specific advantages of the I EEE1101 packaging standard is that a number of vendors make 'erector sets' that can be configured to practically any requirement. Thus a particular UAM could use the building blocks described here, and still be tailored to the requirements of a specific application.
Distributed office communications A fibre optic voice-and-data 'integrated services local network' (ISLN), known as ANSC X3T9.5 FDDI-II, will most likely become a standard within the next 12-18 months. Figure 3 depicts the types of equipment that can be expected to attach to such systems. Given that the ISLN itself will be a standard, as are practically all the access methods to the ISLN (X.25, ISDN, 802 LANs etc.) it is a natural extrapolation to standardize the node backplane and package.
the public network. For example, no depth or card height restrictions exist except those imposed by the constraints of good design and economics. Rear access is generally acceptable, even preferred. Next-generation 'ISLN-PBXs' will provide considerable computing power, and will therefore require a standard computer bus. Figure 4 shows a possible ISLN node configuration. It would be premature to speculate as to whether the cards from the UAM described below will be usable in ISLN office systems, but it would clearly be a most satisfactory situation if standard modules were available for analogue access, ISDN basic access, ISDN primary access, X.25 access, I_AN access etc.
PACKAGING ISSUES I / O considerations Figure 5 depicts the option of having I/O cabling terminate on the fronts of cards. From a maintainability standpoint, this is undesirable, at least in the USA. At least one major European telecommunications vendor successfully uses the '1/O on the front' approach, however. I/O can be put on the rear using small adapter cards that connect onto the back side of the backplane bus as shown in Figure 6. Surface-mount technology is being considered for this.
P 1 3 9 6 BUS FUNCTIONAL DESIGN Transceiver functional characteristics The P1396 bus will employ the same open collector transceiver technology as defined for I EEE896 Futurebus 4.
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Vol 12 No 3 April 1988
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CONTROL__INDICA TION The control indication bit can be viewed as a ninth data bit modifying the meaning of the eight data bits. Control indication will be interpreted in conjunction with isochronous indication. When isochronous indication is unasserted, control indication will determine whether the associated byte is control (asserted) or data (unasserted).
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indication is asserted) or packet switched (when isochronous indication is not asserted). Thus, idle time slots default to packet switched mode. This signal is pipelined one time slot relative to data and control and is sourced by the same card that provides clock and frame synchronization. This implies that cratewide time slot management is a centralized function.
ISOCHRONOUS__INDICA TION_JNVERSE This signal is included solely for error detection. It is effectively an odd-parity indication of ISOCHRONOUS_ SYNC INDICATION. Like isochronous indication, it is pipelined one time slot.
ARBITRATION The arbitration signal is used to control access to the bus for the purpose of packet transfers. The details of the method are described below.
ARBITRA TION__INVERSE As for ISOCH RONOUS_IN DICATION_INVERSE, corruption of the arbitration signal must be detectable instantly to deter multiple masters from erroneously taking control of the bus.
CLOCK__INDICATION The clock indication signal is produced by a master clock source located on a card which, in general, will be redundant. The clock source may be on a card with other functions, such as a network interface, or it may be a single-function card.
SYNC__INDICA T/ON SYNC__INDICATION is also sourced by the master clock module that is providing the timing reference for the entire crate. The signal will normally be high (false) and will be asserted by the source for at least one CLOCK__ INDICATION interval. In Sonet applications, this signal will be asserted for two, four or six clock times to correspond to the two bytes of the frame word for each Sonet synchronous transport signal (STS). The 155.520 Mbit s -1 STS-3 signal for which the P1396 bus is designed will therefore require that SYNC_INDICATION be asserted for six time slots. ISOCHRONOUS__ INDICATION and ISOCHRONOUS__INDICATION__ INVERSE are both ignored duringthe SYNC__INDICATION interval. In telephony applications, this signal will occur at a nominal rate of 8000 Hz.
Isochronous data transfer Conventional time switching will be accomplished by the module which sources data into a time slot for which the corresponding isochronous indication bit is asserted. Allocation of time slots will be accomplished by management entities, the details of which are beyond the scope of the present work. The P1396 working group intends to address this class of issues in a P1396.2 project, which will be aimed at protocols above the physical and media access layers.
Vol 12 No 3 April 1988
Nonisochronous data transfer Packet or nonisochronous or burst-mode traffic will be transported across the backplane bus using all the bandwidth not presently allocated and labelled as isochronous time slots (ISOCHRONOUS_INDICATION = logic 1). In this manner, the P1396 hybrid bus provides variable allocation between the two types of service at a granularity of one time slot or 64 kbit s-1. Of equal importance to granularity is the ability to label individual bytes. This allows maximum flexibility in allocation and deallocation of isochronous bandwidth.
Minimum channel for management signalling Because packet-mode messages may be used for management of all the modules in a crate, it is imperative that there is no possible case where all the time slots can be designated as isochronous. This would result in a deadlocked bus, because no messages could be sent to deallocate the slots. Accordingly, the P1396 protocol will always treat the time slot(s) associated with SYNC_ INDICATION as nonisochronous regardless of the state of the associated ISOCHRONOUS_INDICATION (and inverse) bits. This guarantees a minimum of 64 kbit s -1 packet bandwidth even if the ISOCHRONOUS__ INDICATION (and inverse) bits become stuck in some illegal state. In Sonet applications, six bytes are occupied by frame synchronization information. In these applications, SYNC_INDICATION can be asserted for six clock periods and provide 384kbits -1 for management signalling.
Packet transfer protocol The packet transfer protocol consists of three phases: the access or arbitration phase, the data transfer phase and the acknowledgement phase.
Access or arbitration phase Slotted serial arbitration has been proposed 5. Arbitration slots of approximately 9 bit are defined. Intent to arbitrate is signalled by assertingthe first bit in a slot; then the 5-bit arbitration address is driven onto the line, least significant bit first. Any module that sent a logic 0 (unasserted) and saw a logic I (asserted) has lost the arbitration and retires from the process. After five bits, the winner continues to assert ARBITRATION until capturing the bus. The master elect monitors the bus for an idle state (data, control and isochronous bits all unasserted) for two slot times. Upon seeing the idle state, the master elect captures the bus by first sending a START__ DELIMITER followed by the rest of the packet, and then releasingARBITRATION to allow the next arbitration to occur. Priority and fairness are provided by assigning priority to all even arbitration slots, and fairness to all odd arbitration slots. In priority mode, the highest numbered competitor wins the bus; in fairness mode, a winner cannot arbitrate again until all other contenders have had use of the bus.
Transfer phase Once the master elect has become the master, a variablelength packet is transferred using a format that is based on the IEEE 802.2 logical link control (LCC) packet data unit
145
(PDU) format 6. Media access control protocol constructs are used to delineate the start and end of packets. The acknowledgement phase borrows the 'addressed-copied' concept from the 802.5 and FDDI token rings. The variable-length acknowledgement concept is borrowed from the work being done in the P1394 serial bus committee. The 'null' control character is suggested to handle underrun situations where the transmission of a packet is interrupted because the transmitting processor or DMA logic failed to keep up with the demands of the bus. If nulls are sent, the packet can be sent without error in spite of the underrun. This prevents a heavily loaded bus from experiencing a further increase in demand to handle rejected packets.
Acknowledgement phase
NOUS_INDICATION__INVERSE lines, arbitration will proceed in the normal manner and the only valid time slots for packet data will be those time slots which coincide with SYNC__INDICATION. Depending on the system application, this may be from one to six slot times.
Maintainability Live insertion and removal of modules All equipment built to the P1396 standards will support live insertion and removal of modules without interruption of service, The suitability of the DIN connector specified in IEEE 1101 is in doubt for this requirement. Other IEEE1101-compatible connectors are being studiedl
A variable-length packet format is proposed for use in the acknowledgement phase. This would allow a slave module to return an arbitrary-length packet of information without arbitrating for the bus. The construct will allow a master to poll a collection of slaves and get responses without requiring the slaves to arbitrate. An alternative view is that the master could read a register or block from the slave. This concept affords considerable flexibility by supporting the following.
Module identification
• Single-master polling: a single master polls slave cards. • Multimaster polling: two or more bus masters contend for the bus and then poll the slave cards. The population of slave cards could be shared among the masters or specific slaves could be allocated to their own 'master'. A second master could be used for redundancy. • Multiple access: the bus functions as an intracrate LAN. The acknowledgement phase is limited to 'addressedcopied' single-byte transfers. • Dumb slave boards can be controlled by read and write operations; thus there is no requirement for all boards to be 'smart'. • Intelligent boards can use multiple access for normal operations and read/write operations for board-level diagnostics.
Maintenance history
Each pluggable module will provide, as a minimum, a machine readable part number. Machine readable serial numbers, hardware revision levels, firmware revision levels, software applicability codes and other productspecific information can be supported based on this part number. These data may be accessed using the read operation described earlier. Thus even dumb cards can support this function.
Depending upon user and manufacturer preferences, each module may provide sufficient write-once memory to accommodate the entire service history of that module. The format for this data is beyond the scope of the present effort.
CONCLUSIONS At this stage of the P1396 committee work, there are many more questions than conclusions. It seems clear that P1396 is addressing a genuine market need and that timely completion of the standard will benefit the industry. The committee intends to have a draft standard ready for initial working group ballot by July 1988.
Error detection Parity will be used to detect errors on data and control. ISOCH RONOUS__IN DICATION and ARBITRATION errors will be detected by using ISOCHRONOUS_ INDICATION_INVERSE and ARBITRATION_INVERSE (equivalent to odd parity). CLOCIC_INDICATION and SYNC_INDICATION errors will be detected using missing pulse detector logic.
REFERENCES 1
2
Error recovery When errors are detected, it is assumed that appropriate logic will cause a switch over to a back-up bus and/or a back-up card. The details of such algorithms are beyond the scope of the present P1396 effort.
3
4
Signalling during error conditions
5
If a bus is determined to have failed by loss of integrity of the ISOCHRONOUS_INDICATION and ISOCHRO-
6
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'Network equipment-building system (NEBS), generic equipment requirements' Bell Communications Research Technical Reference TR-EOP-000063, issue 1 (August 1985) 'Network architecture concepts for the 90's -- Intelligent Network/2' Bell Communications Research Technical Requirements and Information Forum (April 1987) 'ISDN, basic access transport' Bell Communications Research Technical Requirements and Information Forum (TRIF), St Louis, MO, USA (July 1987) IEEE896.1 Futurebus, a backplane bus specification for multiprocessor architectures (July 1987) Elderkin, M P1396 contribution, 18 August 1987 ANSI/IEEEStd 802.2-1985, ISO/DIS 8802/2 logical link control IEEE/Wiley, New York, NY, USA
Microprocessors and Microsystems