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Standard bus for 8-bit microprocessor systems
Standard bus for 8-bit microprocessor systems Despite the recent flood of 1 6-bit microprocessors and microcomputers most applications areas can be adequately served by 8-bit systems. Tim Elsmore describes the STD bus, which has now become a standard in the US, and the recently proposed Eurocard version A large application area o f microprocessor systems, where low cost is essential and relatively low throughout can be tolerated, is serviced by simple 8-bit systems. Examples o f such applications are industrial process control, program development systems and intelligent instrumentation. A bus definition which adequately covers the requirements o f this application area is currently being investigated for standardization by the IEEE Computer Society's P961 working group, and is known to the industry as the STD bus. There are already a number of 8-bit schemes in use, particularly in Europe, but most do not have the potential for use as a standard as they are defined in such as way that they are specific to one family of CPU only. The STD bus will support any 8-bit CPU and has already evolved as a de facto standard for small card systems in the US, being supported by around 60 manufacturers to date. Its popularity in Europe is restricted only by its nonconformance with IEC mechanical specifications (Eurocard) and its use o f direct edge connectors rather than the more reliable DIN 41612 connector. However a recent move to provide a European format STD bus had been made and is highlighted later in this paper microsystems
standards bus
STD
to use the bus. Mid-1979 saw the formation of the STD Manufacturers Group [STDMG), whose charter it is to maintain order, resolve unforseen problems and recommend standard practice on methods such as priority interrupt and bus priority. The STDMG have also set up working groups to provide specified practices for implementation of various 8-bit microprocessors on the bus, investigation of a CMOS interface, backplane practice and memory extension techniques. In May 1981 the IEEE Microprocessor Standards Committee IMSC) was again approached and in September 1981 a working group were allocated the project authorization number P961. Later in 1981 an STD bus users group was formed. April 1982 saw the first European manufacturers group meeting, held in Paris at which the European requirement for an STD bus based on the DIN 41612 Eurocard connector was discussed. A formal proposal for a DIN connector STD bus was made at the P961 group's regular meeting in conjunction with the Electro exhibition at Boston May 19822 . In August 1982 the MSC decided to start a working group tasked with developing a bus proposal derived from the STD bus and implemented on a Eurocard with a DIN connector.
bus FUNCTIONAL
BACKGROUND
As implied by its name, the STD busI evolved from beginnings where its potential as a standard was recognized. It started in 1973 when a 4.5 in by 6.5 in card size was selected by Pro-Log to package a variety of microprocessor systems [see Figure I ). The intention was to select a card size that allowed modular convenience to simplify design. Early bus definitions for interconnection of Pro-Log's cards fell foul of the temptation to mix system I/O lines with the processor bus on the backplane. But in 1976 ProLog redefined its bus, separating the I/O interface from the processor bus. The new definition dedicated the backplane to the processor bus and made use of the opposite card edge to provide I/O interface via often familiar connectors. In 1978 Mostek joined Pro-Log and a short time later the final details of the bus specification were complete. The STD bus was announced at Wescon of that year. To realize the potential of industry standardization, it was agreed that neither Pro-Log nor Mostek would register the concept by trademark or copyright. Early contacts were made with the IEEE standards groups. These efforts never gained momentum and it was decided that if the STD bus were to become a standard it would have to be accepted on its own merits. So other manufacturers were encouraged GMT Electronic Systems Ltd, Newport House, 22 Hartfield Road, Wimbledon, London SW19 3TD, UK
vol 6 no 9 november 1982
PARTITIONING
The design principle that has become dominant in 8-bit board level systems is that of system partitioning by function i.e., CPU on one card, a portion of memory on another, specific I/O functions on others, etc. This has partic01ar value in applications were cost is a key factor as it allows a highly modular approach using small cards. The advantages over larger, Multibus or VERSAbus type cards, are
Figure I. STD bus in its original 5.4 x 6.5 in card size
0141-9331/82/090455-I I $03.00 © 1982 Butterworth & Co [Publishers) Ltd
455
• • • • • •
closer tailoring of hardware to the final requirement due to minimal hardware redundancy on eai~h card higher degree of reliability due to lower component count and the rigidity of small cards higher degree of flexibility in system mechanical design conceptual simplicity for the system designer simpler procedures for testing, fault finding and maintenance the small card sizes allow advances in LSI to be optimally used by means of a gradually evolving increase in functionality per card
The greater number of connectors required in a given system can be considered a disadvantage as there is a tendency towards reduced reliability, especially in the case of direct edge connectors.
WHY STANDARDIZE? At this functional level of partitioning, it is clearly necessary that many functions are provided to enable close hardware tailoring. A single company would have difficulty in identifying every requirement and still more in providing functions to satisfy every requirement. It is therefore desirable that many manufacturers provide wholly compatible functions while maintaining the specialization in their own application area (e.g. high precision analogue). Definition of standard interconnection schemes removes the need for companies to split resources or diversify and provides a means for small or specialist companies to support one another by contributing compatible functions. This ensures that system designers have access to a wide range of functions and are not confined to a single source.
Wide acceptance and use of a standard justifies the development costs of custom LSI design at the bus interface. This would naturally increase the real estate available for functions on a card allowing for denser and thus more economic system packaging, though this is considered unnecessary in the case of STD bus due to the simplicity of interface circuits required.
CONTROL STD bus is a synchronous nonmultiplexed backplane bus providing control for the transfer of data over an 8-bit wide parallel path. Although primary provision is for the addressing of 64 kbyte of memory, additional address space may be realized by use of the MEMEX signal extra address space. Table 1 details the pin out and signal mnemonic functions. STD bus can be conceptually illustrated as in Figure 2 as four separate buses. The 22-line control bus is carefully defined to achieve a significant degree of CPU independence with minimal modification of the component level bus in its translation to the backplane bus. This reduction in complexity of the bus interface logic compared to, say, Multibus or VME, allows an attractive level of system partitioning on the small card size defined by the STD bus mechanical specification. Direction of data movement on the bus is controlled by separate read [RD*) and write IWR*)~- signals. The RD* and WR* signals are also used to gate data on and off the bus. This technique is familiar to users of Intel processors tThe trailing asterisk (*) denotes an active-low signal.
Table 1. STD bus pinouts with signal flow referenced to the processor card Component side Pin Logic power bus
1 3 5
Circuit side
Mnemonic
Signal flow
Description
+5 V DC GND VBB#1
In In In
Logic power (bussed) Logic ground (bussed) Logic bias#l (-5 V)
Pin 2 4 6
Mnemonic
Signal flow
Description
+5 V DC GND VBB#2
In In In
Logic power (bussed) Logic ground (bussed) Logic bias#2(-5 V)
Databus
7 9 11 13
D3 D2 D1 DO
In/out In/out In/out In/out
Low order databus Low order databus Low order databus Low order databus
8 10 12 14
D7 D6 D5 D4
In/out In/out In/out In/out
Highorder databus Highorder databus Highorder databus Highorder databus
Address bus
15 17 19 21 23 25 27 29
A7 A6 A5 A4 A3 A2 A1 A0
Out Out Out Out Out Out Out Out
Low Low Low Low Low Low Low Low
16 18 20 22 24 26 28 30
A15 A14 A13 A12 A11 A10 A9 A8
Out Out Out Out Out Out Out Out
High order addressbus High order address bus High order address bus High order address bus High order address bus High order address bus High order address bus High order address bus
Control
31 33 35 37 39 41 43 45 47 49
Out Out In/out Out Out Out In Out Out Out
Write to memory or I/O I/O addressselect I/O expansion Refresh timing CPU status
51
WR* IORQ* IOEXP REFRESH* STATUSI * BUSAK* INTAK* WAITRQ* SYSRESET* CLOCK* PCO
Interrupt acknowledge Wait request System reset Clock from processor Priority chain out
32 34 36 38 40 42 44 46 48 50 52
RD* MEMRQ* MEMEX MCSTNC* STATUS0* BUSRQ* INTRQ* NMIRQ* PBRESET* CNTRL* PCI '
Out Out In/out Out Out In In In In In In
53 55
AUX GND AUX + V
In In
AUX ground (bussed) AUX positive (+12 V DC)
54 56
AUXGND AUX-V
In In
bus
Auxiliary power bus
456
Out
order address bus order address bus order address bus order address bus order address bus order address bus order address bus order address bus
Bus acknowledge
Read memory or I/O Memory address select Memoryexpansion
CPU machine cycle sync. CPU status Bus request Interrupt request Nonmaskable interrupt Push button reset
AUX timing Priority chain in AUX ground (bussed) AUX negative (-12 V DC)
microprocessors and microsystems
User’s
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interface
Motor
Soknoid
Digital
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Input ports output ports
8085 280 6800 Other
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l/O
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Industrial
UART control CRT Other
Optolnput triac relay drivers
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Figure 2. STD bus implementation and the 280, but is inherently less flexible than the method of data transfer control associated with the 6800-type processors which use a logical read/write (R/W*) signal to control data direction and a separate synchronization strobe signal (E). In this method the R/W signal precedes the synchronization strobe in the time domain allowing for a period of data set up time. This is useful for turning around bidirectional bus transceivers, for example. The separate RD* and WR* strobe technique has, however, the advantage of requiring less interface logic for most CPUs and is commonly used with bytewide memory.
6500 family peripheral circuit such as the 6821 peripheral inteface adaptor. These circuits require a presynchronization read/write signal as described above. STD bus makes provision for this and other processor status signals that are specific to one CPU by, means of four peripheral timing control lines. These four lines are separately defined for each CPU type to provide for specific timing requirements as shown, for example, in Table 2; it is in this way that the STD bus achieves CPU independence. So, although, all memory functions and simple input and output functions can be
, STD
Processortype independence The attributes are
in which CPU independence
is fundamental
applications which can implement the CPU whose architecture and instruction set offer the most relevant facilities system designs which can be upgraded late in their development without major hardware redesign different CPU families which can be used within the same system allowing optimum use of existing LSI devices STD bus displays of all these attributes but the latter, only with careful design. Any g-bit CPU type can control data transfers over the bus by means of read (RD*), write (WR*), memory request (MEMRQ*) and I/O request (lORQ*) signals, all of which can easily be derived from that CPUs component level bus. Figure 3 illustrates the 6809 as an example. A complication occurs when data is written to a 6800/
vol6
no 9 november 1982
Date
bus
DO- D7
ADDfi
AO-A15
IORQ*
6809 CPU
WR%
Rllnr
RD*
E 0
B& control Figure 3. Interfacing a 6809 to the STD bus
457
solution, and although STD bus is not truly processorindependent, it offers an attractive compromise on the two major alternatives which are either truly CPU independent systems using large cards with sophisticated interface logic or cheaper small card systems which simply extend the CPU bus signals on to the backplane. The former are prohibitively expensive in the application area under discussion and the latter offer no potential for CPU independence.
Table 2. Peripheral timing control lines for various 8-bit microprocessors 8-bit microprocessor
8080 8085 NCS800 8088 Z80 6800 6809 6809E 6502
REFRESH*
MCSYNC*
Pin 37
Pin 38
REFRESH*
SYNC* ALE* ALE* ALE* (RD*+WR*+INTAK*) ,
REFRESH*
STATUS1*
EOUT*(02*) EOUT*(D2*) 02* STATUS 0*
Pin 39
Pin 40
MI* S1" SI* DT/R* MI* VMA*
SO* SO* SSO* R/W* R/W* R/W* R/W*
--
8080 8085 NCS800 8088 Z80 6800 6809 6809E 6502
--
LIC* SYNC*
M i x i n 0 generic C P U families Any attempt to overcome the inherent incompatibilities between CPU families (to interface a Z80 CPU to a 6821 PIA, for example) necessarily results in an increase in the complexity of the bus interface. A variety of techniques can be used to overcome such compatibility problems, the particular method used depending upon the CPU families being mixed. The resulting cost factors and performance degradation (due to the introduction of wait states or clock stretching) must be considered and justified. Some CPU families interrelate more easily than others (6800 and 6500 for example) and others can be interrelated by simple decoding of the CPU status lines provided by STD bus (as in the case of the 8085 CPU controlling 6800 family peripheral circuits - see Figure 4). The most logical approaches for designers wishing to mix CPU fa'milies on STD bus are either to restrict themselves to a uniprocessor architecture and allow the processor's component level signals to dominate the backplane bus or to use a permanent bus master/intelligent slave class of multiprocessing architecture where each slave is entirely, but possibly uniquely, restricted to one particular CPU family.
designed to be compatible with any CPU cards, some interface cards using LSI peripheral chips will be incompatible with certain CPU cards. This method of achieving CPU independence requires that any attempt at providing a rigid standard must separate out universal elements such as memory and I/O timing to a core specification. Separate specifications must also be defined for each CPU type, detailing timing for specific hardware signals, interrupt and DMA protocols, etc. CPU independence is of paramount importance in a bus specification which is aimed at providing a universal
B u f f e r e d drive STD bus specification defines a set of signals which must mean something to the cards on the bus. For most CPU STD bus
A8 - A5
[O/M A7 ADO-AD7
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A7 - A3
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A2 - AO
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D7 I bus 8 DO
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8
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8085 CPU card
68XX / 65XX family interface CAI
Figure 4. 8085 interface to 65xx/ 68xx periphera/ circuits via STD bus
458
microprocessors and microsystems
cards, the required interface is an expansion of the CPU level bus and is extended on to the backplane via bus buffers. The definition of the STD bus signals allows a minimal modification of the CPU bus, which is a necessary feature. This is because only limited time is available for transition delays through the interface logic. The simplicity of interface is a considerable cost saver for systems operating with a relatively low cycle time [around 1 MHz), but introduction of wait states and clock stretching techniques is necessary for higher clock speeds, thus increasing the interface complexity and the cost. As the system clock frequency is increased, the time available for address decoding and buffer transition is reduced. This is illustrated for the case of the 6800 generic family in Table 3. Note that the 2 MHz [B series) family is allowed no extra time at all for buffer transition delay in write cycles. Throughput cannot be continually increased by turning up the system clock, as there is a maximum frequency which is determined by current technology component transition speeds and by transmission line effects on the backplane. Designers seeking greater throughput and computing power must graduate to more powerful solutions provided by more sophisticated buses.
Memory extension The potential for extending the bus' addressing capability beyond 64k is provided by the memory extension {MEMEX) signal. MEMEX can be used in a number of different ways. Three examples are: • to expand the address space to 128k • to distinguish between local and global memory resources - allowing a 64k global resource, to be shared by all resident processors and a 64k local resource, a portion of which can be allocated to each processor • to disable primary memory for bootstrap operations [phantom memory) The STDMG has formed a working group to study these methods and others. MEMEX is commonly provided via an I/O port resident on the master CPU card. A method of memory expansion which has been proposed is to extend this idea to having each of the eight lines of an I/O port define a separate 64k memory plane. This method is clearly expensive in both administrative software and in hardware as every memory card must decode an I/O port. Techniques of this sort attempt to stretch the resources of STD bus beyond their limits and indicate a need to seriously consider more sophisticated bus structures and wider path processors with a greater addressing capability for such applications. One of the most common criticisms of STD bus is that
Table 3.6800 generic bus buffer/decode time provision Clock
Available address
frequency
buffer/decoder
CPU
(MHz)
Time (ns)
Available data buffer time (ns) Read Write
6809
1
150
80
365
68A09
1.5
80
30
230
68B09
2
60
30
160
6802
1
100
60
60
68A02
1.5
40
20
30
68B02
2
10
15
0
its addressing capability is limited, though the 128k provided is a generous allocation for most 8-bit applications. However, some of the more recent applications of the bus, such as the multitask multiuser development system marketed by Yrel of France, indicate that greater resources are required. Designers of these sort of applications, which require the addressing capability of 16-bit microprocessors, do not find that the highly sophisticated bus structures such as VME and P896 or the less modular approach of Multibus-type cards provide tangible solutions. There is thus a clear requirement for a simple STD-type bus structure that can provide these resources.
Input/output The design philosophy of STD bus cards, illustrated in Figure 5, favours the implementation of I/O-intensive systems wherein each I/O function is specific to one card, allowing both conceptual and electrical isolation of nonrelated signals. This is particularly useful in an industrial control situation where high voltage outputs and sensitive inputs may be isolated either by relays or opto devices and can be kept physically separate within the same system. The positioning of an I/O connector at the user interface edge of the card allows an orderly signal flow across the card, separating the I/O function from the bus interface logic. The bus provides an I/O request [IORQ*) signal to differentiate between I/O transfers and memory transfers on the bus. IORO* identifies I/O transfers which, using RD* and WR* strobes, are otherwise identical to memory transfers. In this way both separate I/O plane and memorymapped I/O techniques can be implemented. In the case of the latter, IORQ* can be decoded from the upper address lines on the CPU card. The separate I/O plane defines 256 addresses, allowing a total of 256 input ports (using RD*) and 256 output [using WR.*). This may seem a restricted allocation for I/O intensive systems but is enhanced by the provision of an I/O expansion signal (IOEXP) which allows the primary plane of I/O to be disabled, thus, doubling the facility. Current trends in the design of LSI peripheral devices indicate a more efficient use of address space; a device will typically use two addresses, a control port and a data port - the control port being used as a pointer to internal registers. An example is the Advanced Micro Devices AMD9513 system timing controller, wttich uses just two port addresses to control five 16-bit counters. This represents a considerable saving in address space compared to, say, a Motorola MC6840 programmable timer module which requires eight addresses to control three 16-bit counters.
i !
Bus interface logic
IlO
function logic
: eg: Data latches parallel ports shift registers UARTS AID - D/A
I/O interface
eg : Optoiso level translators line drivers voltage amplifiers
Si~Inalflow
m
Figure 5. STD bus I / 0 card arrangement
vol 6 no 9 november 1982
459
Interrupt and bus priority
tents of an 8-bit 'interrupt vector page' register into the most significant half. The address formed by the 8-bit vector and the page ~egister points to the first of two consecutive memory locations which contain the start address of the specific interrupt service routine relating to that vector. Processors without single-byte vector capability, but providing an interrupt acknowledge signal, can use the scheme illustrated in Figure 7, where INTAK* is asserted while the CPU does two memory read cycles. The CPU address bus addresses the internally-defined vector locations but, by disabling the databus drivers on the memory cards containing those vectors, the system can use INTAK* to force a two byte vector onto the databus from the priority encoder card. Figure 8 illustrates a serial priority interrupt scheme using the PCI and PCO daisychain. Priority is assigned to an interrupting card by virtue of its position on the backplane. The card nearest to the processor card has the highest priority. When a request is made by a card pulling INTRQ* low, the PCO output from that card is also pulled low, this inhibits lesser priority cards from responding to INTAK*. On response to INTRQ*, the processor completes its instruction, stores its status and asserts INTAK*. Cards not involved in the arbitration scheme simply connect PCI to PCO maintaining the daisychain. When the interrupting card recognizes INTAK*, it responds by placing its vector on the databus as described for the parallel scheme. The vectors in this scheme are usually hardwired or switchselected inputs to an octal tristate buffer. The serial priority scheme is simple to implement and required very few bus lines. However it has a number of disadvantages:
STD bus provides signalling for both interrupt and bus requests. Using INTRQ*, conventional interrupt structures can be used, such as that in the 6800, where the processor recognizes the interrupt at the end of the current instruction, provided it is not masked. It then continues with an interrupt service routine whose address is determined by the programmer and inserted in an internally-defined vector location. If more than one interrupting device can assert the INTRQ* line in a given system, then the interrupt service routine can poll the possible interrupt sources to identify the specific interrupt and can then jump to the relevant service routine. This scheme is practical only for just a few interrupts as the polling overheads can become prohibitive. STD bus provides an interrupt acknowledge signal (INTAK*) enabling those CPUs capable of producing such a signal to use vectored schemes to give fast response to interrupts. Arbitration of priority-vectored interrupts on the bus can be achieved either in parallel fashion or by using the serial daisychain formed by PCI and PCO. In the parallel priority example, shown in Figure 6, the interrupts are collected on a separate card (connected via the user interface) which assigns priority using an encoder. The output of the priority encoder drives a vector generator circuit, typically a PROM, which places an 8-bit vector address on the data bus. The processor loads this vector into the least significant half of the program counter and, typically, loads the con-
=rocesso ~T Inta!~
# ~
JlPrior
Interrupts
• it is inherently slow because of the number of levels the daisychain signal must pass through • the number of requests it can handle is limited by transition delays through the arbitration logic • it requires a dedicated backplane • it is position sensitive
{ ~ |,ntrq# JvL..J
Dotabus
This rather spoils the position-independent aspect of the STD bus, and, in some circumstances, priority assignment by card position is incompatible with requirements for mechanical proximity to external connectors or with thermal spreading considerations.
Figure 6. Parallel vectored interrupt scheme
STD bus
/ 8
DO- D7
Vector generator PROM
DO- D7
CPU
O
IO
I/O
MEM
RQ*
To
I/O
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r D
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cords
INT
Interrupt controller
Figure Z Forcing the databus
460
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INTRQ-XPCI
o
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PCI
O
O
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.y
Vector J
Vector J
Interrupt
Interrupt
Arbitration logic
Arbitration logic
Figure 8. Serial priority interrupt schemes
Bus control arbitration Transfer of the.bus control for DMA or multiprocessing is achieved via a two-wire handshake using the bus request [BUSRQ*) and the bus acknowledge (BUSAK*) signals. The protocol of the handshake is dependent upon the particular CPU in use. Handover between different CPU types may not necessarily be possible due to protocol incompatibilities. Generally, though, these signals should be purely asynchronous and a requesting controller, having succeeded arbitration, should receive a BUSAK* at some unspecified time later. The daisychain can be used in an identical fashion to that described above to arbitrate between multiple masters requesting the bus for DMA or multiprocessing purposes. Again such schemes are limited by propogation delays. Clearly, if the daisychain is used for bus control arbitration, it cannot also be used for interrupt arbitration, In such circumstances only polled interrupt schemes are possible and all interrupts must be handled by one processor. This restricts the bus' usefulness to only one class of multiprocessing architectures, i.e. those requiring the use of a centralized master.
ELECTRICAL INTERFACE The technology specified for the STD bus interface is low power Schottky TTL, though moves are afoot to define a CMOS interface for the bus. This is a logical progression and should present no significant difficulty as some of the latest technology CMOS devices outperform TTL LS logic in terms of both driving capability and speed. A number of semiconductor manufacturers have, indeed, introduced ranges of pin-compatible CMOS devices, notably memory and octal bus interface circuits. The bus uses three-state rather than open collector drivers. The inherent advantage of design simplicity outweighing the superior driving performance of open collector devices [used in a properly terminated system), which is not required for the relatively low transfer rates associated with STD bus. The major disadvantage of three-state drivers is that very high currents can flow in bus-contention situations and permanent damage can occur. To avoid this, system designers must study carefully manufacturer's timing information when interfacing cards on the bus.
vol 6 no 9 november 1982
It is desirable to terminate backplane traces whenever an application requires a backplane of more than a few inches Iong.STD bus, unfortunately, does not define either backplane parameters or termination techniques, though a subgroup of the STDMG is currently studying this. Generally a simple Thevenin equivalent type of termination, such as that shown in Figure 9a, will suffice. The value of the parallel combination of the two resistors should be approximately equal to the unloaded characteristic impedence of the backplate trace, though the limited transfer rates associated with STD bus (2 MHz) allow a wide tolerance in termination. The termination network shown in Figure 9b provides a matched line for high frequencies without imposing a DC load on supplies and driver outputs. STD bus allows up to five regulated power supplies with two separate ground returns, and provides isolation of analogue and logic supplies. The supplies are +5 V logic supply; -5 V low current substrate bias supply - rarely used these days; and -+12 V auxiliary supplies, for RS232C or analogue circuits. The 5 V logic supply and return are provided via bus edge connector pins 1,2 and 3,4 respectively. This has the disadvantage that all signals must return via two connector positions at one end of the connector. This means that some of the signals on the connector are as much as 3 in distant from their nearest ground return. This distance tends to cause a degradation in the transition time of a signal and to cause reflection noise on the line. Neither of these, though, are significant problems as long as the time required for a signal to propogate the full length of the backplane; and back is considerably less than the system clock period. This is normally the case for STD bus. A more insidious problem is that of shock current caused by the data lines or the address lines simultaneously changing state from all 0s to all ls. This current has to be .
Tov
Signal line ooo
I Signal line
a Thevenin equivalent
b
High frequency termination
Figure 9. Termination of STD bus backplanes
461
absorbed by the backplane ground via pins 3 and 4 which provide ground returns for all other signals. It is possible for the shock current to cause a spike on the ground line large enough to transgress into the transition region of the receivers. Beyond defining the logic levels on the bus, the specification does not detail the electrical interface to the bus in terms of capacitive loads, DC loads, or maximum currents at which the TTL levels specified must be guaranteed true, or hysteresis. This could result in card manufacturers making use of a variety of drivers and receivers displaying inherent incompatibilities when required to operate close to their speed and power limits. A gold-plated direct edge connector is specified for interconnection to the backplane. Still very popular in the US it is unfortunately difficult to obtain in Europe, due to the dominance of the more reliable DIN 41612 connector. It is also becoming a relatively expensive option due to the increasing cost of gold. The direct edge connector is less reliable because of the low insertion life of the soft gold contacts, its vulnerability to dirty environments and the susceptability of its mating connector to mechanical resonance. It also imposes a restriction on the number of connections available at a card edge. One company which manufactures computer control systems for space flight equipment develop their systems using standard STD bus cards, which are then redesigned with a direct edge connector, military specification components and a more rigid card for actual spaceflight modules.
surface area and linear dimensions. Useful attributes, for example, are that two 40-pin DIL circuits can be positioned end-to-end across the width of the card and that eight 14-, 16-, 18- or 20-pin DIL circuits can be positioned side-byside across the width of the card. In Europe, the lack of conformance in the more common Eurocard outline, though, results in a lack of choice for the designer in packaging his systems and inevitably this makes packaging more costly as it may often have to be custom built. For this reason, a proposal has been made to the I EEE P961 committee to consider an alternative mechanical format.for the STD bus specification, to be provided alongside the original format. It should be stressed that this is only a proposal. One of the many attributes of the recently proposed European format STD bus 3 is that a variety of card sizes may be used (Figure 11 ), all of which are totally supported by packaging, racking and backplanes defined by International Electrotechnical Committee spec 2974.
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MECHAN ICAL $PECl FICATION Figure 10 details the mechanical requirements of the STD bus specification. The inherent advantages of this small card size, as discussed earlier, are marred, in respect of European usage, only by its nonconformance with common mechanical standards. It is in fact an extremely useful size for the type of system partitioning inherent to STD bus, both in terms of
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462
microprocessors and microsystems
EUROCARD STD BUS The Eurocard concept comprises a family of compatible boards in various sizes, ranging from single to quad height modules with optional length extensions. Figure 12 compares the outlines of the single Eurocard and an STD bus card. The modular nature of the Eurocard family complements that of the STD bus and though most manufacturers prefer single and double height Eurocards at the moment {see Figure 13) the horizontally extended versions offer a considerable real estate increase, allowing much greater functionality without the requirement for a taller rack {Figure 14), in which to house the system. Indeed, manufacturers of CMOS based systems have found it necessary to use extended Eurocards due to the lack of CMOS LSI peripheral circuits such as serial interface adaptors and programmable timer circuits. An extended {220 ram) single Eurocard gives 17 per cent more surface area than a standard STD bus card. Use of multiheight Eurocards also offers some interesting system design alternatives. Due to the identical connectors on each unit of the multiheight Eurocard, multiple bus structures can be implemented in order to increase throughput, or indeed, fault tolerant designs can be implemented using dual redundant buses. A further possibility is to implement all I/O interface on physically separate connectors on the same edge of the card as the backplane. This is particularly useful to industrial users who often prefer to STD 6.5in (165.1mm)
vI _1
Eurocord 6.3 in (160mm)
r i
D B m
i
I i
o o
E
m
m
c~ c_ o')
L~
m
0 I-W .__L
Figure 12. Comparison of single Eurocard and STD card size
Figure 14. STD Eurocard bus rack locate I/O at the back of a unit reducing the possibility of misconnection during maintenance. Table 4 illustrates the pinout, signal mnemonic and flow with respect to the processor card. The logical structure of the STD bus has been r.etained in its transfer to the DIN 4161:2 connector. The only changes are a modification of the power supply pinout, rejection of the -5 V substrate bias supply, inclusion of the two 0 V signal returns and the adoption of an enhanced interrupt structure including an additional arbitration daisychain. This can be used either to provide a way out/way back arbitration scheme, in conjunction with the existing daisychain, allowing a greater flexibility in positioning of modules or can be used for multiple processor arbitration. The single Eurocard is nominally 160 m m x 100 mm and makes use of a multipin two-part connector using a maximum of 96 pins organized in three rows of 32. The pins are situated on 0.1 in {2.54 mm) pitches. The surface area of this card is about 15 per cent less than that of an STD bus card. Most commonly used in microprocessor applications are the outside two rows of pins, rows a and c. The third row, row b, is often used to provide 0 V guard tracks on the backplane. In topographical terms row c is equivalent to the component side of and edge connector and row a to the noncomponent side. A direct topographical transfer of the STD bus edge connector positions to DIN 41612 rows a and c would result in the nonuse of eight pins {a29-a32, c29-c32) on the DIN connector. I he proposed Eurocard STD bus capitalizes on these extra pins to improve on many of the deficiencies of the STD bus, which were highlighted earlier, by expanding existing STD bus facilities while maintaining the structure and philosophy of the bus.
Power supply and signal ground distribution
Figure 13. STD bus in Eurocard format
vo/ 6 no 9 november 1982
The advantages of relocating the power supply grounds at both ends of the connector and locating two signal ground returns around the address bus are numerous. The actual ground return currents see a very low impedence. This is especially so if ground gridding has been used in the PCB design, as it can be carried through to the backplane. The shock currents caused by simultaneous switching of the address or databus lines are returned to ground locally so that they do not interfere with adjacent signal lines. The maximum distance of a signal from its nearest
463
ground return is reduced from 3 in to 0.7 in and the two signal return grounds, at connector positions c7 and a15, double as 0 V guard tracks, minimizing crosstalk by reducing capacitive coupling between the address, data and control buses. The last pin to be disconnected when a PCB is removed is always a 0 V pin. This point is a useful safeguard as it is quite feasible that nontechnical personnel may be used for first level servicing of board level systems, which, of course, increases the risk of a board being removed while supplies are still switched on. The -5 V substrate bias supply (Vbb #1 and Vbb #2) has become virtually obsolete and in rare cases where it is required it can be very easily generated locally/using Texas Instruments TL 497, or Intersil ICL7660, for example). So, rather than waste two valuable connector pins, these have been removed. Interestingly, there is pressure within the STDMG to redefine these two connector positions, possibly as an additional priority chain or as + 15 V supplies on the STD bus proper. Enhanced interrupt structure
A third interrupt request line has been introduced in order to allow a much more full implementation of recently introduced CPUs, such as the 6809 with fast interrupt request or the NSC800 with its five interrupt lines. In order to maintain the philosophy of CPU-independence the interrupt functions have been renamed in a manner indicative of priority - I N T R Q I * , I N T R 0 2 * and INTRQ3*. The choice of level at which the processor is interrupted is made at the interrupting card. A further enhancement of the original bus definition is the addition of the auxiliary priority chain (AC1 and AC0). This effectively reduces stress on the interrupt structure of the bus by ensuring that use of a serial priority system of bus control does not preclude the use of a serial interrupt arbitration system, or vice versa.
16-bit growth path Although STD bus was designed to cope with 8-bit transfers only, increasing pressure to make use of the more popular 16-bit processors has led to the definition of an implementation of the 8086 and a proposed implementation of the 68000 on the bus. Though very recent additions to the specification, both of these implementations are supported with products and make use of a multiplexed databus to provide the eight additional address lines and the extra data field width. The proposed European format STD bus includes an undefined pin (c24 reserved) and specifies that rows a and c are used for the 8-bit bus signals, leaving row b undefined. The three row DIN connector body is widely available fitted with either rows a and c or all three rows a, b and c. Thus the potential for a second level STD bus, complete with a 16-bit wide data path, a 16 Mbyte addressing capability and an expanded control bus is provided. It is intended that the reserved pin be used to indicate to two row cards in the system that the third row is in use. Although such a bus structure may seem superfluous in the presence of such wide-path buses as VME and IEEE P896, it should be noted that the interface to the bus continues to remain simple, the system retains its high modularity and thus a 16-bit Eurocard STD bus would be considerably cheaper to implement. It would provide an attractive alternative to manufacturers requiring 16-bit power but who
464
Table 4. Proposed European STD bus pin out a 1
ov
2 3 4 __ 5 6
+sv O~ D6
C
b /
) ) j; /
D5
) .
.
.
.
.
D4
7
A15
8 9 10
A13
AI4
,, ~'
11 12 13 14 15 16
AIO
J
A~
~_ ~8
)
ov
~)
RD*
) ) )
17
MEMRQ*
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MEMEX
(
.
)
....
y
(~ (
ol
DO
(
0V
( ( ( ( ( ( ( (~
A7 A6 A5 A4 A3 A2 A1 A0
(
WR*
(
IOEXP
)
BUSRO*
"~
STATUS 1"
(
WAITRQ*
\f
( )
C
ACI AUX GND
BUSAK* INTAI~
) )
PBRESET* CNTRL* PCI
) /
IORQ*
INTRQ 1"
~-
)
(
REFRESH*
STATUS O*
INTRQ 3*
)
)
(
MCSYNC*
INTRQ 2*
+5V
D3
)
RESERVED SYSRESET* CLOCK* PCO
~-
ACO
(
AUX GND AUX+V
AUX-V +SV
)
ov
~,
+5V
C
0v
are uninterested in the sophisticated protocol of the high end buses, which is necessarily expensive to implement. The proposed European format STD bus, though only recently introduced, is supported by a number of UK manufacturers, and interest is spreading rapidly. French, Spanish and Italian distributors of STD bus cards have expressed concern at the business they are losing to Eurocard-based systems where a customer has preferred to restrict himself to a single-sourced product rather than suffer the disadvantages of a nonstandard card size based on a less reliable connector.
CONCLUSIONS Obsolescence and tenability Since its introduction in 1978 by Pro-Log and Mostek, 5TD bus has consistently proved its value to the industry by the demonstration of support from an ever-increasing number of manufacturers and users. It provides an extremely cost effective solution for simple uniprocessor systems with relatively low cycle time requirement, and is a significant solution for multiple processor systernswith simple architectures. It does not, and was never intended to, support the sophisticated 'state-of-the-art' multiprocessor architectures which use advanced programming concepts such as interintelligence and block transfers, nor does it provide resources for memory intensive systems. Largely due to the ever-decreasing cost of components and systems, and to the conceptual development of software techniques, multiprocgssing is becoming a more and more realistic system solution in application areas where such techniques had previously been prohibitively expensive.
microprocessors and microsystems
STD bus, therefore, has a built-in obsolescence and will gradually become less and less useful though this is many years hence. The growth path provided by the European format bus, with its extra row of pins, counters this tendency, providing an effective resistance to obsolescence. The formation of the P961 working group has had the effect of encouraging contribution towards final definition of a standard from across the industry, thus increasing the resources available to provide a complete and practical standard whose implementation is simple and cheap. This means that a usable standard should be published shortly and all design requirements to ensure compatibility with other cards conforming to the standard will be documented to the guidelines set down by the IEEE MSC. This backplane bus standard, IEEE P961, and its complementary Eurocard version, will provide an effective basis for the design of 8-bit simple architecture systems, for at least the rest of this decade.
REFERENCES 1 5TD ManufacturersGroup STD BUS Specification and Practice Pro-Log Corp., California, USA 2 Electro '82 proposal for a European format STD bus
GMT Electronic Systems, London, UK 3 International Electrotechnical Committee Publication 297
Issue 2 SC48D Central Office, London, UK (1980) 4 The Eurocard STD BUS specification GMT Electronic
Systems, London
vol 6 no 9 november 1982
BIBLIOGRAPHY Borrill, P 'Microprocessor bus structures and standards' Proc. Euromicro '80 (Amsterdam (September 1980))
Borrill, P P 8 9 6 - PLB-I 7 Electrical and Pinout Considerations Mullard Space Science Laboratory, University College, London (June 1981) Cummings, W C 'STD bus: a standard for the '80s' Proc. Midcon 81 25/1
Elsmore, T 'A low cost backplane bus for the Eurocard' Electron. Prod. Des. (April 1982) pp 69-72
Nicholson, B 'Three/ac bus configurations vie for 16-bit Eurocard ascendancy' Electron. Des. News (March 1982) pp 51-57 Warren, C 'Understanding bus basics helps resolve design conflicts' EDN Vol 26 No 11 (27 May 1981 ) pp 158-173 Vol 26 No 12 (10 June 1981) pp 141-153 Vol 26 No 13 {24 June 1981) pp 157-187 Biewer, M 'This bus handles different microprocessors' Electron. Des. (1978)
EDITOR'S NOTE Report from P961 Chairman The IEEE P961 STD bus working group met in Boston during Electro '82. The approach to specifying the core timing for memory and I/O read and write operations was reviewed and accepted. Preparations are being made to do a release of the first draft for public review. A preliminary draft was distributed to attendees of the June meeting of the Microprocessor Standards Committee for comment.
465
standards bus
STD
to use the bus. Mid-1979 saw the formation of the STD Manufacturers Group [STDMG), whose charter it is to maintain order, resolve unforseen problems and recommend standard practice on methods such as priority interrupt and bus priority. The STDMG have also set up working groups to provide specified practices for implementation of various 8-bit microprocessors on the bus, investigation of a CMOS interface, backplane practice and memory extension techniques. In May 1981 the IEEE Microprocessor Standards Committee IMSC) was again approached and in September 1981 a working group were allocated the project authorization number P961. Later in 1981 an STD bus users group was formed. April 1982 saw the first European manufacturers group meeting, held in Paris at which the European requirement for an STD bus based on the DIN 41612 Eurocard connector was discussed. A formal proposal for a DIN connector STD bus was made at the P961 group's regular meeting in conjunction with the Electro exhibition at Boston May 19822 . In August 1982 the MSC decided to start a working group tasked with developing a bus proposal derived from the STD bus and implemented on a Eurocard with a DIN connector.
bus FUNCTIONAL
BACKGROUND
As implied by its name, the STD busI evolved from beginnings where its potential as a standard was recognized. It started in 1973 when a 4.5 in by 6.5 in card size was selected by Pro-Log to package a variety of microprocessor systems [see Figure I ). The intention was to select a card size that allowed modular convenience to simplify design. Early bus definitions for interconnection of Pro-Log's cards fell foul of the temptation to mix system I/O lines with the processor bus on the backplane. But in 1976 ProLog redefined its bus, separating the I/O interface from the processor bus. The new definition dedicated the backplane to the processor bus and made use of the opposite card edge to provide I/O interface via often familiar connectors. In 1978 Mostek joined Pro-Log and a short time later the final details of the bus specification were complete. The STD bus was announced at Wescon of that year. To realize the potential of industry standardization, it was agreed that neither Pro-Log nor Mostek would register the concept by trademark or copyright. Early contacts were made with the IEEE standards groups. These efforts never gained momentum and it was decided that if the STD bus were to become a standard it would have to be accepted on its own merits. So other manufacturers were encouraged GMT Electronic Systems Ltd, Newport House, 22 Hartfield Road, Wimbledon, London SW19 3TD, UK
vol 6 no 9 november 1982
PARTITIONING
The design principle that has become dominant in 8-bit board level systems is that of system partitioning by function i.e., CPU on one card, a portion of memory on another, specific I/O functions on others, etc. This has partic01ar value in applications were cost is a key factor as it allows a highly modular approach using small cards. The advantages over larger, Multibus or VERSAbus type cards, are
Figure I. STD bus in its original 5.4 x 6.5 in card size
0141-9331/82/090455-I I $03.00 © 1982 Butterworth & Co [Publishers) Ltd
455
• • • • • •
closer tailoring of hardware to the final requirement due to minimal hardware redundancy on eai~h card higher degree of reliability due to lower component count and the rigidity of small cards higher degree of flexibility in system mechanical design conceptual simplicity for the system designer simpler procedures for testing, fault finding and maintenance the small card sizes allow advances in LSI to be optimally used by means of a gradually evolving increase in functionality per card
The greater number of connectors required in a given system can be considered a disadvantage as there is a tendency towards reduced reliability, especially in the case of direct edge connectors.
WHY STANDARDIZE? At this functional level of partitioning, it is clearly necessary that many functions are provided to enable close hardware tailoring. A single company would have difficulty in identifying every requirement and still more in providing functions to satisfy every requirement. It is therefore desirable that many manufacturers provide wholly compatible functions while maintaining the specialization in their own application area (e.g. high precision analogue). Definition of standard interconnection schemes removes the need for companies to split resources or diversify and provides a means for small or specialist companies to support one another by contributing compatible functions. This ensures that system designers have access to a wide range of functions and are not confined to a single source.
Wide acceptance and use of a standard justifies the development costs of custom LSI design at the bus interface. This would naturally increase the real estate available for functions on a card allowing for denser and thus more economic system packaging, though this is considered unnecessary in the case of STD bus due to the simplicity of interface circuits required.
CONTROL STD bus is a synchronous nonmultiplexed backplane bus providing control for the transfer of data over an 8-bit wide parallel path. Although primary provision is for the addressing of 64 kbyte of memory, additional address space may be realized by use of the MEMEX signal extra address space. Table 1 details the pin out and signal mnemonic functions. STD bus can be conceptually illustrated as in Figure 2 as four separate buses. The 22-line control bus is carefully defined to achieve a significant degree of CPU independence with minimal modification of the component level bus in its translation to the backplane bus. This reduction in complexity of the bus interface logic compared to, say, Multibus or VME, allows an attractive level of system partitioning on the small card size defined by the STD bus mechanical specification. Direction of data movement on the bus is controlled by separate read [RD*) and write IWR*)~- signals. The RD* and WR* signals are also used to gate data on and off the bus. This technique is familiar to users of Intel processors tThe trailing asterisk (*) denotes an active-low signal.
Table 1. STD bus pinouts with signal flow referenced to the processor card Component side Pin Logic power bus
1 3 5
Circuit side
Mnemonic
Signal flow
Description
+5 V DC GND VBB#1
In In In
Logic power (bussed) Logic ground (bussed) Logic bias#l (-5 V)
Pin 2 4 6
Mnemonic
Signal flow
Description
+5 V DC GND VBB#2
In In In
Logic power (bussed) Logic ground (bussed) Logic bias#2(-5 V)
Databus
7 9 11 13
D3 D2 D1 DO
In/out In/out In/out In/out
Low order databus Low order databus Low order databus Low order databus
8 10 12 14
D7 D6 D5 D4
In/out In/out In/out In/out
Highorder databus Highorder databus Highorder databus Highorder databus
Address bus
15 17 19 21 23 25 27 29
A7 A6 A5 A4 A3 A2 A1 A0
Out Out Out Out Out Out Out Out
Low Low Low Low Low Low Low Low
16 18 20 22 24 26 28 30
A15 A14 A13 A12 A11 A10 A9 A8
Out Out Out Out Out Out Out Out
High order addressbus High order address bus High order address bus High order address bus High order address bus High order address bus High order address bus High order address bus
Control
31 33 35 37 39 41 43 45 47 49
Out Out In/out Out Out Out In Out Out Out
Write to memory or I/O I/O addressselect I/O expansion Refresh timing CPU status
51
WR* IORQ* IOEXP REFRESH* STATUSI * BUSAK* INTAK* WAITRQ* SYSRESET* CLOCK* PCO
Interrupt acknowledge Wait request System reset Clock from processor Priority chain out
32 34 36 38 40 42 44 46 48 50 52
RD* MEMRQ* MEMEX MCSTNC* STATUS0* BUSRQ* INTRQ* NMIRQ* PBRESET* CNTRL* PCI '
Out Out In/out Out Out In In In In In In
53 55
AUX GND AUX + V
In In
AUX ground (bussed) AUX positive (+12 V DC)
54 56
AUXGND AUX-V
In In
bus
Auxiliary power bus
456
Out
order address bus order address bus order address bus order address bus order address bus order address bus order address bus order address bus
Bus acknowledge
Read memory or I/O Memory address select Memoryexpansion
CPU machine cycle sync. CPU status Bus request Interrupt request Nonmaskable interrupt Push button reset
AUX timing Priority chain in AUX ground (bussed) AUX negative (-12 V DC)
microprocessors and microsystems
User’s
a
interface
Motor
Soknoid
Digital
Processors
Input ports output ports
8085 280 6800 Other
STD
I IO
Analogue interface
l/O
D/A converters AID converters
I
Peripheral
Industrial
UART control CRT Other
Optolnput triac relay drivers
panel
I
l/O
I
bus Interface
Figure 2. STD bus implementation and the 280, but is inherently less flexible than the method of data transfer control associated with the 6800-type processors which use a logical read/write (R/W*) signal to control data direction and a separate synchronization strobe signal (E). In this method the R/W signal precedes the synchronization strobe in the time domain allowing for a period of data set up time. This is useful for turning around bidirectional bus transceivers, for example. The separate RD* and WR* strobe technique has, however, the advantage of requiring less interface logic for most CPUs and is commonly used with bytewide memory.
6500 family peripheral circuit such as the 6821 peripheral inteface adaptor. These circuits require a presynchronization read/write signal as described above. STD bus makes provision for this and other processor status signals that are specific to one CPU by, means of four peripheral timing control lines. These four lines are separately defined for each CPU type to provide for specific timing requirements as shown, for example, in Table 2; it is in this way that the STD bus achieves CPU independence. So, although, all memory functions and simple input and output functions can be
, STD
Processortype independence The attributes are
in which CPU independence
is fundamental
applications which can implement the CPU whose architecture and instruction set offer the most relevant facilities system designs which can be upgraded late in their development without major hardware redesign different CPU families which can be used within the same system allowing optimum use of existing LSI devices STD bus displays of all these attributes but the latter, only with careful design. Any g-bit CPU type can control data transfers over the bus by means of read (RD*), write (WR*), memory request (MEMRQ*) and I/O request (lORQ*) signals, all of which can easily be derived from that CPUs component level bus. Figure 3 illustrates the 6809 as an example. A complication occurs when data is written to a 6800/
vol6
no 9 november 1982
Date
bus
DO- D7
ADDfi
AO-A15
IORQ*
6809 CPU
WR%
Rllnr
RD*
E 0
B& control Figure 3. Interfacing a 6809 to the STD bus
457
solution, and although STD bus is not truly processorindependent, it offers an attractive compromise on the two major alternatives which are either truly CPU independent systems using large cards with sophisticated interface logic or cheaper small card systems which simply extend the CPU bus signals on to the backplane. The former are prohibitively expensive in the application area under discussion and the latter offer no potential for CPU independence.
Table 2. Peripheral timing control lines for various 8-bit microprocessors 8-bit microprocessor
8080 8085 NCS800 8088 Z80 6800 6809 6809E 6502
REFRESH*
MCSYNC*
Pin 37
Pin 38
REFRESH*
SYNC* ALE* ALE* ALE* (RD*+WR*+INTAK*) ,
REFRESH*
STATUS1*
EOUT*(02*) EOUT*(D2*) 02* STATUS 0*
Pin 39
Pin 40
MI* S1" SI* DT/R* MI* VMA*
SO* SO* SSO* R/W* R/W* R/W* R/W*
--
8080 8085 NCS800 8088 Z80 6800 6809 6809E 6502
--
LIC* SYNC*
M i x i n 0 generic C P U families Any attempt to overcome the inherent incompatibilities between CPU families (to interface a Z80 CPU to a 6821 PIA, for example) necessarily results in an increase in the complexity of the bus interface. A variety of techniques can be used to overcome such compatibility problems, the particular method used depending upon the CPU families being mixed. The resulting cost factors and performance degradation (due to the introduction of wait states or clock stretching) must be considered and justified. Some CPU families interrelate more easily than others (6800 and 6500 for example) and others can be interrelated by simple decoding of the CPU status lines provided by STD bus (as in the case of the 8085 CPU controlling 6800 family peripheral circuits - see Figure 4). The most logical approaches for designers wishing to mix CPU fa'milies on STD bus are either to restrict themselves to a uniprocessor architecture and allow the processor's component level signals to dominate the backplane bus or to use a permanent bus master/intelligent slave class of multiprocessing architecture where each slave is entirely, but possibly uniquely, restricted to one particular CPU family.
designed to be compatible with any CPU cards, some interface cards using LSI peripheral chips will be incompatible with certain CPU cards. This method of achieving CPU independence requires that any attempt at providing a rigid standard must separate out universal elements such as memory and I/O timing to a core specification. Separate specifications must also be defined for each CPU type, detailing timing for specific hardware signals, interrupt and DMA protocols, etc. CPU independence is of paramount importance in a bus specification which is aimed at providing a universal
B u f f e r e d drive STD bus specification defines a set of signals which must mean something to the cards on the bus. For most CPU STD bus
A8 - A5
[O/M A7 ADO-AD7
/8\/8
ALE 8085 CPU
A7 - A3
74LS373 / Address Latch - - - I line
A2 - AO
T ,
RS 68XX o r 65XX peripheral
D7 I bus 8 DO
I Data
I
8
DO- D7
RD WR sI
E R/~
8085 CPU card
68XX / 65XX family interface CAI
Figure 4. 8085 interface to 65xx/ 68xx periphera/ circuits via STD bus
458
microprocessors and microsystems
cards, the required interface is an expansion of the CPU level bus and is extended on to the backplane via bus buffers. The definition of the STD bus signals allows a minimal modification of the CPU bus, which is a necessary feature. This is because only limited time is available for transition delays through the interface logic. The simplicity of interface is a considerable cost saver for systems operating with a relatively low cycle time [around 1 MHz), but introduction of wait states and clock stretching techniques is necessary for higher clock speeds, thus increasing the interface complexity and the cost. As the system clock frequency is increased, the time available for address decoding and buffer transition is reduced. This is illustrated for the case of the 6800 generic family in Table 3. Note that the 2 MHz [B series) family is allowed no extra time at all for buffer transition delay in write cycles. Throughput cannot be continually increased by turning up the system clock, as there is a maximum frequency which is determined by current technology component transition speeds and by transmission line effects on the backplane. Designers seeking greater throughput and computing power must graduate to more powerful solutions provided by more sophisticated buses.
Memory extension The potential for extending the bus' addressing capability beyond 64k is provided by the memory extension {MEMEX) signal. MEMEX can be used in a number of different ways. Three examples are: • to expand the address space to 128k • to distinguish between local and global memory resources - allowing a 64k global resource, to be shared by all resident processors and a 64k local resource, a portion of which can be allocated to each processor • to disable primary memory for bootstrap operations [phantom memory) The STDMG has formed a working group to study these methods and others. MEMEX is commonly provided via an I/O port resident on the master CPU card. A method of memory expansion which has been proposed is to extend this idea to having each of the eight lines of an I/O port define a separate 64k memory plane. This method is clearly expensive in both administrative software and in hardware as every memory card must decode an I/O port. Techniques of this sort attempt to stretch the resources of STD bus beyond their limits and indicate a need to seriously consider more sophisticated bus structures and wider path processors with a greater addressing capability for such applications. One of the most common criticisms of STD bus is that
Table 3.6800 generic bus buffer/decode time provision Clock
Available address
frequency
buffer/decoder
CPU
(MHz)
Time (ns)
Available data buffer time (ns) Read Write
6809
1
150
80
365
68A09
1.5
80
30
230
68B09
2
60
30
160
6802
1
100
60
60
68A02
1.5
40
20
30
68B02
2
10
15
0
its addressing capability is limited, though the 128k provided is a generous allocation for most 8-bit applications. However, some of the more recent applications of the bus, such as the multitask multiuser development system marketed by Yrel of France, indicate that greater resources are required. Designers of these sort of applications, which require the addressing capability of 16-bit microprocessors, do not find that the highly sophisticated bus structures such as VME and P896 or the less modular approach of Multibus-type cards provide tangible solutions. There is thus a clear requirement for a simple STD-type bus structure that can provide these resources.
Input/output The design philosophy of STD bus cards, illustrated in Figure 5, favours the implementation of I/O-intensive systems wherein each I/O function is specific to one card, allowing both conceptual and electrical isolation of nonrelated signals. This is particularly useful in an industrial control situation where high voltage outputs and sensitive inputs may be isolated either by relays or opto devices and can be kept physically separate within the same system. The positioning of an I/O connector at the user interface edge of the card allows an orderly signal flow across the card, separating the I/O function from the bus interface logic. The bus provides an I/O request [IORQ*) signal to differentiate between I/O transfers and memory transfers on the bus. IORO* identifies I/O transfers which, using RD* and WR* strobes, are otherwise identical to memory transfers. In this way both separate I/O plane and memorymapped I/O techniques can be implemented. In the case of the latter, IORQ* can be decoded from the upper address lines on the CPU card. The separate I/O plane defines 256 addresses, allowing a total of 256 input ports (using RD*) and 256 output [using WR.*). This may seem a restricted allocation for I/O intensive systems but is enhanced by the provision of an I/O expansion signal (IOEXP) which allows the primary plane of I/O to be disabled, thus, doubling the facility. Current trends in the design of LSI peripheral devices indicate a more efficient use of address space; a device will typically use two addresses, a control port and a data port - the control port being used as a pointer to internal registers. An example is the Advanced Micro Devices AMD9513 system timing controller, wttich uses just two port addresses to control five 16-bit counters. This represents a considerable saving in address space compared to, say, a Motorola MC6840 programmable timer module which requires eight addresses to control three 16-bit counters.
i !
Bus interface logic
IlO
function logic
: eg: Data latches parallel ports shift registers UARTS AID - D/A
I/O interface
eg : Optoiso level translators line drivers voltage amplifiers
Si~Inalflow
m
Figure 5. STD bus I / 0 card arrangement
vol 6 no 9 november 1982
459
Interrupt and bus priority
tents of an 8-bit 'interrupt vector page' register into the most significant half. The address formed by the 8-bit vector and the page ~egister points to the first of two consecutive memory locations which contain the start address of the specific interrupt service routine relating to that vector. Processors without single-byte vector capability, but providing an interrupt acknowledge signal, can use the scheme illustrated in Figure 7, where INTAK* is asserted while the CPU does two memory read cycles. The CPU address bus addresses the internally-defined vector locations but, by disabling the databus drivers on the memory cards containing those vectors, the system can use INTAK* to force a two byte vector onto the databus from the priority encoder card. Figure 8 illustrates a serial priority interrupt scheme using the PCI and PCO daisychain. Priority is assigned to an interrupting card by virtue of its position on the backplane. The card nearest to the processor card has the highest priority. When a request is made by a card pulling INTRQ* low, the PCO output from that card is also pulled low, this inhibits lesser priority cards from responding to INTAK*. On response to INTRQ*, the processor completes its instruction, stores its status and asserts INTAK*. Cards not involved in the arbitration scheme simply connect PCI to PCO maintaining the daisychain. When the interrupting card recognizes INTAK*, it responds by placing its vector on the databus as described for the parallel scheme. The vectors in this scheme are usually hardwired or switchselected inputs to an octal tristate buffer. The serial priority scheme is simple to implement and required very few bus lines. However it has a number of disadvantages:
STD bus provides signalling for both interrupt and bus requests. Using INTRQ*, conventional interrupt structures can be used, such as that in the 6800, where the processor recognizes the interrupt at the end of the current instruction, provided it is not masked. It then continues with an interrupt service routine whose address is determined by the programmer and inserted in an internally-defined vector location. If more than one interrupting device can assert the INTRQ* line in a given system, then the interrupt service routine can poll the possible interrupt sources to identify the specific interrupt and can then jump to the relevant service routine. This scheme is practical only for just a few interrupts as the polling overheads can become prohibitive. STD bus provides an interrupt acknowledge signal (INTAK*) enabling those CPUs capable of producing such a signal to use vectored schemes to give fast response to interrupts. Arbitration of priority-vectored interrupts on the bus can be achieved either in parallel fashion or by using the serial daisychain formed by PCI and PCO. In the parallel priority example, shown in Figure 6, the interrupts are collected on a separate card (connected via the user interface) which assigns priority using an encoder. The output of the priority encoder drives a vector generator circuit, typically a PROM, which places an 8-bit vector address on the data bus. The processor loads this vector into the least significant half of the program counter and, typically, loads the con-
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460
microprocessors and microsystems
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Bus control arbitration Transfer of the.bus control for DMA or multiprocessing is achieved via a two-wire handshake using the bus request [BUSRQ*) and the bus acknowledge (BUSAK*) signals. The protocol of the handshake is dependent upon the particular CPU in use. Handover between different CPU types may not necessarily be possible due to protocol incompatibilities. Generally, though, these signals should be purely asynchronous and a requesting controller, having succeeded arbitration, should receive a BUSAK* at some unspecified time later. The daisychain can be used in an identical fashion to that described above to arbitrate between multiple masters requesting the bus for DMA or multiprocessing purposes. Again such schemes are limited by propogation delays. Clearly, if the daisychain is used for bus control arbitration, it cannot also be used for interrupt arbitration, In such circumstances only polled interrupt schemes are possible and all interrupts must be handled by one processor. This restricts the bus' usefulness to only one class of multiprocessing architectures, i.e. those requiring the use of a centralized master.
ELECTRICAL INTERFACE The technology specified for the STD bus interface is low power Schottky TTL, though moves are afoot to define a CMOS interface for the bus. This is a logical progression and should present no significant difficulty as some of the latest technology CMOS devices outperform TTL LS logic in terms of both driving capability and speed. A number of semiconductor manufacturers have, indeed, introduced ranges of pin-compatible CMOS devices, notably memory and octal bus interface circuits. The bus uses three-state rather than open collector drivers. The inherent advantage of design simplicity outweighing the superior driving performance of open collector devices [used in a properly terminated system), which is not required for the relatively low transfer rates associated with STD bus. The major disadvantage of three-state drivers is that very high currents can flow in bus-contention situations and permanent damage can occur. To avoid this, system designers must study carefully manufacturer's timing information when interfacing cards on the bus.
vol 6 no 9 november 1982
It is desirable to terminate backplane traces whenever an application requires a backplane of more than a few inches Iong.STD bus, unfortunately, does not define either backplane parameters or termination techniques, though a subgroup of the STDMG is currently studying this. Generally a simple Thevenin equivalent type of termination, such as that shown in Figure 9a, will suffice. The value of the parallel combination of the two resistors should be approximately equal to the unloaded characteristic impedence of the backplate trace, though the limited transfer rates associated with STD bus (2 MHz) allow a wide tolerance in termination. The termination network shown in Figure 9b provides a matched line for high frequencies without imposing a DC load on supplies and driver outputs. STD bus allows up to five regulated power supplies with two separate ground returns, and provides isolation of analogue and logic supplies. The supplies are +5 V logic supply; -5 V low current substrate bias supply - rarely used these days; and -+12 V auxiliary supplies, for RS232C or analogue circuits. The 5 V logic supply and return are provided via bus edge connector pins 1,2 and 3,4 respectively. This has the disadvantage that all signals must return via two connector positions at one end of the connector. This means that some of the signals on the connector are as much as 3 in distant from their nearest ground return. This distance tends to cause a degradation in the transition time of a signal and to cause reflection noise on the line. Neither of these, though, are significant problems as long as the time required for a signal to propogate the full length of the backplane; and back is considerably less than the system clock period. This is normally the case for STD bus. A more insidious problem is that of shock current caused by the data lines or the address lines simultaneously changing state from all 0s to all ls. This current has to be .
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461
absorbed by the backplane ground via pins 3 and 4 which provide ground returns for all other signals. It is possible for the shock current to cause a spike on the ground line large enough to transgress into the transition region of the receivers. Beyond defining the logic levels on the bus, the specification does not detail the electrical interface to the bus in terms of capacitive loads, DC loads, or maximum currents at which the TTL levels specified must be guaranteed true, or hysteresis. This could result in card manufacturers making use of a variety of drivers and receivers displaying inherent incompatibilities when required to operate close to their speed and power limits. A gold-plated direct edge connector is specified for interconnection to the backplane. Still very popular in the US it is unfortunately difficult to obtain in Europe, due to the dominance of the more reliable DIN 41612 connector. It is also becoming a relatively expensive option due to the increasing cost of gold. The direct edge connector is less reliable because of the low insertion life of the soft gold contacts, its vulnerability to dirty environments and the susceptability of its mating connector to mechanical resonance. It also imposes a restriction on the number of connections available at a card edge. One company which manufactures computer control systems for space flight equipment develop their systems using standard STD bus cards, which are then redesigned with a direct edge connector, military specification components and a more rigid card for actual spaceflight modules.
surface area and linear dimensions. Useful attributes, for example, are that two 40-pin DIL circuits can be positioned end-to-end across the width of the card and that eight 14-, 16-, 18- or 20-pin DIL circuits can be positioned side-byside across the width of the card. In Europe, the lack of conformance in the more common Eurocard outline, though, results in a lack of choice for the designer in packaging his systems and inevitably this makes packaging more costly as it may often have to be custom built. For this reason, a proposal has been made to the I EEE P961 committee to consider an alternative mechanical format.for the STD bus specification, to be provided alongside the original format. It should be stressed that this is only a proposal. One of the many attributes of the recently proposed European format STD bus 3 is that a variety of card sizes may be used (Figure 11 ), all of which are totally supported by packaging, racking and backplanes defined by International Electrotechnical Committee spec 2974.
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microprocessors and microsystems
EUROCARD STD BUS The Eurocard concept comprises a family of compatible boards in various sizes, ranging from single to quad height modules with optional length extensions. Figure 12 compares the outlines of the single Eurocard and an STD bus card. The modular nature of the Eurocard family complements that of the STD bus and though most manufacturers prefer single and double height Eurocards at the moment {see Figure 13) the horizontally extended versions offer a considerable real estate increase, allowing much greater functionality without the requirement for a taller rack {Figure 14), in which to house the system. Indeed, manufacturers of CMOS based systems have found it necessary to use extended Eurocards due to the lack of CMOS LSI peripheral circuits such as serial interface adaptors and programmable timer circuits. An extended {220 ram) single Eurocard gives 17 per cent more surface area than a standard STD bus card. Use of multiheight Eurocards also offers some interesting system design alternatives. Due to the identical connectors on each unit of the multiheight Eurocard, multiple bus structures can be implemented in order to increase throughput, or indeed, fault tolerant designs can be implemented using dual redundant buses. A further possibility is to implement all I/O interface on physically separate connectors on the same edge of the card as the backplane. This is particularly useful to industrial users who often prefer to STD 6.5in (165.1mm)
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Figure 14. STD Eurocard bus rack locate I/O at the back of a unit reducing the possibility of misconnection during maintenance. Table 4 illustrates the pinout, signal mnemonic and flow with respect to the processor card. The logical structure of the STD bus has been r.etained in its transfer to the DIN 4161:2 connector. The only changes are a modification of the power supply pinout, rejection of the -5 V substrate bias supply, inclusion of the two 0 V signal returns and the adoption of an enhanced interrupt structure including an additional arbitration daisychain. This can be used either to provide a way out/way back arbitration scheme, in conjunction with the existing daisychain, allowing a greater flexibility in positioning of modules or can be used for multiple processor arbitration. The single Eurocard is nominally 160 m m x 100 mm and makes use of a multipin two-part connector using a maximum of 96 pins organized in three rows of 32. The pins are situated on 0.1 in {2.54 mm) pitches. The surface area of this card is about 15 per cent less than that of an STD bus card. Most commonly used in microprocessor applications are the outside two rows of pins, rows a and c. The third row, row b, is often used to provide 0 V guard tracks on the backplane. In topographical terms row c is equivalent to the component side of and edge connector and row a to the noncomponent side. A direct topographical transfer of the STD bus edge connector positions to DIN 41612 rows a and c would result in the nonuse of eight pins {a29-a32, c29-c32) on the DIN connector. I he proposed Eurocard STD bus capitalizes on these extra pins to improve on many of the deficiencies of the STD bus, which were highlighted earlier, by expanding existing STD bus facilities while maintaining the structure and philosophy of the bus.
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Figure 13. STD bus in Eurocard format
vo/ 6 no 9 november 1982
The advantages of relocating the power supply grounds at both ends of the connector and locating two signal ground returns around the address bus are numerous. The actual ground return currents see a very low impedence. This is especially so if ground gridding has been used in the PCB design, as it can be carried through to the backplane. The shock currents caused by simultaneous switching of the address or databus lines are returned to ground locally so that they do not interfere with adjacent signal lines. The maximum distance of a signal from its nearest
463
ground return is reduced from 3 in to 0.7 in and the two signal return grounds, at connector positions c7 and a15, double as 0 V guard tracks, minimizing crosstalk by reducing capacitive coupling between the address, data and control buses. The last pin to be disconnected when a PCB is removed is always a 0 V pin. This point is a useful safeguard as it is quite feasible that nontechnical personnel may be used for first level servicing of board level systems, which, of course, increases the risk of a board being removed while supplies are still switched on. The -5 V substrate bias supply (Vbb #1 and Vbb #2) has become virtually obsolete and in rare cases where it is required it can be very easily generated locally/using Texas Instruments TL 497, or Intersil ICL7660, for example). So, rather than waste two valuable connector pins, these have been removed. Interestingly, there is pressure within the STDMG to redefine these two connector positions, possibly as an additional priority chain or as + 15 V supplies on the STD bus proper. Enhanced interrupt structure
A third interrupt request line has been introduced in order to allow a much more full implementation of recently introduced CPUs, such as the 6809 with fast interrupt request or the NSC800 with its five interrupt lines. In order to maintain the philosophy of CPU-independence the interrupt functions have been renamed in a manner indicative of priority - I N T R Q I * , I N T R 0 2 * and INTRQ3*. The choice of level at which the processor is interrupted is made at the interrupting card. A further enhancement of the original bus definition is the addition of the auxiliary priority chain (AC1 and AC0). This effectively reduces stress on the interrupt structure of the bus by ensuring that use of a serial priority system of bus control does not preclude the use of a serial interrupt arbitration system, or vice versa.
16-bit growth path Although STD bus was designed to cope with 8-bit transfers only, increasing pressure to make use of the more popular 16-bit processors has led to the definition of an implementation of the 8086 and a proposed implementation of the 68000 on the bus. Though very recent additions to the specification, both of these implementations are supported with products and make use of a multiplexed databus to provide the eight additional address lines and the extra data field width. The proposed European format STD bus includes an undefined pin (c24 reserved) and specifies that rows a and c are used for the 8-bit bus signals, leaving row b undefined. The three row DIN connector body is widely available fitted with either rows a and c or all three rows a, b and c. Thus the potential for a second level STD bus, complete with a 16-bit wide data path, a 16 Mbyte addressing capability and an expanded control bus is provided. It is intended that the reserved pin be used to indicate to two row cards in the system that the third row is in use. Although such a bus structure may seem superfluous in the presence of such wide-path buses as VME and IEEE P896, it should be noted that the interface to the bus continues to remain simple, the system retains its high modularity and thus a 16-bit Eurocard STD bus would be considerably cheaper to implement. It would provide an attractive alternative to manufacturers requiring 16-bit power but who
464
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are uninterested in the sophisticated protocol of the high end buses, which is necessarily expensive to implement. The proposed European format STD bus, though only recently introduced, is supported by a number of UK manufacturers, and interest is spreading rapidly. French, Spanish and Italian distributors of STD bus cards have expressed concern at the business they are losing to Eurocard-based systems where a customer has preferred to restrict himself to a single-sourced product rather than suffer the disadvantages of a nonstandard card size based on a less reliable connector.
CONCLUSIONS Obsolescence and tenability Since its introduction in 1978 by Pro-Log and Mostek, 5TD bus has consistently proved its value to the industry by the demonstration of support from an ever-increasing number of manufacturers and users. It provides an extremely cost effective solution for simple uniprocessor systems with relatively low cycle time requirement, and is a significant solution for multiple processor systernswith simple architectures. It does not, and was never intended to, support the sophisticated 'state-of-the-art' multiprocessor architectures which use advanced programming concepts such as interintelligence and block transfers, nor does it provide resources for memory intensive systems. Largely due to the ever-decreasing cost of components and systems, and to the conceptual development of software techniques, multiprocgssing is becoming a more and more realistic system solution in application areas where such techniques had previously been prohibitively expensive.
microprocessors and microsystems
STD bus, therefore, has a built-in obsolescence and will gradually become less and less useful though this is many years hence. The growth path provided by the European format bus, with its extra row of pins, counters this tendency, providing an effective resistance to obsolescence. The formation of the P961 working group has had the effect of encouraging contribution towards final definition of a standard from across the industry, thus increasing the resources available to provide a complete and practical standard whose implementation is simple and cheap. This means that a usable standard should be published shortly and all design requirements to ensure compatibility with other cards conforming to the standard will be documented to the guidelines set down by the IEEE MSC. This backplane bus standard, IEEE P961, and its complementary Eurocard version, will provide an effective basis for the design of 8-bit simple architecture systems, for at least the rest of this decade.
REFERENCES 1 5TD ManufacturersGroup STD BUS Specification and Practice Pro-Log Corp., California, USA 2 Electro '82 proposal for a European format STD bus
GMT Electronic Systems, London, UK 3 International Electrotechnical Committee Publication 297
Issue 2 SC48D Central Office, London, UK (1980) 4 The Eurocard STD BUS specification GMT Electronic
Systems, London
vol 6 no 9 november 1982
BIBLIOGRAPHY Borrill, P 'Microprocessor bus structures and standards' Proc. Euromicro '80 (Amsterdam (September 1980))
Borrill, P P 8 9 6 - PLB-I 7 Electrical and Pinout Considerations Mullard Space Science Laboratory, University College, London (June 1981) Cummings, W C 'STD bus: a standard for the '80s' Proc. Midcon 81 25/1
Elsmore, T 'A low cost backplane bus for the Eurocard' Electron. Prod. Des. (April 1982) pp 69-72
Nicholson, B 'Three/ac bus configurations vie for 16-bit Eurocard ascendancy' Electron. Des. News (March 1982) pp 51-57 Warren, C 'Understanding bus basics helps resolve design conflicts' EDN Vol 26 No 11 (27 May 1981 ) pp 158-173 Vol 26 No 12 (10 June 1981) pp 141-153 Vol 26 No 13 {24 June 1981) pp 157-187 Biewer, M 'This bus handles different microprocessors' Electron. Des. (1978)
EDITOR'S NOTE Report from P961 Chairman The IEEE P961 STD bus working group met in Boston during Electro '82. The approach to specifying the core timing for memory and I/O read and write operations was reviewed and accepted. Preparations are being made to do a release of the first draft for public review. A preliminary draft was distributed to attendees of the June meeting of the Microprocessor Standards Committee for comment.
465