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Phase-Locked Loop based frequency adder
Signal Processing 10 (1986) 245-252 North-Holland
245
PHASE-LOCKED LOOP BASED FREQUENCY ADDER Dov W U L I C H Department of Electrical and Computer Engineering, Ben-Gurion University of the Negev, P.O. Box 653, Beer-Sheva 84 105, Israel Received 18 September 1984 Revised 11 June 1985 and 1 October 1985
Abstract. The Phase-Locked Loop (PLL) frequency adder is based on the fractional N technique which is successfully applied in the frequency synthesis field. This method may be used to add two frequencies f~ and f2, i.e., to give a one frequency equal to f~ +f2. The only a priori information needed is to know that f~ >f2 and that ft/f2 is a rational number. The proposed method may be effectively implemented by inexpensive digital logic or on a microprocessor when the input frequencies are not too high. This method may be easily extended to frequency subtraction.
Zusammenfassung. Die Frequenzaddierschaltung nach dem PLL-Prinzip basiert auf dem Prinzip des Frequenzteilers, das bei der Frequenzsynthese erfolgreich angewendet wird. Das Verfahren kann dazu verwendet werden, zwei Frequenzen fl und f2 zu addieren, so dab sich eine neue Frequenz fl +f2 ergibt. Es geniigt, im voraus zu wissen, dab f~ grfl3er ist als f2, und dab der Quotient f~/f2 eine rationale Zahl ergibt. Das vorgeschlagene Verfahren l~iSt sich mit Hilfe preiswerter digitaler Logik oder auch auf einem Mikroprozessor implementieren, wenn die beteiligten Frequenzen nicht grol3 sind. Die Erweiterung des Verfahrens auf die Subtraktion von Frequenzen ist einfach. R6sum6. L'additionneur de fr6quence ~ boucle de phase asservi est bas6 sur la technique fractionnelle N qui est utilis6 avec succ~s dans le domaine de la synth6se de fr6quence. Cette m&hode peut ~tre utilis6e pour additionner deux fr6quences f~ et f2 pour donner une seule fr6quence f~ +f2. La seule information a priori n6cessaire est de savoir que fl est sup6rieur ~ f2 et que f~/f2 est un nombre rationnel. La m6thode propos6e peut ~tre raise en oeuvre efficacement avec de la logique num6rique bon march6 ou par microprocesseur quand la fr6quence d'entr6e n'est pas tr~s 61ev6e. Cette m6thode peut ~tre 6tendue facilement ~ la soustraction de fr6quences. Keywords. PLL, frequency adder.
1. Introduction The Phase-Locked Loop (PLL) in its linear approximation may be considered as a feedback control system. The system with proportional controller (often named electronic servomechanism [7]) is considered (see Fig. l(a)). Physically, the input and output are periodic waveforms: a train of pulses with frequency fl as input and with frequency fc as output. But, in PLL analysis, the phases of signals 0~ and 0c serve as system variables and, there, the PLL may be reduced to the feedback control system (see Fig. l(b)). The considered system is a sampled data system, i.e., the system
variables (phases) are taken at discrete times, namely at t = 0, T, 2 T , . . . , where T is the period of the system's clock. Let us consider the system from Fig. l(b). If an additional signal 02(k), which represents another train of pulses with frequency f2, is introduced to the adder (see Fig. 2), then, because of the loop's efforts to keep the error e(k) constant, 1 the frequency f¢ will be equal to fl +f2. This proves that it is possible, at least theoretically at this stage, to build a frequency adder (frequently named up converter) on the basis of a PLL. t Here we consider PLL of type 1 in which the steady state error e(k) depends on the VCO frequency.
0165-1684/86/$3.50 © 1986, Elsevier Science Publishers B.V. (North-Holland)
246
D. Wulich / PLL based frequency adder
_J--L_F-L Sampling
f~; el
Phase Detector
_~[J
e ~
Loop Filter toptlonal )
I~
m
VCO
~
C,OC
optional) b
Fig. 1. PLL as a feedback control system.
To realize the system of Fig. 2, it would be necessary to have a special phase detector which generates O j k ) + O 2 ( k ) - O J k ) . Such a phase detector does not exit. A usual phase detector compares the phases of two signals only.
rgl(k),fl ~'~e(k) I Loop ~ ) , t ¢ ~.d,]----! Filter
ez(k), fz "y'~
I(oPtiorml )
Fig. 2. Feedback control system with two inputs.
The main problem which should be solved is to generate a voltage which is proportional to 01(k) + 0 2 ( k ) - Ojk). A solution proposed here is based on the following. It is possible to use a phase detector to measure the difference O~(k) - Oc(k). If we do so, it remains to measure the absolute phase of frequency f2, i.e., 02(k); the value of phase 02(k) is converted to a physical value like that of e(k) (which is proportional to the difference O~(k)0c(k); see Fig. l(b)) and then added to e(k). 2 Such a solution only formally solves our problem, because the signal 02(k) represents a phase and therefore is a staircase signal which goes to infinity when the time increases. This problem is success2 e(k) may be current, voltage, or charge. Signal Processing
fully solved by resetting 02(k ) to zero every time the VCO makes one additional cycle as a response to the second input with frequency f2. Simultaneously with the reset command an extra pulse should be removed at Oc(k) input of the phase detector in order to keep the VCO control voltage equal to a constant value. Such a procedure is a theoretical basis of the fractional N technique, which is used, as mentioned above, for frequency synthesis [3, 4, 9] and for FM modulation of PLL from DC [2]. As will be clear later, the circuit used in order to realize the proposed method is not simple. But it has some advantages compared with a simple frequency adder, e.g., the mixer: (1) The proposed system addes two frequencies, while the mixer gives a sum and a difference of input frequencies. (2) The input signals can be of arbitrary shape; in the mixer, the input signals should be sine waves; if not, an intermodulation product appears at the mixer's output. (3) The level of the output signal does not depend on the input level, so if, for example, it is used for achieving the IF in an FM receiver, then there is no need for a limiter in the demodulator. The paper is organized as follows. A basic algorithm is presented in Section 2. In Section 3
D. Wulich/ PLL basedfrequency adder an analysis of the proposed system is given. Section 4 gives a computer simulation.
from (1), /3(k) represents the increment of the phase 02 (measured in 'cycles') during one period of the signal u~(t). It will be proved later that lim f l ( k ) = A / A ,
2. Basic algorithm
247
koc~
(2)
The block diagram of a PLL based frequency adder, which realizes the idea proposed in Section 1 is given in Fig. 3. Here we assume that f, >f2. The system is clocked by a pulse train with frequency f, (the sampling period is l/f,). Let us first explain the main blocks of Fig. 3.
i.e., fl(k) in steady state represents the ratio f2/f~. Suppose, at this stage, that the ratio f2/f, is known. In order to generate the absolute phase 02(k) it is necessary to integrate the value f2/f,, i.e., to generate a signal
2.1. Description of main blocks
which in fact is equal to the phase 02(k ). If we put T = 1/f,, we obtain 02(k)=f2kT. In a real system, the ratio f2/f, is computed 'on line'; therefore, the signal n(k) is computed according to
As was mentioned above, it is necessary to measure the absolute phase of the signal having the frequency f2. In order to do this, the above ratio is computed,
(1)
fl(k) a=Nk/k,
where Nk is the number of cycles of the signal u2(t) within k cycles of the signal ul(t). As follows
°l(k)'flu I U) --r,llSomp|inqoetecl~orPhase ~+~
t
n(k) = (AIA)k,
n(k)= n ( k - 1 ) + fl(k),
(3)
(4)
which leads to a transient at the VCO output as /3(k) only in infinity represents the value f21f,.
Filter
~n(k)=ez(R)
Pulse J ~emoverJ"
Carry V- Clock
----
~.tk~ [ Z" -' f_lFrequency ZlRofio u2(t) JComputot|on Fig. 3. Blockdiagram of the frequencyadder. Vol. 10, No. 3, April 1986
248
D. Wulich / PLL based frequency adder
As follows from (4), n ( k ) goes to infinity when k increases. To overcome this, the accumulator which generates n ( k ) (see (4)) is 'limited to 1', i.e., when n ( k ) > 1, the content of the accumulator is reduced by 1, a carry signal is produced which initiates a pulse remover command, and the counter then counts an extra period. This procedure keeps the VCO tuning voltage constant in the steady state, and keeps the values 02(k) and e ( k ) (see Fig. 3) within a dynamic range of the system. If an implementation of the accumulator (integrator) is digital, then the number of bits of the adder gives an additional restriction on the frequencies fl and f2, namely A = LT,/2",
where N is the number of bits and 1,2,...,2N-1.
From the above it follows that there is only one equilibrium point at which the phase error is fixed and the VCO frequency equals fl +f2. For better illustration, an example of waveforms n ( k T ) and e ( k T ) is given for f l = 1 0 and f 2 = 3 (see Fig. 4). 2.3. Transfer functions
The considered system is a sample data system and, consequently, the Z-transform technique is applied for analysis. There are two transfer functions related to the two inputs of the system (Fig. 2). The first is given by a 0¢(z) I O'(z) = o , - ~ o2~k~=o
(S) L=
(8a)
and the second by
O2(z)
a= O¢(z) O~(z) o,~k~=o
(8b)
2.2. Description o f the whole system
Suppose, for explanation only, that the frequency f~ =f~ +f2; therefore, the phase error is given by
In order to obtain explicit formulae for Gl(z) and G2(z) we observe after Lindsey and Chie [8] that the transfer function of VCO is given by
e( k ) = [ 2rtflk r + 0 ° - ( 2"rrf¢kT + O°)]kp = [-2~rf2kT+ O1o Oc]kp, o
Hvco(Z)-
kvco Tz- ' 1 - z -1 '
(9)
(6)
where kp is the phase detector gain; i.e., this phase error linearly decreases as a function of time (here discrete time). As already known [8], the sampling phase detector acts as a phase comparator (adder in Fig. l(b)) only when the phase difference is less than 2~r. The action of the pulse remover holds the phase difference within the interval [0, 2~r]. The signal e ( k ) is added to the voltage a n ( k ) , where a is some positive constant. The resulting signal e(t) is given as
where kvco is the gain of VCO. So, kpHvco( Z ) G1(z) = 1 + kpHvco(Z) kpkvcoTz -1 = 1 + z - l ( k p k v c o T - 1)
(10a)
and G2(z)=
Hvco(Z) 1 +kpHvco(Z)
e(k)=e(k)+an(k)
kvcoTz- 1 - 1 + z-X(kpkvcoT-I)"
= kp[-E~rf2kT+ 0 ° - 0 °] + ~ A k T = kp(O ° - 0°),
where a = 2~rkp. Signal Processing
(7)
(10h)
Eq. (10) will be useful in the next section for stability and convergence considerations.
D. Wulich / PLL based frequency adder
249
E(kt)
7/" C= ~TT
L•
-7~+C
I •
1__, L_~
.
I
kl
-71" C 4 7t" iarbltrory)
n(ktl 1.2
I.(3 O.8 Q6
Q4 0.2 0
?
I J
1 I
Pulse
I
I
I T /1
J
± I
ft~
kT
removing
Fig. 4. Example of n(kT) and e(kT).
3. System analysis
[5]. In our case the system is stable if'
(12)
0
3.1. Stability or
From (10), the characteristic equation of the system is given by
F(z)=z+(kL-1),
(11)
where KL = k p k v c o T is the normalized loop gain. A sampled data system is stable if all roots of the characteristic equation are within the unit circle
f l >~kpkvco '
for kp>0.
(13)
This condition gives a restriction on the frequency f~. If a loop filter is used, (13) is not true; however, it represents an 'upper bound' of a specific restriction which depends on the loop filter transfer function. Vol. 10, No. 3, April 1986
D. Wulicb / PLL based frequency adder
250
3.2. Convergence time
or
A convergence time is defined here as a time in which the VCO reaches the steady state frequency within specified error band. The convergence time depends on the following factors: loop constant kL, initial frequency of the VCO, fo, and the ratio f2/fl which determines the convergence of/3(k), i.e., the convergence time depends both on the loop parameters and on the external quantities,
fo, f,,f2. First we analyze the convergence time assuming that /3(k)=f2/fl=constant. m(k) can be calculated from Ol(k) and 02(k) by the Z-transform
M(z)=
k p ( 1 - z - i ) Ol(Z) l + ( k r - 1 ) z -1 (14)
For the initial VCO frequencyfo, the instantaneous frequency as a function of discrete time is obtained by using the inverse Z-transform of (14) when Ol(k) = k and 02(k) =f2Tk, fi,,~t(k) = kvcom(k) (fl +f2 - f o ) [
1 - (1 -
k=0, 1,2,....
~< l/k,
kL)k] +fo (15)
(17)
which proves (2). Now, our efforts will be concentrated on translating (17) into the settling time of the VCO frequency assuming that the loop convergence equals one period off1. From the considerations of Section 2 and the basic principle of fractional N technique [4] it follows that, under the steady state loop condition, the resulting VCO frequency is given as
fc=fl + /3(k)fv
(18)
From (17) and (18), the VCO frequency deviation Af¢(k) is therefore bounded by
Aft(k) a=l Y e - f , -f2l <~fl/k.
(1 - z -l) 4 1 + (kL-- 1)Z-' 02(z).
=
I/3(k) - f U f d
(19)
From (19), the settling time is easily obtained. It should be pointed out here that the result obtained is not general and depends on the/3(k) computation method. But, with no connection with a specific method of/3 (k) computation, the convergence of/3(k) depends on the value off2 and is equivalent to the time needed to measure the frequency f2. Therefore, the convergence of/3(k) (especially for low f2) is a dominant part of the whole convergence process. This means that the loop gain kL should be chosen to guarantee the loop stability only according to (13).
Here we assume that the initial phase difference
~(0) =0.
3.3. Jitter
From (15) for any specific fo, kL and a given frequency accuracy the convergence time can be found. It is very interesting to observe that, for kL = 1,f,st(k) =f~ +f2 (k = 1, 2, 3 , . . . ) and does not depend onfo. So, at least theoretically, it is possible to obtain a loop convergence equal to one period of ft. Now, let us analyze the convergence of/3(k). From the definition of Nk it follows that Nk = [kf2/fl] or Nk = [kf2/fl] + 1, where [. ] denotes real to integer truncation. From the above, the following inequalities are obtained:
There are no theoretical reasons for jitter in steady state. However, in a practical system there will appear some jitter which is a 'superposition' of a variety of factors connected with specific hardware implementation and working frequencies. Here we consider only one, which appears as a direct consequence of the fractional N procedure. The second input, 02(k) (see Fig. 2), is introduced to the loop via a summing node (Fig, 3), 3 which in practice is implemented with some finite accuracy. Let us analyze the influence of the 3 The q u a n t i t i e s w h i c h are s u m m e d m a y be voltages, cur-
k f U f , - 1 ~ N~ <~ k f U f l + 1 Signal Processing
(16)
rents, or charges.
D. Wulich/ PLL basedfrequency adder given as
summer accuracy on the jitter. For this, we suppose that the nonaccuracy will be represented by periodic signal y(k) (Fig. 3) having a frequency o f f , =fl/n, where n is the minimal numerator of the rational number fl/f2, and the amplitude depends on the accuracy of the summing node. The shape of the signal y(k) is very difficult to predict and depends on many features, so that in the worst case we may assume that
y(k) = A~ cos(2rrf, Tk),
Arc = IH~ (f.)lAr.
The proposed method was simulated on a digital computer. The results obtained are presented in Fig. 5, in which the normalized deviation of instantaneous frequency from the required (in %) as a function of time (represented here by k, number of periods fl) is given. The initial frequency of the VCO is chosen to be equal to fl, and the normalized loop gain kL=0.16. As can be seen from Fig. 5, the output frequency fl+f2 has a jitter which decreases with time (as was explained in Section 3.3 ), according to the convergence of/3 (k) to f2/fv It is observed that for f2/fl =0.01 or 0.1, in our example, the instantaneous frequency is greater than the final frequency and decreases towards f~ +f2 in spite of the fact that the initial frequency is f~ and the loop is overdamped (kL=0.16), i.e., the convergence should be monotonically increased from f~ up tof~ +f2 (see (15) for kL< 1).
where Ar represents the accuracy of summing. As we shall see later, this approximation leads to the upper bound of the VCO frequency deviation. The transfer function relating y(k) to the VCO frequency fc is given as
(21)
and the frequency response is therefore given as [ 1]
U~(z)lz-v=,,,.
H~(f) =
(22)
The upper bound of the VCO frequency deviation Arc caused by nonaccurate summing node is ~ ~
5
I
I
I
= I 40
I 60
I 80
(22a)
4. Computer simulated results
(20)
k v c o ( 1 - z 1)
251
I
I
I
I
I
I 140
I 160
I 180
4"
3"
~
z.
Z
I'
0 p,~ 0
~-Z ~ -4, i
q 20
I
I00
I 120
200 k/f D
TIME
Fig. 5. Normalized deviation of resulting frequency from the required as a function of time. Vol. 10, No. 3, April 1986
252
D. Wulich / PLL based frequency adder
The explanation of this behaviour is based on the fact that fl(k) in the first stage of its convergence can achieve much greater values than required, particularly for small f2/fl. For example, forf2/f~ = 0.1, we have/3(1) = 1,/3(2) =0.5, and/3(3) =].
5. Summary The PLL frequency adder based on the fractional N technique is described. The proposed system adds two frequencies, fl and f:. f~ must be greater than f2 and f~/f2 must be a rational number. The system can be divided into two functional parts: (1) the PLL with the fractional N procedure, and (2) the block which computes the ratio f2/fl. It is proved that in the steady state condition there are no theoretical reasons for any jitter of the output frequency, The convergence time, which is combined from convergence time of PLL and convergence time of fl(k), practically depends on the convergence of/3(k). The proposed method may be effectively implemented by inexpensive digital logic or on a micro-
Signal Processing
processor when the input frequencies are not too high. This method may be extended to frequency subtraction.
References [1] S.M. Bozic, Digital and Kalman filtering, Arnold, Paris, 1979. [2] M. Da Silva, "Synthesis of FM signals", RF Design, September/October 1984, pp. 29-38. [3] J. Gorski-Popiel, Frequency Synthesis: Techniques and Applications, IEEE Press, 1975. [4] K. Jessen, "Fractional-N simplifies frequency synthesis", Bench Briefs, Service Information from Hewlett-Packard, May-August 1977. [5] E.I. Jury, Theory and Application of the Z-Transform Method, Wiley, New York, 1964. [6] B. Kuo, Automatic Control Systems, Prentice-Hall, Englewood Cliffs, NJ, 1975. [7] W. Lindsey and M.K. Simon, Phase Locked Loops and Their Application, IEEE Press, 1978. [8] W.C. Lindsey and C.N. Chic, "A survey of digital phaselocked loops", Proc. IEEE, Vol. 69, No. 4, April 1981, pp. 410-431. [9] U.I. Rodhe, Digital PLL Frequency Synthesis, Theory and Design, Prentice-Hall, Englewood Cliffs, NJ, 1983.
245
PHASE-LOCKED LOOP BASED FREQUENCY ADDER Dov W U L I C H Department of Electrical and Computer Engineering, Ben-Gurion University of the Negev, P.O. Box 653, Beer-Sheva 84 105, Israel Received 18 September 1984 Revised 11 June 1985 and 1 October 1985
Abstract. The Phase-Locked Loop (PLL) frequency adder is based on the fractional N technique which is successfully applied in the frequency synthesis field. This method may be used to add two frequencies f~ and f2, i.e., to give a one frequency equal to f~ +f2. The only a priori information needed is to know that f~ >f2 and that ft/f2 is a rational number. The proposed method may be effectively implemented by inexpensive digital logic or on a microprocessor when the input frequencies are not too high. This method may be easily extended to frequency subtraction.
Zusammenfassung. Die Frequenzaddierschaltung nach dem PLL-Prinzip basiert auf dem Prinzip des Frequenzteilers, das bei der Frequenzsynthese erfolgreich angewendet wird. Das Verfahren kann dazu verwendet werden, zwei Frequenzen fl und f2 zu addieren, so dab sich eine neue Frequenz fl +f2 ergibt. Es geniigt, im voraus zu wissen, dab f~ grfl3er ist als f2, und dab der Quotient f~/f2 eine rationale Zahl ergibt. Das vorgeschlagene Verfahren l~iSt sich mit Hilfe preiswerter digitaler Logik oder auch auf einem Mikroprozessor implementieren, wenn die beteiligten Frequenzen nicht grol3 sind. Die Erweiterung des Verfahrens auf die Subtraktion von Frequenzen ist einfach. R6sum6. L'additionneur de fr6quence ~ boucle de phase asservi est bas6 sur la technique fractionnelle N qui est utilis6 avec succ~s dans le domaine de la synth6se de fr6quence. Cette m&hode peut ~tre utilis6e pour additionner deux fr6quences f~ et f2 pour donner une seule fr6quence f~ +f2. La seule information a priori n6cessaire est de savoir que fl est sup6rieur ~ f2 et que f~/f2 est un nombre rationnel. La m6thode propos6e peut ~tre raise en oeuvre efficacement avec de la logique num6rique bon march6 ou par microprocesseur quand la fr6quence d'entr6e n'est pas tr~s 61ev6e. Cette m6thode peut ~tre 6tendue facilement ~ la soustraction de fr6quences. Keywords. PLL, frequency adder.
1. Introduction The Phase-Locked Loop (PLL) in its linear approximation may be considered as a feedback control system. The system with proportional controller (often named electronic servomechanism [7]) is considered (see Fig. l(a)). Physically, the input and output are periodic waveforms: a train of pulses with frequency fl as input and with frequency fc as output. But, in PLL analysis, the phases of signals 0~ and 0c serve as system variables and, there, the PLL may be reduced to the feedback control system (see Fig. l(b)). The considered system is a sampled data system, i.e., the system
variables (phases) are taken at discrete times, namely at t = 0, T, 2 T , . . . , where T is the period of the system's clock. Let us consider the system from Fig. l(b). If an additional signal 02(k), which represents another train of pulses with frequency f2, is introduced to the adder (see Fig. 2), then, because of the loop's efforts to keep the error e(k) constant, 1 the frequency f¢ will be equal to fl +f2. This proves that it is possible, at least theoretically at this stage, to build a frequency adder (frequently named up converter) on the basis of a PLL. t Here we consider PLL of type 1 in which the steady state error e(k) depends on the VCO frequency.
0165-1684/86/$3.50 © 1986, Elsevier Science Publishers B.V. (North-Holland)
246
D. Wulich / PLL based frequency adder
_J--L_F-L Sampling
f~; el
Phase Detector
_~[J
e ~
Loop Filter toptlonal )
I~
m
VCO
~
C,OC
optional) b
Fig. 1. PLL as a feedback control system.
To realize the system of Fig. 2, it would be necessary to have a special phase detector which generates O j k ) + O 2 ( k ) - O J k ) . Such a phase detector does not exit. A usual phase detector compares the phases of two signals only.
rgl(k),fl ~'~e(k) I Loop ~ ) , t ¢ ~.d,]----! Filter
ez(k), fz "y'~
I(oPtiorml )
Fig. 2. Feedback control system with two inputs.
The main problem which should be solved is to generate a voltage which is proportional to 01(k) + 0 2 ( k ) - Ojk). A solution proposed here is based on the following. It is possible to use a phase detector to measure the difference O~(k) - Oc(k). If we do so, it remains to measure the absolute phase of frequency f2, i.e., 02(k); the value of phase 02(k) is converted to a physical value like that of e(k) (which is proportional to the difference O~(k)0c(k); see Fig. l(b)) and then added to e(k). 2 Such a solution only formally solves our problem, because the signal 02(k) represents a phase and therefore is a staircase signal which goes to infinity when the time increases. This problem is success2 e(k) may be current, voltage, or charge. Signal Processing
fully solved by resetting 02(k ) to zero every time the VCO makes one additional cycle as a response to the second input with frequency f2. Simultaneously with the reset command an extra pulse should be removed at Oc(k) input of the phase detector in order to keep the VCO control voltage equal to a constant value. Such a procedure is a theoretical basis of the fractional N technique, which is used, as mentioned above, for frequency synthesis [3, 4, 9] and for FM modulation of PLL from DC [2]. As will be clear later, the circuit used in order to realize the proposed method is not simple. But it has some advantages compared with a simple frequency adder, e.g., the mixer: (1) The proposed system addes two frequencies, while the mixer gives a sum and a difference of input frequencies. (2) The input signals can be of arbitrary shape; in the mixer, the input signals should be sine waves; if not, an intermodulation product appears at the mixer's output. (3) The level of the output signal does not depend on the input level, so if, for example, it is used for achieving the IF in an FM receiver, then there is no need for a limiter in the demodulator. The paper is organized as follows. A basic algorithm is presented in Section 2. In Section 3
D. Wulich/ PLL basedfrequency adder an analysis of the proposed system is given. Section 4 gives a computer simulation.
from (1), /3(k) represents the increment of the phase 02 (measured in 'cycles') during one period of the signal u~(t). It will be proved later that lim f l ( k ) = A / A ,
2. Basic algorithm
247
koc~
(2)
The block diagram of a PLL based frequency adder, which realizes the idea proposed in Section 1 is given in Fig. 3. Here we assume that f, >f2. The system is clocked by a pulse train with frequency f, (the sampling period is l/f,). Let us first explain the main blocks of Fig. 3.
i.e., fl(k) in steady state represents the ratio f2/f~. Suppose, at this stage, that the ratio f2/f, is known. In order to generate the absolute phase 02(k) it is necessary to integrate the value f2/f,, i.e., to generate a signal
2.1. Description of main blocks
which in fact is equal to the phase 02(k ). If we put T = 1/f,, we obtain 02(k)=f2kT. In a real system, the ratio f2/f, is computed 'on line'; therefore, the signal n(k) is computed according to
As was mentioned above, it is necessary to measure the absolute phase of the signal having the frequency f2. In order to do this, the above ratio is computed,
(1)
fl(k) a=Nk/k,
where Nk is the number of cycles of the signal u2(t) within k cycles of the signal ul(t). As follows
°l(k)'flu I U) --r,llSomp|inqoetecl~orPhase ~+~
t
n(k) = (AIA)k,
n(k)= n ( k - 1 ) + fl(k),
(3)
(4)
which leads to a transient at the VCO output as /3(k) only in infinity represents the value f21f,.
Filter
~n(k)=ez(R)
Pulse J ~emoverJ"
Carry V- Clock
----
~.tk~ [ Z" -' f_lFrequency ZlRofio u2(t) JComputot|on Fig. 3. Blockdiagram of the frequencyadder. Vol. 10, No. 3, April 1986
248
D. Wulich / PLL based frequency adder
As follows from (4), n ( k ) goes to infinity when k increases. To overcome this, the accumulator which generates n ( k ) (see (4)) is 'limited to 1', i.e., when n ( k ) > 1, the content of the accumulator is reduced by 1, a carry signal is produced which initiates a pulse remover command, and the counter then counts an extra period. This procedure keeps the VCO tuning voltage constant in the steady state, and keeps the values 02(k) and e ( k ) (see Fig. 3) within a dynamic range of the system. If an implementation of the accumulator (integrator) is digital, then the number of bits of the adder gives an additional restriction on the frequencies fl and f2, namely A = LT,/2",
where N is the number of bits and 1,2,...,2N-1.
From the above it follows that there is only one equilibrium point at which the phase error is fixed and the VCO frequency equals fl +f2. For better illustration, an example of waveforms n ( k T ) and e ( k T ) is given for f l = 1 0 and f 2 = 3 (see Fig. 4). 2.3. Transfer functions
The considered system is a sample data system and, consequently, the Z-transform technique is applied for analysis. There are two transfer functions related to the two inputs of the system (Fig. 2). The first is given by a 0¢(z) I O'(z) = o , - ~ o2~k~=o
(S) L=
(8a)
and the second by
O2(z)
a= O¢(z) O~(z) o,~k~=o
(8b)
2.2. Description o f the whole system
Suppose, for explanation only, that the frequency f~ =f~ +f2; therefore, the phase error is given by
In order to obtain explicit formulae for Gl(z) and G2(z) we observe after Lindsey and Chie [8] that the transfer function of VCO is given by
e( k ) = [ 2rtflk r + 0 ° - ( 2"rrf¢kT + O°)]kp = [-2~rf2kT+ O1o Oc]kp, o
Hvco(Z)-
kvco Tz- ' 1 - z -1 '
(9)
(6)
where kp is the phase detector gain; i.e., this phase error linearly decreases as a function of time (here discrete time). As already known [8], the sampling phase detector acts as a phase comparator (adder in Fig. l(b)) only when the phase difference is less than 2~r. The action of the pulse remover holds the phase difference within the interval [0, 2~r]. The signal e ( k ) is added to the voltage a n ( k ) , where a is some positive constant. The resulting signal e(t) is given as
where kvco is the gain of VCO. So, kpHvco( Z ) G1(z) = 1 + kpHvco(Z) kpkvcoTz -1 = 1 + z - l ( k p k v c o T - 1)
(10a)
and G2(z)=
Hvco(Z) 1 +kpHvco(Z)
e(k)=e(k)+an(k)
kvcoTz- 1 - 1 + z-X(kpkvcoT-I)"
= kp[-E~rf2kT+ 0 ° - 0 °] + ~ A k T = kp(O ° - 0°),
where a = 2~rkp. Signal Processing
(7)
(10h)
Eq. (10) will be useful in the next section for stability and convergence considerations.
D. Wulich / PLL based frequency adder
249
E(kt)
7/" C= ~TT
L•
-7~+C
I •
1__, L_~
.
I
kl
-71" C 4 7t" iarbltrory)
n(ktl 1.2
I.(3 O.8 Q6
Q4 0.2 0
?
I J
1 I
Pulse
I
I
I T /1
J
± I
ft~
kT
removing
Fig. 4. Example of n(kT) and e(kT).
3. System analysis
[5]. In our case the system is stable if'
(12)
0
3.1. Stability or
From (10), the characteristic equation of the system is given by
F(z)=z+(kL-1),
(11)
where KL = k p k v c o T is the normalized loop gain. A sampled data system is stable if all roots of the characteristic equation are within the unit circle
f l >~kpkvco '
for kp>0.
(13)
This condition gives a restriction on the frequency f~. If a loop filter is used, (13) is not true; however, it represents an 'upper bound' of a specific restriction which depends on the loop filter transfer function. Vol. 10, No. 3, April 1986
D. Wulicb / PLL based frequency adder
250
3.2. Convergence time
or
A convergence time is defined here as a time in which the VCO reaches the steady state frequency within specified error band. The convergence time depends on the following factors: loop constant kL, initial frequency of the VCO, fo, and the ratio f2/fl which determines the convergence of/3(k), i.e., the convergence time depends both on the loop parameters and on the external quantities,
fo, f,,f2. First we analyze the convergence time assuming that /3(k)=f2/fl=constant. m(k) can be calculated from Ol(k) and 02(k) by the Z-transform
M(z)=
k p ( 1 - z - i ) Ol(Z) l + ( k r - 1 ) z -1 (14)
For the initial VCO frequencyfo, the instantaneous frequency as a function of discrete time is obtained by using the inverse Z-transform of (14) when Ol(k) = k and 02(k) =f2Tk, fi,,~t(k) = kvcom(k) (fl +f2 - f o ) [
1 - (1 -
k=0, 1,2,....
~< l/k,
kL)k] +fo (15)
(17)
which proves (2). Now, our efforts will be concentrated on translating (17) into the settling time of the VCO frequency assuming that the loop convergence equals one period off1. From the considerations of Section 2 and the basic principle of fractional N technique [4] it follows that, under the steady state loop condition, the resulting VCO frequency is given as
fc=fl + /3(k)fv
(18)
From (17) and (18), the VCO frequency deviation Af¢(k) is therefore bounded by
Aft(k) a=l Y e - f , -f2l <~fl/k.
(1 - z -l) 4 1 + (kL-- 1)Z-' 02(z).
=
I/3(k) - f U f d
(19)
From (19), the settling time is easily obtained. It should be pointed out here that the result obtained is not general and depends on the/3(k) computation method. But, with no connection with a specific method of/3 (k) computation, the convergence of/3(k) depends on the value off2 and is equivalent to the time needed to measure the frequency f2. Therefore, the convergence of/3(k) (especially for low f2) is a dominant part of the whole convergence process. This means that the loop gain kL should be chosen to guarantee the loop stability only according to (13).
Here we assume that the initial phase difference
~(0) =0.
3.3. Jitter
From (15) for any specific fo, kL and a given frequency accuracy the convergence time can be found. It is very interesting to observe that, for kL = 1,f,st(k) =f~ +f2 (k = 1, 2, 3 , . . . ) and does not depend onfo. So, at least theoretically, it is possible to obtain a loop convergence equal to one period of ft. Now, let us analyze the convergence of/3(k). From the definition of Nk it follows that Nk = [kf2/fl] or Nk = [kf2/fl] + 1, where [. ] denotes real to integer truncation. From the above, the following inequalities are obtained:
There are no theoretical reasons for jitter in steady state. However, in a practical system there will appear some jitter which is a 'superposition' of a variety of factors connected with specific hardware implementation and working frequencies. Here we consider only one, which appears as a direct consequence of the fractional N procedure. The second input, 02(k) (see Fig. 2), is introduced to the loop via a summing node (Fig, 3), 3 which in practice is implemented with some finite accuracy. Let us analyze the influence of the 3 The q u a n t i t i e s w h i c h are s u m m e d m a y be voltages, cur-
k f U f , - 1 ~ N~ <~ k f U f l + 1 Signal Processing
(16)
rents, or charges.
D. Wulich/ PLL basedfrequency adder given as
summer accuracy on the jitter. For this, we suppose that the nonaccuracy will be represented by periodic signal y(k) (Fig. 3) having a frequency o f f , =fl/n, where n is the minimal numerator of the rational number fl/f2, and the amplitude depends on the accuracy of the summing node. The shape of the signal y(k) is very difficult to predict and depends on many features, so that in the worst case we may assume that
y(k) = A~ cos(2rrf, Tk),
Arc = IH~ (f.)lAr.
The proposed method was simulated on a digital computer. The results obtained are presented in Fig. 5, in which the normalized deviation of instantaneous frequency from the required (in %) as a function of time (represented here by k, number of periods fl) is given. The initial frequency of the VCO is chosen to be equal to fl, and the normalized loop gain kL=0.16. As can be seen from Fig. 5, the output frequency fl+f2 has a jitter which decreases with time (as was explained in Section 3.3 ), according to the convergence of/3 (k) to f2/fv It is observed that for f2/fl =0.01 or 0.1, in our example, the instantaneous frequency is greater than the final frequency and decreases towards f~ +f2 in spite of the fact that the initial frequency is f~ and the loop is overdamped (kL=0.16), i.e., the convergence should be monotonically increased from f~ up tof~ +f2 (see (15) for kL< 1).
where Ar represents the accuracy of summing. As we shall see later, this approximation leads to the upper bound of the VCO frequency deviation. The transfer function relating y(k) to the VCO frequency fc is given as
(21)
and the frequency response is therefore given as [ 1]
U~(z)lz-v=,,,.
H~(f) =
(22)
The upper bound of the VCO frequency deviation Arc caused by nonaccurate summing node is ~ ~
5
I
I
I
= I 40
I 60
I 80
(22a)
4. Computer simulated results
(20)
k v c o ( 1 - z 1)
251
I
I
I
I
I
I 140
I 160
I 180
4"
3"
~
z.
Z
I'
0 p,~ 0
~-Z ~ -4, i
q 20
I
I00
I 120
200 k/f D
TIME
Fig. 5. Normalized deviation of resulting frequency from the required as a function of time. Vol. 10, No. 3, April 1986
252
D. Wulich / PLL based frequency adder
The explanation of this behaviour is based on the fact that fl(k) in the first stage of its convergence can achieve much greater values than required, particularly for small f2/fl. For example, forf2/f~ = 0.1, we have/3(1) = 1,/3(2) =0.5, and/3(3) =].
5. Summary The PLL frequency adder based on the fractional N technique is described. The proposed system adds two frequencies, fl and f:. f~ must be greater than f2 and f~/f2 must be a rational number. The system can be divided into two functional parts: (1) the PLL with the fractional N procedure, and (2) the block which computes the ratio f2/fl. It is proved that in the steady state condition there are no theoretical reasons for any jitter of the output frequency, The convergence time, which is combined from convergence time of PLL and convergence time of fl(k), practically depends on the convergence of/3(k). The proposed method may be effectively implemented by inexpensive digital logic or on a micro-
Signal Processing
processor when the input frequencies are not too high. This method may be extended to frequency subtraction.
References [1] S.M. Bozic, Digital and Kalman filtering, Arnold, Paris, 1979. [2] M. Da Silva, "Synthesis of FM signals", RF Design, September/October 1984, pp. 29-38. [3] J. Gorski-Popiel, Frequency Synthesis: Techniques and Applications, IEEE Press, 1975. [4] K. Jessen, "Fractional-N simplifies frequency synthesis", Bench Briefs, Service Information from Hewlett-Packard, May-August 1977. [5] E.I. Jury, Theory and Application of the Z-Transform Method, Wiley, New York, 1964. [6] B. Kuo, Automatic Control Systems, Prentice-Hall, Englewood Cliffs, NJ, 1975. [7] W. Lindsey and M.K. Simon, Phase Locked Loops and Their Application, IEEE Press, 1978. [8] W.C. Lindsey and C.N. Chic, "A survey of digital phaselocked loops", Proc. IEEE, Vol. 69, No. 4, April 1981, pp. 410-431. [9] U.I. Rodhe, Digital PLL Frequency Synthesis, Theory and Design, Prentice-Hall, Englewood Cliffs, NJ, 1983.