Realization of deep-submicron MOSFETS by lateral etching

Microelectronic Engineering ]3 (1991) 473-476 Elsevier

REALIZATION

OF

R. Burmester,

473

DEEP-SUBMICRON

J. Winnerl,

MOSFETS

BY

LATERAL

ETCHING

F. Neppl

Siemens AG C o r p o r a t e Research and Development O t t o - H a h n - R i n g 6, D-8000 M~nchen 83, G e r m a n y A lateral etching technique is presented that allows the reproducible realization of 0.2 ~m lines with a standard 1.0 ~m g-line stepper lithography. The lateral etching was applied to the submicron device development. MOSFETs with quarter-micron gate lengths were s u c c e s s f u l l y fabricated with standard lithography. A further application is to boost p e r f o r m a n c e of an existing t e c h n o l o g y by reducing the gate length without increasing the lithography requirements. i.

INTRODUCTION

The m i n i m u m feature sizes for CMOS technologies in the 64M-DRAM generation will be s 0.4 ~m [i]. These processes require high resolution l i t h o g r a p h y techniques like d e e p - U V or X-ray. A lateral etching technique has been developed that allows the reproducible patterning of p o l y s i l i c o n gates down to 0.2 ~m with a standard 1.0 ~m g-line stepper lithography. This method enables the realization of MOSFETs with deep submicron gate lengths prior to the a v a i l a b i l i t y of high resolution exposure techniques. 2.

PROCESS

FLOW

The lateral etching technique was integrated in a 0.5 ~m CMOS technology. The specific process steps for gate p a t t e r n i n g are illustrated in Fig. i. After growing a gate oxide of i0 nm, polysilicon with a thickness of 300 nm was d e p o s i t e d and phosphorus doped. For the lateral etching process an a u x i l i a r y layer is necessary which can be etched selectively with respect to the polysilicon b e n e a t h and to the photoresist on top of it. An LPCVD oxide with a thickness of 150 nm offers a sufficient etch selectivity and was used throughout the experiments reported here. The resist was exposed with a standard g-line CANON 5:1 stepper with a numerical aperture of 0.43. In a first anisotropic dry etching step the LPCVD oxide layer was p a t t e r n e d with the resist mask. S u b s e q u e n t l y the oxide was laterally etched in an HF solution reducing the linewidth with respect to the resist mask. After stripping the photoresist, the polysilicon was patterned with the LPCVD oxide mask using a standard etch process. Fig. 1 shows a 0.2 ~m wide polysilicon line o r i g i n a l l y exposed to 1.0 ~m. Compared to a standard CMOS t e c h n o l o g y the only additional process steps are the deposition and etching of the auxiliary layer and the lateral etching step. For w o r d l i n e e n c a p s u l a t i o n in DRAM t e c h n o l o g i e s an oxide cap on top of the p o l y s i l i c o n gate is often used [2]. Then only the lateral etching step has to be added. 0167-9317/91/$3.50 © 1991 - Elsevier Science Publishers B.V.

R. Burmester et al. / Realization of deep-submicron MOSFETs

474

Polysilicon deposition Auxiliary oxide layer Resist patterning Resist Auxiliary oxide layer Polysilicon

__~ Anisotropic oxide etching

Lateral oxide etching

Resist stripping

I_

,l Polysilicon etching

Process

3. 3.1.

flow

EXPERIMENTAL Polysilicon

FIGURE 1 for gate p a t t e r n i n g with

lateral

etching.

RESULTS Gate

Patterning

The lateral e t c h i n g process was found to be c o n t r o l l a b l e and reproducible. The l i n e w i d t h r e d u c t i o n can e a s i l y be c o n t r o l l e d by the HF etch time. The linear d e p e n d e n c e in Fig. 2 holds over a wide range and is i n d e p e n d e n t of the original line width and pitch. The overall gate length u n i f o r m i t y in several b a t c h e s was better than ± 50 nm. In order to e v a l u a t e the i n f l u e n c e of the lateral etching process on g a t e l e n g t h uniformity, part of the wafers of one b a t c h w e r e p r o c e s s e d with the lateral e t c h i n g process w h i l e the r e m a i n i n g wafers were patterned conventionally without the a u x i l i a r y oxide layer. A c o m p a r i s o n of the electrically m e a s u r e d gate lengths (mean value and s t a n d a r d deviation) for the w a f e r s of the d i f f e r e n t groups does not show a de-

475

R. Bunnester et al. / Realization of deep-submicron MOSFETs

gradation of the linewidth scattering (Fig. 3). Deep submicron polysilicon gates patterned with the lateral etching process proved to be homogeneous in linewidth. They did not show the typical line width narrowing near topology steps caused by defocus and reflection problems during exposure of narrow lines with a standard 1.0 ~m lithography (Fig. 4).

1(11i8newidthreductionAI [pm ]

0.6

tttt t

i Deviation from designed linewidth [pm] 0.1

Originalfinew i d t h : [] I=l.01Jm x 1:0:7 um

J

o

-0.1

0.4

-0.2

0.2 -0,3

o

2

-04 I

,~

Wafers without ,~aleral etching

Etching time [ min ]

Wafers with lateral etching/

Y Exposed m one batch

FIGURE

2

Calibration function of linewidth reduction vs. lateral etching time.

FIGURE 3 Comparison of the linewidth scattering with and without the lateral etching process.

i

J FIGURE

4a

FIGURE

standard lithography

4b

lateral etching FIGURE

4

Improvement of the linewidth narrowing at topology steps by the lateral etching process. 3.2. Application examples The lateral etching process was applied to the fabrication of deep submicron MOSFETs using a standard 1.0 ~m g-line lithography. Fig. 5 shows the SEM cross section and the output characteristics of an n-channel MOSFET with 0.25 ~m gate length and i0 nm gate oxide thickness.

R. Bunnester et al. / Realization of deep-submicron MOSFETs

476

I

ID

mA

tox = 1Ohm L G = 0.25p.m W =2 0

VGS • 4 V n

m

~

~0

Y n

i

i

1

2

3 VOS

SEM cross

section

FIGURE 5 and output characteristics n-channel MOSFET.

0

V =.

of a 0.25 ~m

The lateral etching process enables the device d e v e l o p m e n t for CMOS technologies in 64M-DRAM generation and beyond prior to the availability of high resolution lithography techniques. The excellent reproducibility makes the lateral mask reduction process not only attractive for the fabrication of test samples. In an existing t e c h n o l o g y this method can be utilized to boost performance by reducing transistor channel length without increasing l i t h o g r a p h y requirements.

4.

CONCLUSIONS

A lateral etching technique was developed that allows the controllable and reproducible patterning of submicron lines with a standard 1.0 ~m g-line stepper lithography. This process was implemented in a CMOS technology for gate p a t t e r n i n g and provides a linewidth h o m o g e n i o u t y of ± 50 nm for several batches. The lateral etching process was sucessfully applied to the fabrication of MOSFETs with 0.25 ~m gatelength. Besides the development of submicron devices this technique has the potential to boost performance of an existing t e c h n o l o g y by reducing the gate length without increasing lithography requirements. ACKNOWLEDGEMENTS The authors would like to thank S. Schmid and C. Schmid for their assistance in f o t o l i t h o g r a p h y and lateral etching and E. Voit for the p r e p a r a t i o n of the SEM pictures. REFERENCES [i] [2]

L. Risch et. al., SSDM 90 extended abstracts, 837 (1990). K.H. K~sters et. al., ECS spring m e e t i n g extended abstracts, vol. 87-1, 289 (1987).