- Email: [email protected]
Signal processor controlled USB2.0 interface for Medipix2 detector
ARTICLE IN PRESS
Nuclear Instruments and Methods in Physics Research A 591 (2008) 245–247 www.elsevier.com/locate/nima
Signal processor controlled USB2.0 interface for Medipix2 detector Michal Platkevic, Viktor Bocarov, Jan Jakubek, Stanislav Pospisil, Vladimir Tichy, Zdenek Vykydal Institute of Experimental and Applied Physics, Czech Technical University in Prague, Horska 3a/22, CZ-12800 Prague 2, Czech Republic Available online 25 March 2008
Abstract We developed the new USB2.0 based read-out signal processor controlled interface for the Medipix family of detectors. This interface uses the advantages of the USB2.0 standard, is controlled by signal processor providing high performance and flexibility and is able to read-out data as fast as Medipix can generate.1 All signals go thru the FPGA (Field Programmable Gate Array) giving possibility to implement new functionality easily by reprogramming the FPGA without need to change hardware. This interface is compatible with all versions of Medipix chips (Medipix2, Medipix MXR, Timepix) including future chips (Medipix3). r 2008 Elsevier B.V. All rights reserved. PACS: 07.50.Qx; 07.85.Fv; 07.05.Hd; 07.05.Wr; 87.59.Bh Keywords: Medipix; Timepix; USB interface; Signal processor
1. Introduction State-of-the-art digital detecting systems of the Medipix family [1] are available and make possible real time imaging with high sensitivity and broad dynamic range. Nowadays, for the hybrid silicon pixel detector device Medipix2 [2] the acquisition control and data read-out can be realized via devoted interface MUROS2 [3] or USB1.0 interface [4]. MUROS2 (Medipix2 re-Usable Read Out System version 2) is the FPGA (Field Programmable Gate Array) based device as a bridge between Medipix2 chipboard and a universal data acquisition card (National Instruments DIO-653X) for the PCI computer slot. This interface requires external power supplies and detector bias. Due to large dimensions of these external devices and limited lengths of cables the applicability of detectors with this interface is limited. The USB1.0 interface significantly extends the applicability of the Medipix2 device and makes it more portable.
However, the total frame rate is limited to 5 frames per second. The proposed second-generation USB2.0 interface [5] removes these limitations and provides enhanced operability. 2. The new Medipix interface To make the Medipix2 detector more efficient we developed a read-out system using the advantages of the USB2.0 interface [6]—transfer rate of 480 Mb/s and simplicity of usage. The Medipix serial output is used. Data are de-serialized in devoted circuitry and taken by processor. The new interface is controlled by digital signal processor (DSP) providing high level of flexibility and high performance for online data processing. The interface is equipped with large memory allowing stand alone operation. 2.1. Data de-serialization
Corresponding author. Tel.: +420 224 359 396; fax: +420 224 359 392. 1
E-mail address: [email protected] (M. Platkevic). This is also true for the parallel readout option of Medipix (100 MHz).
0168-9002/$ - see front matter r 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2008.03.065
Serial data from Medipix are not loaded directly to the signal processor but are first de-serialized (see Fig. 1).
ARTICLE IN PRESS M. Platkevic et al. / Nuclear Instruments and Methods in Physics Research A 591 (2008) 245–247
246
Fig. 1. Principle of data de-serialization. Fig. 2. Usage of fast shift registers with multichip assembly.
Principle of data de-serialization: The FPGA provides the following features:
The serial data are shifted to fast shift registers at high frequency generated by PLL.2 When the registers are filled up, the parallel data are loaded to the latch. DSP reads the data from the latch via the data bus at lower frequency.
realization of all digital logic between DSP and Medipix; configurable input/output pins (LVDS4, CMOS); speed—440 MHz; flexibility—possibility to change functionality without need of hardware modification; compact size (14 14 mm2).
Individual chips of the multichip assembly (Medipix Quad [1]) can be read out simultaneously (the 32-bit fast shift register can be divided into four parallel 8-bit segments). Each segment can be fed from a separate Medipix chip (see Fig. 2).
2.3. Prototype The prototype for this interface was realized with DSP TMS320C6455 and FPGA Lattice XP starter kits (see Fig. 4).
2.2. Hardware design
3. Conclusions and future work
The interface board (Fig. 3) consists of two main components: a digital signal processor TMS320C6455 [7] and a FPGA Lattice XP [8]. The digital signal processor provides the following features:
We have designed a new interface for the Medipix family of detectors. The main advantages provided are:
high data throughput; high computational performance (up to 8000 mips3) including sophisticated data processing (threshold equalization, flat field correction, beam hardening correction, cluster analysis, etc.); built in management of large memory; built in 10/100/1000 Mb/s Ethernet MAC.
2 3
PLL stands for Phase-Locked Loop. Mips stands for Million instructions per second.
High data throughput—the new interface is able to read-out the data as fast as Medipix can provide them. Flexibility—all signals between the signal processor and Medipix go thru the FPGA so there is possibility to implement new functionality easily by reprogramming the FPGA without need to change hardware. Compatibility—the new interface is compatible with all versions of the Medipix chips (Medipix2, Medipix MXR, Timepix [9]) and is prepared for future chips (Medipix3 [10]).
4
LVDS stands for Low Voltage Differential Signaling.
ARTICLE IN PRESS M. Platkevic et al. / Nuclear Instruments and Methods in Physics Research A 591 (2008) 245–247
247
Fig. 3. Block diagram of the interface board.
Research Grant Collaboration of Czech Republic with CERN No. 1P04LA211, by the Fundamental Research Center Project LC06041, by Grant MSMT No. 05-61308 and the Research Programs 210000018 and 6840770040 of the Ministry of Education, Youth and Sports of the Czech Republic.
References
Fig. 4. Prototype realized with starter kits.
Efficiency—sophisticated data processing can be done in the signal processor thus the PC can receive processed final images.
A functional prototype has been assembled and tested. At present we are designing the final PCB5 and developing the firmware. Acknowledgments This work has been carried out in frame of the CERN Medipix Collaboration and has been supported in part by the 5
Printed circuit board.
[1] Medipix Collaboration, /http://www.cern.ch/medipixS and /http:// www.utef.cvut.cz/medipixS. [2] X. Llopart, M. Campbell, R. Dinapoli, D. San Segundo, E. Pernigotti, IEEE Trans. Nucl. Sci. NS49 (2001) 2279. [3] D. San Segundo Bello, M. Van Beuzekom, P. Jansweijer, H. Verkooijen, J. Visschers, Nucl. Instr. and Meth. A 509 (2003) 164. [4] Z. Vykydal, J. Jakubek, S. Pospisil, Nucl. Instr. and Meth. Phys. Res. A 563 (2006) 112. [5] M. Platkevic, Signal processor controlled USB2.0 interface for Medipix2 detector, Diploma Thesis, CTU in Prague, 2007. [6] Universal Serial Bus specification at: /http://www.usb.orgS. [7] TMS320C6455-Fixed-Point Digital Signal Processor datasheet at: /http://focus.ti.comS. [8] LatticeXP Family datasheet at: /http://www.latticesemi.comS. [9] X. Llopart, R. Ballabriga, M. Campbell, L. Tlustos, W. Wong, Nucl. Instr. and Meth. A 581 (1–2) (2007) 485. [10] R. Ballabriga, M. Campbell, E.H.M. Heijne, X. Llopart, L. Tlustos, The Medipix3 Prototype, a Pixel Readout Chip Working in Single Photon Counting Mode with Improved Spectrometric Performance, in: Conference Record of Nuclear Science Symposium IEEE 2006 San Diego, 2006.
Nuclear Instruments and Methods in Physics Research A 591 (2008) 245–247 www.elsevier.com/locate/nima
Signal processor controlled USB2.0 interface for Medipix2 detector Michal Platkevic, Viktor Bocarov, Jan Jakubek, Stanislav Pospisil, Vladimir Tichy, Zdenek Vykydal Institute of Experimental and Applied Physics, Czech Technical University in Prague, Horska 3a/22, CZ-12800 Prague 2, Czech Republic Available online 25 March 2008
Abstract We developed the new USB2.0 based read-out signal processor controlled interface for the Medipix family of detectors. This interface uses the advantages of the USB2.0 standard, is controlled by signal processor providing high performance and flexibility and is able to read-out data as fast as Medipix can generate.1 All signals go thru the FPGA (Field Programmable Gate Array) giving possibility to implement new functionality easily by reprogramming the FPGA without need to change hardware. This interface is compatible with all versions of Medipix chips (Medipix2, Medipix MXR, Timepix) including future chips (Medipix3). r 2008 Elsevier B.V. All rights reserved. PACS: 07.50.Qx; 07.85.Fv; 07.05.Hd; 07.05.Wr; 87.59.Bh Keywords: Medipix; Timepix; USB interface; Signal processor
1. Introduction State-of-the-art digital detecting systems of the Medipix family [1] are available and make possible real time imaging with high sensitivity and broad dynamic range. Nowadays, for the hybrid silicon pixel detector device Medipix2 [2] the acquisition control and data read-out can be realized via devoted interface MUROS2 [3] or USB1.0 interface [4]. MUROS2 (Medipix2 re-Usable Read Out System version 2) is the FPGA (Field Programmable Gate Array) based device as a bridge between Medipix2 chipboard and a universal data acquisition card (National Instruments DIO-653X) for the PCI computer slot. This interface requires external power supplies and detector bias. Due to large dimensions of these external devices and limited lengths of cables the applicability of detectors with this interface is limited. The USB1.0 interface significantly extends the applicability of the Medipix2 device and makes it more portable.
However, the total frame rate is limited to 5 frames per second. The proposed second-generation USB2.0 interface [5] removes these limitations and provides enhanced operability. 2. The new Medipix interface To make the Medipix2 detector more efficient we developed a read-out system using the advantages of the USB2.0 interface [6]—transfer rate of 480 Mb/s and simplicity of usage. The Medipix serial output is used. Data are de-serialized in devoted circuitry and taken by processor. The new interface is controlled by digital signal processor (DSP) providing high level of flexibility and high performance for online data processing. The interface is equipped with large memory allowing stand alone operation. 2.1. Data de-serialization
Corresponding author. Tel.: +420 224 359 396; fax: +420 224 359 392. 1
E-mail address: [email protected] (M. Platkevic). This is also true for the parallel readout option of Medipix (100 MHz).
0168-9002/$ - see front matter r 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2008.03.065
Serial data from Medipix are not loaded directly to the signal processor but are first de-serialized (see Fig. 1).
ARTICLE IN PRESS M. Platkevic et al. / Nuclear Instruments and Methods in Physics Research A 591 (2008) 245–247
246
Fig. 1. Principle of data de-serialization. Fig. 2. Usage of fast shift registers with multichip assembly.
Principle of data de-serialization: The FPGA provides the following features:
The serial data are shifted to fast shift registers at high frequency generated by PLL.2 When the registers are filled up, the parallel data are loaded to the latch. DSP reads the data from the latch via the data bus at lower frequency.
realization of all digital logic between DSP and Medipix; configurable input/output pins (LVDS4, CMOS); speed—440 MHz; flexibility—possibility to change functionality without need of hardware modification; compact size (14 14 mm2).
Individual chips of the multichip assembly (Medipix Quad [1]) can be read out simultaneously (the 32-bit fast shift register can be divided into four parallel 8-bit segments). Each segment can be fed from a separate Medipix chip (see Fig. 2).
2.3. Prototype The prototype for this interface was realized with DSP TMS320C6455 and FPGA Lattice XP starter kits (see Fig. 4).
2.2. Hardware design
3. Conclusions and future work
The interface board (Fig. 3) consists of two main components: a digital signal processor TMS320C6455 [7] and a FPGA Lattice XP [8]. The digital signal processor provides the following features:
We have designed a new interface for the Medipix family of detectors. The main advantages provided are:
high data throughput; high computational performance (up to 8000 mips3) including sophisticated data processing (threshold equalization, flat field correction, beam hardening correction, cluster analysis, etc.); built in management of large memory; built in 10/100/1000 Mb/s Ethernet MAC.
2 3
PLL stands for Phase-Locked Loop. Mips stands for Million instructions per second.
High data throughput—the new interface is able to read-out the data as fast as Medipix can provide them. Flexibility—all signals between the signal processor and Medipix go thru the FPGA so there is possibility to implement new functionality easily by reprogramming the FPGA without need to change hardware. Compatibility—the new interface is compatible with all versions of the Medipix chips (Medipix2, Medipix MXR, Timepix [9]) and is prepared for future chips (Medipix3 [10]).
4
LVDS stands for Low Voltage Differential Signaling.
ARTICLE IN PRESS M. Platkevic et al. / Nuclear Instruments and Methods in Physics Research A 591 (2008) 245–247
247
Fig. 3. Block diagram of the interface board.
Research Grant Collaboration of Czech Republic with CERN No. 1P04LA211, by the Fundamental Research Center Project LC06041, by Grant MSMT No. 05-61308 and the Research Programs 210000018 and 6840770040 of the Ministry of Education, Youth and Sports of the Czech Republic.
References
Fig. 4. Prototype realized with starter kits.
Efficiency—sophisticated data processing can be done in the signal processor thus the PC can receive processed final images.
A functional prototype has been assembled and tested. At present we are designing the final PCB5 and developing the firmware. Acknowledgments This work has been carried out in frame of the CERN Medipix Collaboration and has been supported in part by the 5
Printed circuit board.
[1] Medipix Collaboration, /http://www.cern.ch/medipixS and /http:// www.utef.cvut.cz/medipixS. [2] X. Llopart, M. Campbell, R. Dinapoli, D. San Segundo, E. Pernigotti, IEEE Trans. Nucl. Sci. NS49 (2001) 2279. [3] D. San Segundo Bello, M. Van Beuzekom, P. Jansweijer, H. Verkooijen, J. Visschers, Nucl. Instr. and Meth. A 509 (2003) 164. [4] Z. Vykydal, J. Jakubek, S. Pospisil, Nucl. Instr. and Meth. Phys. Res. A 563 (2006) 112. [5] M. Platkevic, Signal processor controlled USB2.0 interface for Medipix2 detector, Diploma Thesis, CTU in Prague, 2007. [6] Universal Serial Bus specification at: /http://www.usb.orgS. [7] TMS320C6455-Fixed-Point Digital Signal Processor datasheet at: /http://focus.ti.comS. [8] LatticeXP Family datasheet at: /http://www.latticesemi.comS. [9] X. Llopart, R. Ballabriga, M. Campbell, L. Tlustos, W. Wong, Nucl. Instr. and Meth. A 581 (1–2) (2007) 485. [10] R. Ballabriga, M. Campbell, E.H.M. Heijne, X. Llopart, L. Tlustos, The Medipix3 Prototype, a Pixel Readout Chip Working in Single Photon Counting Mode with Improved Spectrometric Performance, in: Conference Record of Nuclear Science Symposium IEEE 2006 San Diego, 2006.