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Thin-film polysilicon solar cells on foreign substrates using direct thermal CVD: material and solar cell design
Thin Solid Films 403 – 404 (2002) 229–237
Thin-film polysilicon solar cells on foreign substrates using direct thermal CVD: material and solar cell design G. Beaucarnea,*, S. Bourdaisb, A. Slaouib, J. Poortmansa a
IMEC vzw., Kapeldreef 75, B-3001 Leuven, Belgium CNRS-PHASE, 23 rue du Loess, F-67037 Strasbourg, France
b
Abstract The method to reach low-cost thin-film solar cells studied here involves the deposition of a thin layer of crystalline Si directly on cheap foreign substrates with CVD at high temperatures. Our investigation deals with controlling physical phenomena such as nucleation, layer growth and dopant diffusion to achieve specific properties enabling better performance, effectively designing both the polysilicon material and the device structure. The required grain size is obtained by depositing small isolated crystallites with the right surface density on the substrate and subsequently growing a closed layer from these nuclei. To reduce recombination velocity at grain boundaries the effect of the growth rate and post-deposition treatments are investigated. The high second diode current that usually plagues such devices can be reduced by improving the material quality and optimising the base doping level. We introduce the TREBLE concept in which carrier collection relies on the presence of deep peaks of preferential doping at grain boundaries. 䊚 2002 Elsevier Science B.V. All rights reserved. Keywords: Polycrystalline silicon; Thin film Si; Foreign substrate; CVD; Solar cell; Grain boundary
1. Introduction Many in the photovoltaic industry regard thin layers of crystalline Si on low cost substrate as a promising alternative to standard bulk Si wafers. No approach among the various methods of producing such layers has yet emerged as the ultimate solution. As a result, a broad range of techniques and approaches are being investigated. Recently, techniques involving the transfer of a thin layer of monocrystalline Si onto a cheap substrate have received a lot of attention. Thanks to the good material quality of the active layer, it is expected that high efficiencies will be reached relatively easily with such procedures. A conversion efficiency of 15.3% has already been reported w1x. All other approaches to thin film crystalline Si solar cells involve a deposition process, sometimes combined with a crystallisation proc* Corresponding author. University of New South Wales, Centre for Third-Generation Photovoltaics, Sydney, New South Wales, Australia; Tel.: q61-2-9385-4054; fax: q61-2-9385-5412. E-mail address: [email protected] (G. Beaucarne).
ess. A convenient way of giving an overview is to classify the approaches according to the highest temperature of the whole process sequence, which is usually the deposition temperature. At the lower end of the spectrum, there is the work done on nano- or microcrystalline Si on glass, which is deposited by plasmaenhanced chemical vapour deposition (PECVD) at a temperature in the order of 2008C. Considering the low temperatures involved, very good efficiencies ()7%) have been reached. Increasing the temperature (up to 6508C), one finds a variety of techniques that still allow the use of glass and often involve some kind of low temperature crystallisation (solid phase crystallisation or metal-induced crystallisation). Increasing the temperature higher into the range 700–13008C imposes the choice of another type of substrate, typically made of a ceramic material. These techniques, which have been much less intensely investigated than others, involve the direct deposition of the silicon layer with solution growth w2x or chemical vapour deposition (CVD) w3x. The research described in this paper is relevant to one of these intermediate techniques, namely the CVD route.
0040-6090/02/$ - see front matter 䊚 2002 Elsevier Science B.V. All rights reserved. PII: S 0 0 4 0 - 6 0 9 0 Ž 0 1 . 0 1 5 5 9 - 0
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Finally, some processes require temperatures above the Si melting point. By locally melting a Si layer and scanning the molten zone over the whole wafer (zone melting recrystallisation), it has been shown that it is possible to produce a Si layer with large grains ()1 mm width), and high efficiency solar cells have been made. 2. Thin film Si solar cells using direct CVD As mentioned above, this paper deals with the direct deposition of a Si layer with thermal CVD on foreign substrates. The substrate is brought to a high temperature (typically 11008C); a silicon precursor (e.g. SiHCl3) is introduced in the reactor; and through a complex sequence of gas phase and surface processes, a layer of crystalline Si is deposited. CVD is widely used in microelectronics to grow thin epitaxial layers because it allows excellent dopant concentration and layer thickness control. It is not a new idea to use CVD on potentially cheap foreign substrates for photovoltaics; experiments were done on this topic as early as 1977 w4x. However, the authors believe that the potential of this approach has not been sufficiently explored before. One of the reasons for this is that preliminary experiments tend to give discouraging results. If a CVD process is applied on an arbitrary foreign substrate, a layer with very small grains will be formed, with grains in the order of 1 mm, which implies a large density of defects. Simply applying a standard bulk Si solar cell process on non-optimised layers will yield devices with low efficiency, in the order of 2% and below. This is an order of magnitude lower than what can be achieved with bulk crystalline Si. The gap is so large that many consider it pointless to investigate it further. The approach we have followed has been to first to study in detail the factors that determine device performance, using simple low efficiency cells. This analysis has allowed us to identify the areas on which research should focus to improve devices. It turns out that progress is required both on the level of active layer material improvement and on the level of device structure. Therefore research has evolved from a situation in which the active layer material and the process were regarded as fixed parameters to a situation where they have to be designed for our specific application. This design of both solar cell material and cell structure is the topic of this paper. In Section 3, we briefly discuss the performance limiting factors of fine-grained CVD polysilicon cells. In Section 4, the potential for material improvement through control of the deposition process and post-deposition treatment is treated and our experimental results are shown and discussed. Section 5 deals with the choice of the most appropriate device design. We introduce the concept of the ThRee-dimensional
Emitter Based on Locally Enhanced diffusion (TREBLE) cell and discuss its practical implementation. 3. Performance limiting factors Simple experiments consisting of a non-optimised deposition followed by a process designed for bulk Si solar cell produce cells with very low efficiencies. However, a clear trend is difficult to find. Whereas some devices display considerable short circuit current densities, but open circuit voltages below 200 mV, others combine respectable voltages and fill factors with very small Jsc values. Our first endeavour in this research was therefore to understand what precisely determines device performance. The devices we studied were obtained with CVD polysilicon layers deposited at high temperature on oxidised Si wafers from a chlorinated precursor and with a one-side contacted solar cell process involving emitter formation through P-diffusion. In order to be able to draw conclusions, the experiments were carried out varying only one parameter at a time. 3.1. Shunting In experiments with fine-grained polysilicon solar cells, large shunt currents are sometimes observed. The results suggest that the leakage currents are caused by some process involving carrier hopping between the conduction band on the n-side and the valence band on the p-side via states in the bandgap w5x. While diode leakage can occasionally be a problem in this type of cells, we have repeatedly found in our experimental work that it is possible to obtain a sufficiently high shunt resistance by choosing deposition conditions that ensure sufficient material quality andyor by applying a hydrogenation treatment. We even achieved large area low leakage p–n junction diodes in a polysilicon layer with an average grain size as low as 0.5 mm and a ptype doping level of 5=1017 cmy3 w6x. Diode leakage is therefore not a fundamental barrier towards the development of efficient thin film fine-grained Si solar cells. 3.2. Carrier collection Thin film Si solar cells could in principle yield current densities almost as high as bulk solar cells, thanks to light confinement. However, a prerequisite is that the zone of carrier collection extends over the whole Si layer, or in other words the effective diffusion length should be at least as large as the layer thickness. In experiments on thin film Si solar cells produced in the same temperature range, this requirement has never been fulfilled w4,7,8x. In a recent paper, we gave a detailed analysis of carrier collection in this type of cell w9x. Based on a large number of experiments, two important conclusions could be drawn. The first one is that
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Fig. 1. Schematic representation of the doping profile and the collection probability in a CVD polysilicon cell with preferential doping.
recombination velocity at grain boundaries in high temperature CVD polysilicon is very large (430 000 cmys) in our material grown in standard conditions and subjected to a standard hydrogenation treatment. A second conclusion was that, in cells with diffused emitter, the phenomenon of preferential doping (enhanced diffusion of dopants along grain boundaries) dominates carrier collection, creating a collecting structure extending well below the surface. The resulting effect on the collection probability is illustrated in Fig. 1. The collection probability is high within a depth y2 from the surface (average depth of preferential doping peaks), but drops to zero beyond, because each carrier generated deeper recombines at grain boundaries. It can be shown that in this case the analysis of IQEy1-ay1 plots does not yield the effective diffusion length in the material, but rather gives information on the depth of preferential doping w9x. An increase of grain size in the 1–10-mm range does not significantly improve carrier collection and short circuit current, but a deeper diffusion at grain boundary does. 3.3. Open circuit voltage In the literature, most reported p–n junction solar cells made in fine-grained polysilicon have suffered from a low open circuit voltage, typically below 370 mV w4,7,8,10x. In all cases, the analysis of the dark I– V curve of the devices revealed that this was due to a very large recombination current. The ideality factors were reported to be close to 2 over the whole characteristics and the J0r values were in the order of 10y5 A cmy2. In the assumption of deep traps and symmetrical cross-sections, a simple expression is found for the recombination current w11x: J rs
B qV E qni 1 pkT F expC D 2kT G 2 t qEmr
(1)
In this expression, q is the elementary charge; ni is the intrinsic carrier density; t is the lifetime (determined by the number of traps in the bandgap and their capture cross-sections); and Emr is the electric field at the recombination rate maximum in the junction. Using this
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expression and assuming typical cell parameters, one can calculate an approximate t value of 60 ps from a J0r of 10y5 A cmy2. Such abundant recombination most probably originates from where the grain boundaries cross the junction. Experiments in which we varied the grain size in the range 1–10 mm showed a strong decrease of the J0r with increasing grain size, giving support to grain boundary dominated recombination. Assuming all recombination takes place at grain boundaries we can get an estimate for their surface recombination velocity Sgb. With an average grain size of 1 mm, we come to a value in the order of 4–5=106 cmys. Such enormous grain boundary activity is a major hurdle for efficient devices, and therefore a special effort has to be put into reducing this value. 4. Material design Clearly, the performance of the cells made with direct CVD deposition on foreign substrates has to be increased drastically. Large improvements cannot be achieved by optimising one small aspect of the devices. Rather, research efforts are needed on all aspects of the process, from nucleation to the final metallization. In this section we report on our endeavour to obtain the polysilicon material with the required properties. In Section 5, we discuss how the best performance can be obtained from a polysilicon material with given properties and suggest a device structure which might yield good performance in spite of low material quality. 4.1. Material design through nucleation control Grain boundaries have been shown to have a very detrimental impact on device performance. We therefore have to control the deposition process in order to keep the grain boundary density as low as possible, or in other words to obtain the largest possible average grain size. Our choice of deposition technique poses a limit to the maximum achievable grain size. Direct Si CVD deposition on a substrate that does not allow heteroepitaxy always results in island or Volmer–Weber growth. Continuous layers are formed when the islands or crystallites (with a height roughly equal to the radius) coalesce with each other. With this type of layer growth it is clear that the thickness and grain size are linked. In a layer just starting to coalesce, the grain diameter is more or less equal to twice the height of the grain, which can be regarded as the ‘layer thickness’. The maximum grain size one can reach for a given thickness W is therefore equal to 2 W. Statistical variations in grain size and distance between grains set the practical limit for the grain size to W. For instance, if the cost target imposes a maximum Si layer thickness of 10 mm, our goal is to reach a layer with an average grain size of 10 mm. If, however, we would like to limit the layer
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Fig. 3. SEM picture of a Si-SiO2 sample after a nucleation process but before further growth.
Fig. 2. Nucleus density on SiO2 as a function of the HCl-flow (40 torr, 10508C, 100 sccm DCS, 3 min).
thickness to 5 mm, we will have to accept a material with smaller grains, 5 mm or below. The grain size in a CVD-deposited layer is mainly determined by the early phase deposition, i.e. the nucleation phase. The relationship between nx (the number of nuclei just before coalescence) and a (the average grain size in the final layer) can be roughly approximated by nxfa y2. For 10-mm grains for instance, the nucleus density to be obtained is 106 cmy2, whereas an average grain size of 5 mm requires a larger nx, in the order of 4=106 cmy2. Thus, the specifications for the layer thickness and the limitations of the type of layer growth we use define the nucleus density we should target in order to obtain the best possible material quality. The challenge is to reach this particular nucleus density. Unfortunately, standard deposition processes on foreign substrates will lead to abundant nucleation and therefore to a material with very small grains (below or approx. 1 mm). In order to reduce nucleation without preventing growth altogether, we use a technique inspired from the field of selective epitaxial growth (SEG), in which nucleation on Si oxide is prevented while growth occurs in windows in the oxide (see e.g. w12x). A reduction of nucleation is obtained by adding an etching agent like HCl to the gas flow and by selecting an appropriate temperature. To investigate this type of growth to achieve our goal, several experiments were carried out in a commercial epitaxial reactor. The substrates were 6-inch Cz Si wafers on which 50-nm SiO2 had been grown by wet oxidation. Before each test, a 5-min H2 bake was applied. The nucleation tests were then carried out at a pressure of 40 torr, under a constant flow of dichlorosilane (DCS) diluted in H2 (0.5% input concentration). The time, temperature and HCl flow were varied. The results and their analysis have been discussed in detail in w5x and w13x. We just show here the evolution of the
nucleus density as a function of the HCl flow at 10508C to illustrate that the nucleus density can indeed be varied over many orders of magnitude with this technique (Fig. 2). Another important feature of this graph is the sudden drop in nucleus density at a given HCl concentration. We attribute this phenomenon to a change in mode of nucleation w13x. After nucleation, the layer is grown further to reach the required thickness. Initially, the layer is not coalesced, so that many atoms appear on the oxide surface, in between the nuclei. One might think that selective conditions are necessary to let the nuclei grow while preventing new nucleation between the grains. In practice however, the crystallites after nucleation are such efficient surface atom absorbers that the atom concentration in the empty spaces of the surface is very low. New nucleation is therefore very limited or non-existent. Thus, further growth can be carried out in standard deposition conditions. Rapidly, the nuclei reach each other, coalesce and grow further vertically as grains in the layer. Fig. 3 and Fig. 4 show scanning electron microscope (SEM) pictures of the top surface of a sample before and after further growth. As the nucleus density was
Fig. 4. SEM picture of the same sample as in Fig. 3 after further growth.
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Table 1 Average grain sizes derived from TEM for three different Si layers on SiO2 Sample 1 Sample 2 Sample 3 Nucleus density nx (cmy2) Expected grain sizesny1y2 (mm) x Grain size at the top (mm) Grain size in the middle (mm) Grain size at the bottom (mm)
)108 -1 1.3 0.7 0.4
3.5=107 1.7 1.7 1.5 1.0
6=106 4.1 4.0 3.8 3.5
approximately 106 cmy2, the layer obtained has an average grain size in the order of 10 mm. A number of layers obtained by a nucleation step followed by further growth in standard conditions have been analysed using transmission electron microscopy (TEM). Table 1 gives the average grain sizes (taken as the average of the distances between two grain boundaries for each visible grain) for the bottom, middle and top areas of the layers and compares them with the grain size expected from the nucleus density after the nucleation process (derived from SEM pictures). Given the approximate nature of the method of measuring the average grain size and of the expression for the expected grain size, it can be said that the expected and measured values tally fairly well. This confirms that the control of nucleation is an effective method of producing layers with a desired grain size. The TEM analysis also allows us to get more insight into the process of competitive growth. In sample 1, grain size increases by a factor of 3 going from the bottom to the top, whereas an increase of only 15% is seen in sample 3. Thus, the impact of competitive growth decreases as the grain size increases. While oxidised Si wafers are useful to demonstrate the principle, they cannot qualify as relevant for commercial thin film solar cells. We have therefore also applied this approach of controlled nucleation on ceramic substrates. The type of ceramic substrate chosen for these experiments is commercial alumina (microcrystalline Coors ADS996). Because the surface of this type of substrates give more nucleation opportunity than thermal silicon oxide, we had to use much more selective conditions in order to obtain the desired intermediate nucleus densities. Fig. 5 and Fig. 6 show pictures of the top surface of an alumina sample that has undergone such a nucleation process, before and after further growth in standard conditions. The nucleus density before further growth is 4=106 cmy2, so that we expect an average grain size in the complete layer of approximately 5 mm. From the SEM picture we estimate the average grain size to be approximately 2.5 mm, maybe due to some additional nucleation before complete coalescence or imperfect epitaxial growth. On this type of substrate, one should probably target a somewhat lower nucleus density than the value calculated from
Fig. 5. Optical microscope picture of an alumina sample after nucleation process (1 atm, 10508C, 2 g TCSymin, 400 sccm HCl).
the desired grain size. Note that on other samples obtained without nucleation step, layers deposited in standard conditions yield layers with very small grains below 1 mm. While our experiments have demonstrated the feasibility of grain size control through the nucleation process, this approach is not free of problems. On SiO2, the sudden drop in nucleus densities at a given HCl concentration mentioned above severely limits the reproducibility of the process. Similarly, it has proved very difficult to reproduce the experiments that led to the sample shown in Fig. 5. The nucleus density typically swings from very high values to no nucleation at all. Intermediate nucleus densities, as required for this application are therefore difficult to reach in a reproducible way. This restricts the practical application of this approach. An alternative solution is to decouple nucleation from further growth. A simple technique can be used to obtain tiny crystallites on the surface of the substrate with the right surface density, after which a standard CVD process is carried out. We suggest using Si particles in suspension in a liquid. In the first step of the method, the suspension is spread on the surface of the substrate after which the liquid component is removed (for instance by evaporation of the liquid).
Fig. 6. SEM top view of a Si layer on an alumina substrate obtained by further growth on sample shown in fig.
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The conditions of this step are chosen such that particles remain on the surface with the desired density. Various techniques can be used to spread the suspension including: spinning; spraying; and dipping. A similar technique has been used to grow diamond layers w14x, but in that case, the emphasis is on achieving the growth of a continuous layer (which is difficult with diamond), whereas here the purpose is to obtain a layer with the desired grain size. Note that the amount of Si material required in this ‘nucleation’ step is very small compared to the total volume of Si in the complete layer. We have carried out preliminary experiments with the spinning of a Si powder suspension on alumina substrates and found that samples with the right nucleus density could easily be obtained. Subsequent annealing at 10008C was sufficient to fix the particles firmly to the substrate, probably through the formation of bonds between Si atoms and oxygen atoms contained in the substrate. We are planning experiments on the whole procedure including CVD deposition to form a coalesced layer. The techniques we have described have an intrinsic limitation concerning the achievable grain size in a continuous layer, as discussed earlier. If larger grains are found to be necessary, one might have to use another seed layer technique, which is able to provide grains with very small aspect ratios (heightydiameter). Aluminium-induced crystallisation (AIC) has recently been shown to be such a technique w15x. So far this technique has mainly been investigated in combination with low temperature epitaxy w16x. While this option is certainly of great interest for the long-term goals, a combination of an AIC seed layer with high temperature CVD can probably provide device quality layers more easily and may give a solution for thin film crystalline Si on a shorter term. 4.2. Deposition conditions Apart from an increase in grain size, a decrease in grain boundary electrical activity is also required for better device performance. It appears that recombination at grain boundaries can be influenced by the deposition conditions. In a recent publication, we reported on experiments with devices made in layers deposited with various growth rates while keeping grain size and other growth parameters constant w17x. The analysis shows that the recombination velocity at grain boundaries decrease by more than one order of magnitude when the deposition rate is decreased from 4.8 to 0.05 mmymin (tentative absolute values are 8=106 cmys and 6=105 cmys, respectively). 4.3. Grain boundary passivation Further investigation on the impact of the deposition conditions will probably bring about new insights on
Table 2 Impact of the hydrogenation pressure on the Voc and grain boundary recombination in CVD polysilicon solar cells Pressure (mtorr)
No hydr.
77
156
605
Voc (mV) Estimated SGB (cmys)
332 ™vth
386 1.5=106
396 1.2=106
429 4.3=105
how the grain boundary recombination velocity can be decreased. However, it is unlikely that changing the deposition parameters alone will be sufficient. A treatment to passivate grain boundaries after deposition is probably necessary. The fact that very low recombination grain boundary activity has been achieved in microcrystalline silicon and other fine-grained polycrystalline materials w18,19x suggests that the potential for improvement is very large. Grain boundary passivation through exposure to a hydrogen containing plasma at low temperatures is well known to be effective on many types of multicrystalline silicon materials. Most of the solar cell experiments with high temperature CVD have also included a hydrogenation treatment, but with standard conditions for multicrystalline silicon. There is probably a great potential for improvement through the optimisation of the hydrogenation parameters. To illustrate this, we report on some initial experiments in which the influence of the hydrogenation pressure on grain boundary recombination was investigated. The layers were deposited with DCS at 10508C and 60 torr and had an average grain size of approximately 1 mm. From these layers, solar cells were made, with diffused emitter and a mesa structure. Before antireflection coating deposition, the samples were exposed to the afterglow of a hydrogen and ammonia plasma at 4008C for 1 h. The only variable in the process was the hydrogenation pressure. The grain boundary recombination velocity was estimated from the Voc using Eq. (1), and with a simple square grains model of polycrystalline silicon and the assumption that grain boundary recombination dominates. Table 2 shows the results obtained. At 600 mtorr, SGB has decreased by approximately an order of magnitude compared to the non-hydrogenated case, and by a factor 3 compared to hydrogenation at 150 mtorr, which we used as the standard pressure in all previous experiments. Another road that might be worth investigating is to anneal the Si layers in hydrogen at high temperature just after deposition. The idea behind this is the following. It has been often suggested that the high electrical activity of grain boundaries in polysilicon deposited at high temperature is linked to decoration by oxygen atoms. Annealing at high temperature in a reducing atmosphere could remove many of these atoms and therefore could bring about a large decrease in grain boundary recombination velocity. Preliminary experiments have been carried out and give positive results,
G. Beaucarne et al. / Thin Solid Films 403 – 404 (2002) 229–237 Table 3 Impact of postdeposition hydrogen anneal on fine-grained polysilicon solar cells
No anneal With anneal
Jsc (mA cmy2)
Voc (mV)
FF (%)
h (%)
12.4 12.3
383 410
58 61
2.9 3.1
which do however need to be confirmed. In Table 3, we show the four parameters of cells in layers obtained with and without postdeposition anneal at 11908C in hydrogen for 3 min (deposition carried out at 10508C). There is a clear increase in open circuit voltage, which one could interpret as a lowering of grain boundary activity. A drawback of this annealing procedure is a possible undesired redistribution of dopants, for instance a smearing of the pq layer at the back. We estimate the lowest grain boundary recombination velocity we have reached so far to be 70 000 cmys, in a thin layer obtained with a very low growth rate and a standard hydrogenation. A combination of improved deposition conditions, optimised post-deposition anneal and hydrogenation should help define a procedure that is both practical and leads to even lower Sgb values. 5. Device design Improving the electronic quality of CVD polysilicon is undoubtedly very important towards acceptable solar cell performance. However, there is also a lot to be gained from choosing the right structure and parameters for the device. For the cell designer, the task is to get the best performance out of a given material, with its properties as boundary conditions.
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the junction recombination current in most of our cells. By increasing the doping level, we increase the electric field in the junction wsee Eq. (1)x and in doing so, we narrow the zone of maximum recombination and reduce the total recombination current. In Beaucarne et al. w8x, we reported on solar cells with various doping levels, made in very low quality material. In those cells, the Voc did not exceed 200 mV. Here, we present results obtained with an improved material, also deposited on oxidised silicon wafers. The average grain size was 19 mm and the p layers were deposited at a rate of 0.3 mmymin with DCS at 10508C and 60 torr. The cells had a diffused emitter and a mesa structure (area: 1 cm2). The four parameters are given in Table 4. The efficiency of 5.5% is the best value that has been reached so far with direct CVD on foreign substrates. Up to 3=1017 cmy3, we observe the expected trend of increasing Voc. Increasing the doping level can therefore be a useful tool to help suppress the second diode current. However, it is here clearly at the expense of the short circuit current. As we argue in our paper on carrier collection w9x, we believe this effect is not linked to a lower diffusion length but rather to the shallower junction depth at grain boundaries. A striking anomaly can be seen in this table. At the doping level of 1018 cmy3, the Voc has reduced to 430 mV, but the fill factor has increased to 75%! Such a combination of low Voc and high FF is impossible with a second diode dominated cell, therefore, this must be due to a very large first diode component. For some reason the diffusion current becomes very large at this doping and shifts the transition voltage between the first and second diode to a lower value. An explanation for this is not straightforward (why doesn’t the recombination current increase similarly?) and further investigation is needed to clarify this point.
5.1. Base doping level 5.2. TREBLE structure The doping level of the base is one of the few important material parameters that can be selected freely. It has been suggested in theoretical papers that a very high doping level was beneficial in fine-grained polysilicon because it increased the diffusion length as a result of the lowering of potential barriers at grain boundaries w20,21x. In CVD polysilicon, however, we believe this effect does not play a role. The potential barrier at grain boundaries in our material has been measured to be very low, below the thermal voltage after hydrogenation, for a doping level of 1017 cmy3 or higher w5x (grain boundaries lead to small potential barriers but large recombination velocities, which hint at very large capture cross-sections of grain boundary-related defects). Increasing the doping level can be expected to lower the diffusion length as in other materials. However, it can have a strong positive impact on the open circuit voltage, which as we have seen earlier is dominated by
As we have seen, the Voc of our devices can be improved by decreasing the grain boundary activity and increasing the base doping level. Improving the short circuit current might be more difficult. As long as the grain boundary recombination velocity remains substantially higher than 10 000 cmys, not much of the carriers Table 4 Illuminated four parameters of solar cell series with various doping levels Base doping level (cmy3)
Jsc (mA cmy2)
Voc (mV)
FF (%)
h (%)
3=1016 1017 3=1017 1018
18.6 18.0 16.4 15.0
448 455 460 430
66.0 66.8 68.8 74.6
5.5 5.5 5.2 4.8
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Fig. 7. Structure of the TREBLE solar cell.
generated below the peaks of preferential doping will be collected. Therefore we suggest making active use of the phenomenon of preferential doping for carrier collection. We should obtain a cell structure in which the dopant spikes extend deep, over almost the whole depth of the active layer. We call this cell concept the ‘ThRee-dimensional Emitter Based on Locally Enhanced diffusion (TREBLE)’ structure (Fig. 7). Preferential doping along grain boundaries is well known and has been observed in both compound and bulk cast–multicrystalline Si devices. However, in both cases, the effect on the device operation was small. In this solar cell concept, however, the collection of photogenerated carriers relies on the presence of the thin vertical regions with opposite doping. The increase of junction area is not expected to lead to lower the Voc, since J0 is dominated by recombination at the tips of the peaks. The structure is related to the parallel multijunction concept w22x, as n- and p-doped regions alternate to ensure a high collection probability. The TREBLE cell has additional beneficial features, such as, in effect, a passivation of grain boundaries and a relatively simple manufacturing procedure. A crucial task will be the experimental study of the emitter diffusion. The implementation of the three-dimensional emitter according to a chosen design is not a straightforward task. In particular, the preferential doping should be deep, but at the same time, the top emitter should be sufficiently shallow to avoid the formation of a dead layer. There is, however, a wide range of possibilities that can be implemented to achieve the goal. The various diffusion parameters (Phosphorous concentration of the source, time, temperature,«) are as many degrees of freedom allowing to approach the ideal three-dimensional emitter profile. If that does not prove sufficient, an emitter diffusion consisting of several steps can be imagined (e.g. a low temperature grain boundary doping step followed by a high temperature drive-in, or a deep diffusion combined with a subsequent etch back,«). A question that will have to be answered is whether shunting can be avoided in a device that makes extensive use of preferential doping. Indeed, if nq doped spikes
along grain boundaries reach the rear pq layer, there is a good chance that the diodes will be shunted through band-to-band tunneling. If large leakage currents cannot be avoided, one might be forced to remove the back surface field from the cell design. While this would eliminate the risk of shunting, it would make it much more difficult to maintain the series resistance at an acceptable level and it would put additional requirements on metallization. Narrower finger spacing would undoubtedly be necessary, which in turn would increase reflection. A special metallization scheme featuring a high aspect ratio of the metal fingers might turn out to be necessary (e.g. buried contacts). 6. Conclusions Thin film crystalline Si solar cells using high temperature chemical vapour deposition is a challenging approach towards cheap solar cells. Devices show very poor performance if no special measures are taken. Improvements are required at the level of material quality and device design. We demonstrate how the maximum possible grain size can be reached through nucleation control and suggest a novel technique to enhance the controllability of this approach. Recombination at grain boundaries can be reduced with a lower deposition rate and appropriate post-deposition annealing and hydrogenation treatment. The best solar cell efficiency obtained so far is 5.5% and there is a large prospect for further improvement. In particular, a device structure using preferential doping to achieve efficient carrier collection (the ‘TREBLE’ concept) could lead to devices combining both large open circuit voltage and high short circuit current density. Acknowledgements The authors wish to thank M. Caymax and I. Peytier from IMEC for the help with the CVD work, and H. Eshuis (IMEC-Universiteit Twente) for the hydrogenation experiments. This work was partly funded within the frame of the Joule III-SFINCS project (contract no. JOR3-CT98-0233). References w1x R.B. Bergmann, T.J. Rinke, C. Berge, J. Schmidt, J.H. Werner, Technical Digest 12th Int. PVSEC, 2001. w2x A. Gutjahr, C. Grasso, S.E.A. Schiermeier, P.F. Fung, A. von Keitz, Proceedings 16th EPVSEC, 2000. w3x G. Beaucarne, J. Poortmans, M. Caymax, J. Nijs, R. Mertens, D. Angermeier, S. Bourdais, R. Monna, A. Slaoui, Proceedings of the 14th EPVSEC, 1997, pp. 1007–1010. w4x T.L. Chu, Development of low cost thin film polycrystalline silicon solar cells for terrestrial applications, NSF Report NSFy RANNySEyAERy73-07843yPRy76y4, 1977. w5x G. Beaucarne, PhD thesis KULeuven (2000).
G. Beaucarne et al. / Thin Solid Films 403 – 404 (2002) 229–237 w6x G. Beaucarne, J. Poortmans, M. Caymax, J. Nijs, R. Mertens, Solid State Phenomena, 67–68, 1999, pp. 577–582. w7x R. Brendel, R.B. Bergmann, B. Fischer, J. Krinke, R. Plieninger, U. Rau, J. Reiss, H.P. Strunk, H. Wanka, J. Werner, Proceedings 26th IEEE PVSC, 1997, pp. 635–638. w8x G. Beaucarne, J. Poortmans, M. Caymax, J. Nijs, R. Mertens, IEEE Trans. Electron Devices 47 (2000) 1118–1120. w9x G. Beaucarne, S. Bourdais, A. Slaoui, J. Poortmans, Proceedings 28th IEEE Photovoltaic Specialists Conference, 2000, pp. 128– 133. w10x C. Feldman, N.A. Blum, F.G. Satkiewicz, Proceedings 14th IEEE PVSC, 1980, p. 391. w11x S.C. Choo, Solid-State Electron. 39 (1996) 308. w12x J.O. Borland, C.I. Drowley, Solid State Technol. August (1985) 141–148. w13x G. Beaucarne, J. Poortmans, M. Caymax, J. Nijs, R. Mertens, MRS Proc. 485 (1998) 89–94.
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w14x F. Jansen, M.-A. Machonkin (Xerox corporation), European patent application, publication number 0 343 846L. w15x O. Nast, S. Wenham, J. Appl. Phys. 88 (2000) 124–132. w16x N.-P. Harder, J.A. Xia, S. Oelting, O. Nast, P. Widenborg, A.G. Aberle, Proceedings 28th IEEE PVSC (2000) 351–354. w17x G. Beaucarne, M. Caymax, I. Peytier, J. Poortmans, Polycrystalline semiconductors VI, Solid State Phenomena, Vols. 80–81 (2001) 269–274. w18x K. Yamamoto, M. Yoshimi, Y. Tawada, Y. Okamoto, A. Nakajima, S. Igari, Appl. Phys. A 69 (1999) 179–185. w19x T. Baba, M. Shima, T. Matsuyama, S. Tsuge, K. Wakisaka, S. Tsuda, Proceedings 13th EPVSEC, 1995, pp. 1708–1712. w20x D.P. Bhatt, D.P. Joshi, J. Appl. Phys. 71 (1992) 4594. w21x S.A. Edmiston, A.B. Sproul, M.A. Green, S.R. Wenham, Progr. Photovoltaic Res. Appl. 3 (1995) 333. w22x M.A. Green, S.R. Wenham, Appl. Phys. Lett. 65 (1994) 2907– 2909.
Thin-film polysilicon solar cells on foreign substrates using direct thermal CVD: material and solar cell design G. Beaucarnea,*, S. Bourdaisb, A. Slaouib, J. Poortmansa a
IMEC vzw., Kapeldreef 75, B-3001 Leuven, Belgium CNRS-PHASE, 23 rue du Loess, F-67037 Strasbourg, France
b
Abstract The method to reach low-cost thin-film solar cells studied here involves the deposition of a thin layer of crystalline Si directly on cheap foreign substrates with CVD at high temperatures. Our investigation deals with controlling physical phenomena such as nucleation, layer growth and dopant diffusion to achieve specific properties enabling better performance, effectively designing both the polysilicon material and the device structure. The required grain size is obtained by depositing small isolated crystallites with the right surface density on the substrate and subsequently growing a closed layer from these nuclei. To reduce recombination velocity at grain boundaries the effect of the growth rate and post-deposition treatments are investigated. The high second diode current that usually plagues such devices can be reduced by improving the material quality and optimising the base doping level. We introduce the TREBLE concept in which carrier collection relies on the presence of deep peaks of preferential doping at grain boundaries. 䊚 2002 Elsevier Science B.V. All rights reserved. Keywords: Polycrystalline silicon; Thin film Si; Foreign substrate; CVD; Solar cell; Grain boundary
1. Introduction Many in the photovoltaic industry regard thin layers of crystalline Si on low cost substrate as a promising alternative to standard bulk Si wafers. No approach among the various methods of producing such layers has yet emerged as the ultimate solution. As a result, a broad range of techniques and approaches are being investigated. Recently, techniques involving the transfer of a thin layer of monocrystalline Si onto a cheap substrate have received a lot of attention. Thanks to the good material quality of the active layer, it is expected that high efficiencies will be reached relatively easily with such procedures. A conversion efficiency of 15.3% has already been reported w1x. All other approaches to thin film crystalline Si solar cells involve a deposition process, sometimes combined with a crystallisation proc* Corresponding author. University of New South Wales, Centre for Third-Generation Photovoltaics, Sydney, New South Wales, Australia; Tel.: q61-2-9385-4054; fax: q61-2-9385-5412. E-mail address: [email protected] (G. Beaucarne).
ess. A convenient way of giving an overview is to classify the approaches according to the highest temperature of the whole process sequence, which is usually the deposition temperature. At the lower end of the spectrum, there is the work done on nano- or microcrystalline Si on glass, which is deposited by plasmaenhanced chemical vapour deposition (PECVD) at a temperature in the order of 2008C. Considering the low temperatures involved, very good efficiencies ()7%) have been reached. Increasing the temperature (up to 6508C), one finds a variety of techniques that still allow the use of glass and often involve some kind of low temperature crystallisation (solid phase crystallisation or metal-induced crystallisation). Increasing the temperature higher into the range 700–13008C imposes the choice of another type of substrate, typically made of a ceramic material. These techniques, which have been much less intensely investigated than others, involve the direct deposition of the silicon layer with solution growth w2x or chemical vapour deposition (CVD) w3x. The research described in this paper is relevant to one of these intermediate techniques, namely the CVD route.
0040-6090/02/$ - see front matter 䊚 2002 Elsevier Science B.V. All rights reserved. PII: S 0 0 4 0 - 6 0 9 0 Ž 0 1 . 0 1 5 5 9 - 0
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Finally, some processes require temperatures above the Si melting point. By locally melting a Si layer and scanning the molten zone over the whole wafer (zone melting recrystallisation), it has been shown that it is possible to produce a Si layer with large grains ()1 mm width), and high efficiency solar cells have been made. 2. Thin film Si solar cells using direct CVD As mentioned above, this paper deals with the direct deposition of a Si layer with thermal CVD on foreign substrates. The substrate is brought to a high temperature (typically 11008C); a silicon precursor (e.g. SiHCl3) is introduced in the reactor; and through a complex sequence of gas phase and surface processes, a layer of crystalline Si is deposited. CVD is widely used in microelectronics to grow thin epitaxial layers because it allows excellent dopant concentration and layer thickness control. It is not a new idea to use CVD on potentially cheap foreign substrates for photovoltaics; experiments were done on this topic as early as 1977 w4x. However, the authors believe that the potential of this approach has not been sufficiently explored before. One of the reasons for this is that preliminary experiments tend to give discouraging results. If a CVD process is applied on an arbitrary foreign substrate, a layer with very small grains will be formed, with grains in the order of 1 mm, which implies a large density of defects. Simply applying a standard bulk Si solar cell process on non-optimised layers will yield devices with low efficiency, in the order of 2% and below. This is an order of magnitude lower than what can be achieved with bulk crystalline Si. The gap is so large that many consider it pointless to investigate it further. The approach we have followed has been to first to study in detail the factors that determine device performance, using simple low efficiency cells. This analysis has allowed us to identify the areas on which research should focus to improve devices. It turns out that progress is required both on the level of active layer material improvement and on the level of device structure. Therefore research has evolved from a situation in which the active layer material and the process were regarded as fixed parameters to a situation where they have to be designed for our specific application. This design of both solar cell material and cell structure is the topic of this paper. In Section 3, we briefly discuss the performance limiting factors of fine-grained CVD polysilicon cells. In Section 4, the potential for material improvement through control of the deposition process and post-deposition treatment is treated and our experimental results are shown and discussed. Section 5 deals with the choice of the most appropriate device design. We introduce the concept of the ThRee-dimensional
Emitter Based on Locally Enhanced diffusion (TREBLE) cell and discuss its practical implementation. 3. Performance limiting factors Simple experiments consisting of a non-optimised deposition followed by a process designed for bulk Si solar cell produce cells with very low efficiencies. However, a clear trend is difficult to find. Whereas some devices display considerable short circuit current densities, but open circuit voltages below 200 mV, others combine respectable voltages and fill factors with very small Jsc values. Our first endeavour in this research was therefore to understand what precisely determines device performance. The devices we studied were obtained with CVD polysilicon layers deposited at high temperature on oxidised Si wafers from a chlorinated precursor and with a one-side contacted solar cell process involving emitter formation through P-diffusion. In order to be able to draw conclusions, the experiments were carried out varying only one parameter at a time. 3.1. Shunting In experiments with fine-grained polysilicon solar cells, large shunt currents are sometimes observed. The results suggest that the leakage currents are caused by some process involving carrier hopping between the conduction band on the n-side and the valence band on the p-side via states in the bandgap w5x. While diode leakage can occasionally be a problem in this type of cells, we have repeatedly found in our experimental work that it is possible to obtain a sufficiently high shunt resistance by choosing deposition conditions that ensure sufficient material quality andyor by applying a hydrogenation treatment. We even achieved large area low leakage p–n junction diodes in a polysilicon layer with an average grain size as low as 0.5 mm and a ptype doping level of 5=1017 cmy3 w6x. Diode leakage is therefore not a fundamental barrier towards the development of efficient thin film fine-grained Si solar cells. 3.2. Carrier collection Thin film Si solar cells could in principle yield current densities almost as high as bulk solar cells, thanks to light confinement. However, a prerequisite is that the zone of carrier collection extends over the whole Si layer, or in other words the effective diffusion length should be at least as large as the layer thickness. In experiments on thin film Si solar cells produced in the same temperature range, this requirement has never been fulfilled w4,7,8x. In a recent paper, we gave a detailed analysis of carrier collection in this type of cell w9x. Based on a large number of experiments, two important conclusions could be drawn. The first one is that
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Fig. 1. Schematic representation of the doping profile and the collection probability in a CVD polysilicon cell with preferential doping.
recombination velocity at grain boundaries in high temperature CVD polysilicon is very large (430 000 cmys) in our material grown in standard conditions and subjected to a standard hydrogenation treatment. A second conclusion was that, in cells with diffused emitter, the phenomenon of preferential doping (enhanced diffusion of dopants along grain boundaries) dominates carrier collection, creating a collecting structure extending well below the surface. The resulting effect on the collection probability is illustrated in Fig. 1. The collection probability is high within a depth y2 from the surface (average depth of preferential doping peaks), but drops to zero beyond, because each carrier generated deeper recombines at grain boundaries. It can be shown that in this case the analysis of IQEy1-ay1 plots does not yield the effective diffusion length in the material, but rather gives information on the depth of preferential doping w9x. An increase of grain size in the 1–10-mm range does not significantly improve carrier collection and short circuit current, but a deeper diffusion at grain boundary does. 3.3. Open circuit voltage In the literature, most reported p–n junction solar cells made in fine-grained polysilicon have suffered from a low open circuit voltage, typically below 370 mV w4,7,8,10x. In all cases, the analysis of the dark I– V curve of the devices revealed that this was due to a very large recombination current. The ideality factors were reported to be close to 2 over the whole characteristics and the J0r values were in the order of 10y5 A cmy2. In the assumption of deep traps and symmetrical cross-sections, a simple expression is found for the recombination current w11x: J rs
B qV E qni 1 pkT F expC D 2kT G 2 t qEmr
(1)
In this expression, q is the elementary charge; ni is the intrinsic carrier density; t is the lifetime (determined by the number of traps in the bandgap and their capture cross-sections); and Emr is the electric field at the recombination rate maximum in the junction. Using this
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expression and assuming typical cell parameters, one can calculate an approximate t value of 60 ps from a J0r of 10y5 A cmy2. Such abundant recombination most probably originates from where the grain boundaries cross the junction. Experiments in which we varied the grain size in the range 1–10 mm showed a strong decrease of the J0r with increasing grain size, giving support to grain boundary dominated recombination. Assuming all recombination takes place at grain boundaries we can get an estimate for their surface recombination velocity Sgb. With an average grain size of 1 mm, we come to a value in the order of 4–5=106 cmys. Such enormous grain boundary activity is a major hurdle for efficient devices, and therefore a special effort has to be put into reducing this value. 4. Material design Clearly, the performance of the cells made with direct CVD deposition on foreign substrates has to be increased drastically. Large improvements cannot be achieved by optimising one small aspect of the devices. Rather, research efforts are needed on all aspects of the process, from nucleation to the final metallization. In this section we report on our endeavour to obtain the polysilicon material with the required properties. In Section 5, we discuss how the best performance can be obtained from a polysilicon material with given properties and suggest a device structure which might yield good performance in spite of low material quality. 4.1. Material design through nucleation control Grain boundaries have been shown to have a very detrimental impact on device performance. We therefore have to control the deposition process in order to keep the grain boundary density as low as possible, or in other words to obtain the largest possible average grain size. Our choice of deposition technique poses a limit to the maximum achievable grain size. Direct Si CVD deposition on a substrate that does not allow heteroepitaxy always results in island or Volmer–Weber growth. Continuous layers are formed when the islands or crystallites (with a height roughly equal to the radius) coalesce with each other. With this type of layer growth it is clear that the thickness and grain size are linked. In a layer just starting to coalesce, the grain diameter is more or less equal to twice the height of the grain, which can be regarded as the ‘layer thickness’. The maximum grain size one can reach for a given thickness W is therefore equal to 2 W. Statistical variations in grain size and distance between grains set the practical limit for the grain size to W. For instance, if the cost target imposes a maximum Si layer thickness of 10 mm, our goal is to reach a layer with an average grain size of 10 mm. If, however, we would like to limit the layer
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Fig. 3. SEM picture of a Si-SiO2 sample after a nucleation process but before further growth.
Fig. 2. Nucleus density on SiO2 as a function of the HCl-flow (40 torr, 10508C, 100 sccm DCS, 3 min).
thickness to 5 mm, we will have to accept a material with smaller grains, 5 mm or below. The grain size in a CVD-deposited layer is mainly determined by the early phase deposition, i.e. the nucleation phase. The relationship between nx (the number of nuclei just before coalescence) and a (the average grain size in the final layer) can be roughly approximated by nxfa y2. For 10-mm grains for instance, the nucleus density to be obtained is 106 cmy2, whereas an average grain size of 5 mm requires a larger nx, in the order of 4=106 cmy2. Thus, the specifications for the layer thickness and the limitations of the type of layer growth we use define the nucleus density we should target in order to obtain the best possible material quality. The challenge is to reach this particular nucleus density. Unfortunately, standard deposition processes on foreign substrates will lead to abundant nucleation and therefore to a material with very small grains (below or approx. 1 mm). In order to reduce nucleation without preventing growth altogether, we use a technique inspired from the field of selective epitaxial growth (SEG), in which nucleation on Si oxide is prevented while growth occurs in windows in the oxide (see e.g. w12x). A reduction of nucleation is obtained by adding an etching agent like HCl to the gas flow and by selecting an appropriate temperature. To investigate this type of growth to achieve our goal, several experiments were carried out in a commercial epitaxial reactor. The substrates were 6-inch Cz Si wafers on which 50-nm SiO2 had been grown by wet oxidation. Before each test, a 5-min H2 bake was applied. The nucleation tests were then carried out at a pressure of 40 torr, under a constant flow of dichlorosilane (DCS) diluted in H2 (0.5% input concentration). The time, temperature and HCl flow were varied. The results and their analysis have been discussed in detail in w5x and w13x. We just show here the evolution of the
nucleus density as a function of the HCl flow at 10508C to illustrate that the nucleus density can indeed be varied over many orders of magnitude with this technique (Fig. 2). Another important feature of this graph is the sudden drop in nucleus density at a given HCl concentration. We attribute this phenomenon to a change in mode of nucleation w13x. After nucleation, the layer is grown further to reach the required thickness. Initially, the layer is not coalesced, so that many atoms appear on the oxide surface, in between the nuclei. One might think that selective conditions are necessary to let the nuclei grow while preventing new nucleation between the grains. In practice however, the crystallites after nucleation are such efficient surface atom absorbers that the atom concentration in the empty spaces of the surface is very low. New nucleation is therefore very limited or non-existent. Thus, further growth can be carried out in standard deposition conditions. Rapidly, the nuclei reach each other, coalesce and grow further vertically as grains in the layer. Fig. 3 and Fig. 4 show scanning electron microscope (SEM) pictures of the top surface of a sample before and after further growth. As the nucleus density was
Fig. 4. SEM picture of the same sample as in Fig. 3 after further growth.
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Table 1 Average grain sizes derived from TEM for three different Si layers on SiO2 Sample 1 Sample 2 Sample 3 Nucleus density nx (cmy2) Expected grain sizesny1y2 (mm) x Grain size at the top (mm) Grain size in the middle (mm) Grain size at the bottom (mm)
)108 -1 1.3 0.7 0.4
3.5=107 1.7 1.7 1.5 1.0
6=106 4.1 4.0 3.8 3.5
approximately 106 cmy2, the layer obtained has an average grain size in the order of 10 mm. A number of layers obtained by a nucleation step followed by further growth in standard conditions have been analysed using transmission electron microscopy (TEM). Table 1 gives the average grain sizes (taken as the average of the distances between two grain boundaries for each visible grain) for the bottom, middle and top areas of the layers and compares them with the grain size expected from the nucleus density after the nucleation process (derived from SEM pictures). Given the approximate nature of the method of measuring the average grain size and of the expression for the expected grain size, it can be said that the expected and measured values tally fairly well. This confirms that the control of nucleation is an effective method of producing layers with a desired grain size. The TEM analysis also allows us to get more insight into the process of competitive growth. In sample 1, grain size increases by a factor of 3 going from the bottom to the top, whereas an increase of only 15% is seen in sample 3. Thus, the impact of competitive growth decreases as the grain size increases. While oxidised Si wafers are useful to demonstrate the principle, they cannot qualify as relevant for commercial thin film solar cells. We have therefore also applied this approach of controlled nucleation on ceramic substrates. The type of ceramic substrate chosen for these experiments is commercial alumina (microcrystalline Coors ADS996). Because the surface of this type of substrates give more nucleation opportunity than thermal silicon oxide, we had to use much more selective conditions in order to obtain the desired intermediate nucleus densities. Fig. 5 and Fig. 6 show pictures of the top surface of an alumina sample that has undergone such a nucleation process, before and after further growth in standard conditions. The nucleus density before further growth is 4=106 cmy2, so that we expect an average grain size in the complete layer of approximately 5 mm. From the SEM picture we estimate the average grain size to be approximately 2.5 mm, maybe due to some additional nucleation before complete coalescence or imperfect epitaxial growth. On this type of substrate, one should probably target a somewhat lower nucleus density than the value calculated from
Fig. 5. Optical microscope picture of an alumina sample after nucleation process (1 atm, 10508C, 2 g TCSymin, 400 sccm HCl).
the desired grain size. Note that on other samples obtained without nucleation step, layers deposited in standard conditions yield layers with very small grains below 1 mm. While our experiments have demonstrated the feasibility of grain size control through the nucleation process, this approach is not free of problems. On SiO2, the sudden drop in nucleus densities at a given HCl concentration mentioned above severely limits the reproducibility of the process. Similarly, it has proved very difficult to reproduce the experiments that led to the sample shown in Fig. 5. The nucleus density typically swings from very high values to no nucleation at all. Intermediate nucleus densities, as required for this application are therefore difficult to reach in a reproducible way. This restricts the practical application of this approach. An alternative solution is to decouple nucleation from further growth. A simple technique can be used to obtain tiny crystallites on the surface of the substrate with the right surface density, after which a standard CVD process is carried out. We suggest using Si particles in suspension in a liquid. In the first step of the method, the suspension is spread on the surface of the substrate after which the liquid component is removed (for instance by evaporation of the liquid).
Fig. 6. SEM top view of a Si layer on an alumina substrate obtained by further growth on sample shown in fig.
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The conditions of this step are chosen such that particles remain on the surface with the desired density. Various techniques can be used to spread the suspension including: spinning; spraying; and dipping. A similar technique has been used to grow diamond layers w14x, but in that case, the emphasis is on achieving the growth of a continuous layer (which is difficult with diamond), whereas here the purpose is to obtain a layer with the desired grain size. Note that the amount of Si material required in this ‘nucleation’ step is very small compared to the total volume of Si in the complete layer. We have carried out preliminary experiments with the spinning of a Si powder suspension on alumina substrates and found that samples with the right nucleus density could easily be obtained. Subsequent annealing at 10008C was sufficient to fix the particles firmly to the substrate, probably through the formation of bonds between Si atoms and oxygen atoms contained in the substrate. We are planning experiments on the whole procedure including CVD deposition to form a coalesced layer. The techniques we have described have an intrinsic limitation concerning the achievable grain size in a continuous layer, as discussed earlier. If larger grains are found to be necessary, one might have to use another seed layer technique, which is able to provide grains with very small aspect ratios (heightydiameter). Aluminium-induced crystallisation (AIC) has recently been shown to be such a technique w15x. So far this technique has mainly been investigated in combination with low temperature epitaxy w16x. While this option is certainly of great interest for the long-term goals, a combination of an AIC seed layer with high temperature CVD can probably provide device quality layers more easily and may give a solution for thin film crystalline Si on a shorter term. 4.2. Deposition conditions Apart from an increase in grain size, a decrease in grain boundary electrical activity is also required for better device performance. It appears that recombination at grain boundaries can be influenced by the deposition conditions. In a recent publication, we reported on experiments with devices made in layers deposited with various growth rates while keeping grain size and other growth parameters constant w17x. The analysis shows that the recombination velocity at grain boundaries decrease by more than one order of magnitude when the deposition rate is decreased from 4.8 to 0.05 mmymin (tentative absolute values are 8=106 cmys and 6=105 cmys, respectively). 4.3. Grain boundary passivation Further investigation on the impact of the deposition conditions will probably bring about new insights on
Table 2 Impact of the hydrogenation pressure on the Voc and grain boundary recombination in CVD polysilicon solar cells Pressure (mtorr)
No hydr.
77
156
605
Voc (mV) Estimated SGB (cmys)
332 ™vth
386 1.5=106
396 1.2=106
429 4.3=105
how the grain boundary recombination velocity can be decreased. However, it is unlikely that changing the deposition parameters alone will be sufficient. A treatment to passivate grain boundaries after deposition is probably necessary. The fact that very low recombination grain boundary activity has been achieved in microcrystalline silicon and other fine-grained polycrystalline materials w18,19x suggests that the potential for improvement is very large. Grain boundary passivation through exposure to a hydrogen containing plasma at low temperatures is well known to be effective on many types of multicrystalline silicon materials. Most of the solar cell experiments with high temperature CVD have also included a hydrogenation treatment, but with standard conditions for multicrystalline silicon. There is probably a great potential for improvement through the optimisation of the hydrogenation parameters. To illustrate this, we report on some initial experiments in which the influence of the hydrogenation pressure on grain boundary recombination was investigated. The layers were deposited with DCS at 10508C and 60 torr and had an average grain size of approximately 1 mm. From these layers, solar cells were made, with diffused emitter and a mesa structure. Before antireflection coating deposition, the samples were exposed to the afterglow of a hydrogen and ammonia plasma at 4008C for 1 h. The only variable in the process was the hydrogenation pressure. The grain boundary recombination velocity was estimated from the Voc using Eq. (1), and with a simple square grains model of polycrystalline silicon and the assumption that grain boundary recombination dominates. Table 2 shows the results obtained. At 600 mtorr, SGB has decreased by approximately an order of magnitude compared to the non-hydrogenated case, and by a factor 3 compared to hydrogenation at 150 mtorr, which we used as the standard pressure in all previous experiments. Another road that might be worth investigating is to anneal the Si layers in hydrogen at high temperature just after deposition. The idea behind this is the following. It has been often suggested that the high electrical activity of grain boundaries in polysilicon deposited at high temperature is linked to decoration by oxygen atoms. Annealing at high temperature in a reducing atmosphere could remove many of these atoms and therefore could bring about a large decrease in grain boundary recombination velocity. Preliminary experiments have been carried out and give positive results,
G. Beaucarne et al. / Thin Solid Films 403 – 404 (2002) 229–237 Table 3 Impact of postdeposition hydrogen anneal on fine-grained polysilicon solar cells
No anneal With anneal
Jsc (mA cmy2)
Voc (mV)
FF (%)
h (%)
12.4 12.3
383 410
58 61
2.9 3.1
which do however need to be confirmed. In Table 3, we show the four parameters of cells in layers obtained with and without postdeposition anneal at 11908C in hydrogen for 3 min (deposition carried out at 10508C). There is a clear increase in open circuit voltage, which one could interpret as a lowering of grain boundary activity. A drawback of this annealing procedure is a possible undesired redistribution of dopants, for instance a smearing of the pq layer at the back. We estimate the lowest grain boundary recombination velocity we have reached so far to be 70 000 cmys, in a thin layer obtained with a very low growth rate and a standard hydrogenation. A combination of improved deposition conditions, optimised post-deposition anneal and hydrogenation should help define a procedure that is both practical and leads to even lower Sgb values. 5. Device design Improving the electronic quality of CVD polysilicon is undoubtedly very important towards acceptable solar cell performance. However, there is also a lot to be gained from choosing the right structure and parameters for the device. For the cell designer, the task is to get the best performance out of a given material, with its properties as boundary conditions.
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the junction recombination current in most of our cells. By increasing the doping level, we increase the electric field in the junction wsee Eq. (1)x and in doing so, we narrow the zone of maximum recombination and reduce the total recombination current. In Beaucarne et al. w8x, we reported on solar cells with various doping levels, made in very low quality material. In those cells, the Voc did not exceed 200 mV. Here, we present results obtained with an improved material, also deposited on oxidised silicon wafers. The average grain size was 19 mm and the p layers were deposited at a rate of 0.3 mmymin with DCS at 10508C and 60 torr. The cells had a diffused emitter and a mesa structure (area: 1 cm2). The four parameters are given in Table 4. The efficiency of 5.5% is the best value that has been reached so far with direct CVD on foreign substrates. Up to 3=1017 cmy3, we observe the expected trend of increasing Voc. Increasing the doping level can therefore be a useful tool to help suppress the second diode current. However, it is here clearly at the expense of the short circuit current. As we argue in our paper on carrier collection w9x, we believe this effect is not linked to a lower diffusion length but rather to the shallower junction depth at grain boundaries. A striking anomaly can be seen in this table. At the doping level of 1018 cmy3, the Voc has reduced to 430 mV, but the fill factor has increased to 75%! Such a combination of low Voc and high FF is impossible with a second diode dominated cell, therefore, this must be due to a very large first diode component. For some reason the diffusion current becomes very large at this doping and shifts the transition voltage between the first and second diode to a lower value. An explanation for this is not straightforward (why doesn’t the recombination current increase similarly?) and further investigation is needed to clarify this point.
5.1. Base doping level 5.2. TREBLE structure The doping level of the base is one of the few important material parameters that can be selected freely. It has been suggested in theoretical papers that a very high doping level was beneficial in fine-grained polysilicon because it increased the diffusion length as a result of the lowering of potential barriers at grain boundaries w20,21x. In CVD polysilicon, however, we believe this effect does not play a role. The potential barrier at grain boundaries in our material has been measured to be very low, below the thermal voltage after hydrogenation, for a doping level of 1017 cmy3 or higher w5x (grain boundaries lead to small potential barriers but large recombination velocities, which hint at very large capture cross-sections of grain boundary-related defects). Increasing the doping level can be expected to lower the diffusion length as in other materials. However, it can have a strong positive impact on the open circuit voltage, which as we have seen earlier is dominated by
As we have seen, the Voc of our devices can be improved by decreasing the grain boundary activity and increasing the base doping level. Improving the short circuit current might be more difficult. As long as the grain boundary recombination velocity remains substantially higher than 10 000 cmys, not much of the carriers Table 4 Illuminated four parameters of solar cell series with various doping levels Base doping level (cmy3)
Jsc (mA cmy2)
Voc (mV)
FF (%)
h (%)
3=1016 1017 3=1017 1018
18.6 18.0 16.4 15.0
448 455 460 430
66.0 66.8 68.8 74.6
5.5 5.5 5.2 4.8
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Fig. 7. Structure of the TREBLE solar cell.
generated below the peaks of preferential doping will be collected. Therefore we suggest making active use of the phenomenon of preferential doping for carrier collection. We should obtain a cell structure in which the dopant spikes extend deep, over almost the whole depth of the active layer. We call this cell concept the ‘ThRee-dimensional Emitter Based on Locally Enhanced diffusion (TREBLE)’ structure (Fig. 7). Preferential doping along grain boundaries is well known and has been observed in both compound and bulk cast–multicrystalline Si devices. However, in both cases, the effect on the device operation was small. In this solar cell concept, however, the collection of photogenerated carriers relies on the presence of the thin vertical regions with opposite doping. The increase of junction area is not expected to lead to lower the Voc, since J0 is dominated by recombination at the tips of the peaks. The structure is related to the parallel multijunction concept w22x, as n- and p-doped regions alternate to ensure a high collection probability. The TREBLE cell has additional beneficial features, such as, in effect, a passivation of grain boundaries and a relatively simple manufacturing procedure. A crucial task will be the experimental study of the emitter diffusion. The implementation of the three-dimensional emitter according to a chosen design is not a straightforward task. In particular, the preferential doping should be deep, but at the same time, the top emitter should be sufficiently shallow to avoid the formation of a dead layer. There is, however, a wide range of possibilities that can be implemented to achieve the goal. The various diffusion parameters (Phosphorous concentration of the source, time, temperature,«) are as many degrees of freedom allowing to approach the ideal three-dimensional emitter profile. If that does not prove sufficient, an emitter diffusion consisting of several steps can be imagined (e.g. a low temperature grain boundary doping step followed by a high temperature drive-in, or a deep diffusion combined with a subsequent etch back,«). A question that will have to be answered is whether shunting can be avoided in a device that makes extensive use of preferential doping. Indeed, if nq doped spikes
along grain boundaries reach the rear pq layer, there is a good chance that the diodes will be shunted through band-to-band tunneling. If large leakage currents cannot be avoided, one might be forced to remove the back surface field from the cell design. While this would eliminate the risk of shunting, it would make it much more difficult to maintain the series resistance at an acceptable level and it would put additional requirements on metallization. Narrower finger spacing would undoubtedly be necessary, which in turn would increase reflection. A special metallization scheme featuring a high aspect ratio of the metal fingers might turn out to be necessary (e.g. buried contacts). 6. Conclusions Thin film crystalline Si solar cells using high temperature chemical vapour deposition is a challenging approach towards cheap solar cells. Devices show very poor performance if no special measures are taken. Improvements are required at the level of material quality and device design. We demonstrate how the maximum possible grain size can be reached through nucleation control and suggest a novel technique to enhance the controllability of this approach. Recombination at grain boundaries can be reduced with a lower deposition rate and appropriate post-deposition annealing and hydrogenation treatment. The best solar cell efficiency obtained so far is 5.5% and there is a large prospect for further improvement. In particular, a device structure using preferential doping to achieve efficient carrier collection (the ‘TREBLE’ concept) could lead to devices combining both large open circuit voltage and high short circuit current density. Acknowledgements The authors wish to thank M. Caymax and I. Peytier from IMEC for the help with the CVD work, and H. Eshuis (IMEC-Universiteit Twente) for the hydrogenation experiments. This work was partly funded within the frame of the Joule III-SFINCS project (contract no. JOR3-CT98-0233). References w1x R.B. Bergmann, T.J. Rinke, C. Berge, J. Schmidt, J.H. Werner, Technical Digest 12th Int. PVSEC, 2001. w2x A. Gutjahr, C. Grasso, S.E.A. Schiermeier, P.F. Fung, A. von Keitz, Proceedings 16th EPVSEC, 2000. w3x G. Beaucarne, J. Poortmans, M. Caymax, J. Nijs, R. Mertens, D. Angermeier, S. Bourdais, R. Monna, A. Slaoui, Proceedings of the 14th EPVSEC, 1997, pp. 1007–1010. w4x T.L. Chu, Development of low cost thin film polycrystalline silicon solar cells for terrestrial applications, NSF Report NSFy RANNySEyAERy73-07843yPRy76y4, 1977. w5x G. Beaucarne, PhD thesis KULeuven (2000).
G. Beaucarne et al. / Thin Solid Films 403 – 404 (2002) 229–237 w6x G. Beaucarne, J. Poortmans, M. Caymax, J. Nijs, R. Mertens, Solid State Phenomena, 67–68, 1999, pp. 577–582. w7x R. Brendel, R.B. Bergmann, B. Fischer, J. Krinke, R. Plieninger, U. Rau, J. Reiss, H.P. Strunk, H. Wanka, J. Werner, Proceedings 26th IEEE PVSC, 1997, pp. 635–638. w8x G. Beaucarne, J. Poortmans, M. Caymax, J. Nijs, R. Mertens, IEEE Trans. Electron Devices 47 (2000) 1118–1120. w9x G. Beaucarne, S. Bourdais, A. Slaoui, J. Poortmans, Proceedings 28th IEEE Photovoltaic Specialists Conference, 2000, pp. 128– 133. w10x C. Feldman, N.A. Blum, F.G. Satkiewicz, Proceedings 14th IEEE PVSC, 1980, p. 391. w11x S.C. Choo, Solid-State Electron. 39 (1996) 308. w12x J.O. Borland, C.I. Drowley, Solid State Technol. August (1985) 141–148. w13x G. Beaucarne, J. Poortmans, M. Caymax, J. Nijs, R. Mertens, MRS Proc. 485 (1998) 89–94.
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w14x F. Jansen, M.-A. Machonkin (Xerox corporation), European patent application, publication number 0 343 846L. w15x O. Nast, S. Wenham, J. Appl. Phys. 88 (2000) 124–132. w16x N.-P. Harder, J.A. Xia, S. Oelting, O. Nast, P. Widenborg, A.G. Aberle, Proceedings 28th IEEE PVSC (2000) 351–354. w17x G. Beaucarne, M. Caymax, I. Peytier, J. Poortmans, Polycrystalline semiconductors VI, Solid State Phenomena, Vols. 80–81 (2001) 269–274. w18x K. Yamamoto, M. Yoshimi, Y. Tawada, Y. Okamoto, A. Nakajima, S. Igari, Appl. Phys. A 69 (1999) 179–185. w19x T. Baba, M. Shima, T. Matsuyama, S. Tsuge, K. Wakisaka, S. Tsuda, Proceedings 13th EPVSEC, 1995, pp. 1708–1712. w20x D.P. Bhatt, D.P. Joshi, J. Appl. Phys. 71 (1992) 4594. w21x S.A. Edmiston, A.B. Sproul, M.A. Green, S.R. Wenham, Progr. Photovoltaic Res. Appl. 3 (1995) 333. w22x M.A. Green, S.R. Wenham, Appl. Phys. Lett. 65 (1994) 2907– 2909.