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Lou TomeseNa, of Vttesse Semic ctor in conv satien It is two years since we had an in-depth talk with Lou Tomasetta, in that time Vitesse has restructured shifting its emphasis from the high performance computer market to driving a whole host of applications in communication, for both telecom and computers. Here, Lou Tomasetta updates US Correspondent Jo Ann McDonald on the restructured Vitesse looking not only at new custom and standard products such as the SCAMP and Pentium cache controller, H-GaAs IV and Convex but also how the customer base is changing. JM. When you started in 1984, you chose Si fab-compatible processes and integration and power rather than just speed. How has that stood the ten year test? LT: It was correct then and, quite frankly, it still is. We've found that if you keep to this track then building very high performance 10 Gb/s SON E T devices actually is easier. The discipline you need to make million transistor circuits mandates you have a process so tightly controlled the performance levels you can achieve for modest size circuits (as high as 10 Gb/s) are likely to be easier to build than if you had gone for high speed regardless o f process control. Eventually, process control and yields become your most important factor. JM: How do you see the new S C A M P C P U as a GaAs ASIC upgradable board swap for Unisys A series and the Pentium cache controller - major steps for Vitesse - in the high-end CPU context? LT: The consensus is that almost all of the high performance processors five years from now will be built using conventional microprocessors connected together with elaborate interconnects and some very sophisticated software, and you will not need the man-century designers'

Lou Tomasetta, President & CEO Vitesse Semiconductor Corp.

time to do a custom processor for every application. You'll start seeing systems built of 10, 20, 50, 100 very conventional microprocessors that can give the system the performance of supercomputer. When that change became obvious a few years ago, it snowbailed faster than anyone thought and because of our work with the communications companies, we were able

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to exploit a lot of that technology and shift our emphasis to a very tight communications focus, because performance is all, and what we do best. When you think about the data rates that you have to move around - take a typical processor a year from being widely available, i.e. 100 MHz clock rate - some of the MIPS processors in fact are already beyond this at 64 bits wide and 100 MHz. That's 6.4 Gb/s coming out of one processor. Now you start connecting 10, 20 or 30 of those together and you don't have to have a bandwidth in your communication channel that can make the assumption that everything is always running at 100% efficiency. It doesn't take very long, even assuming a 10% efficiency, that you start needing communication channels that have multiple gigabyte/s in order to make sure that the communications channel between p r o c e s s o r s isn't totally clogged up. Our strategy is very focused and, from the standpoint of the technology, is almost entirely communications driven. For the end user, it's a combination of comms and computer applications. But the baseline technology is the same. It involves taking parallel data, serializing it, putting it on some kind of channel, recovering

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it. and coherently putting at back into a parallel form. If you do that in telecommunications, it's called SONET. If you do it on a connection between a disk drive and processor, you might call it Fiber Channel. If you're doing it between a LAN you might call it ATM. But in terms of expertise it's the same kind of problem. Likewise, in switching, whether it's SONET, ATM, or a general purpose switch, to be successful you really need the same kind of core technology. Our communications strategy springs from these relatively conceptually simple, although not so easy to implement applications, like 2.5 Gb/s S O N E T mux, demux, and PLLs. These systems are now migrating to 10 Gb/s and will probabl~ be prototyped sometime next year. That's a pretty high data rate, and you can do that with conventional M E S F E T t e c h n o l o g y if you have a g o o d process and can control things well enough. Of course, then you have to ask yourself are we ten years too early developing more esoteric GaAs-based technologies because the marketplace for something in excess of 10 Gb/s is so small. aM: SCAMP was a custom architecture, geared for Unisys' particular customer base. It's a routine ASIC for you and a natural upgrade for them? LT: Yes. Unisys had already done this part in advanced CMOS and

decided that, since our ASIC capability was essentially transparent to their design group, they could do it with the same tools and so on for a relatively small N R E certainly minor compared to the man-century that probably went into doing the original processor - they could basically take their design which was done in V H D L environment, run it through a synthesis tool and map it into our gate array. They could probably have gotten another factor of 2 performance if they had done a c u s t o m chip, but the return on investment probably wouldn't have been worth it. So, with a relatively small amount of engineering effort, they were able to pick up a factor of 2.5 to 3 speed improvement, which was big for the system. aM: It sounds too easy, but that's undoubtedly reflective of not only a stable process, but also how eft'iciently the C A D tools have evolved in such a short time. How long did it take to implement'? LT: It took about a year from when they started to when they l a d prototypes, and then about anather nine months to get it qualified and actually start shipping systems with it. Compared to doing a custom design from scratch, it took less than half the time. We've done a few hundred ASICs, so we have most o f t e c h n o l o g y specific landmines taken ce.re of, but a lot of the credit for lhe first-time

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success must be given to the sophistication of the design tools that are now available. You need a stable process and good simulation tools. From our viewpoint, the SCAMP chip simply has about 75 000 gates, and a big register file. Other than that, the architecture, for the most part, is buried in the V H D L code. JM: The Pentium cache controller chip, however, is a new Vitesse standard product. What's behind the development of the product? LT: The strategy here is not to build the processor itself, because you can't justify the man-century for the small part of the market where GaAs might appropriate. You don't need that for any of these conventional processors. If the strategy is eventually to connect them together then that takes the burden off of making processors with higher and higher speed, and moves it to communication channels, which is quite frankly a higher volume and probably a somewhat less designintensive task that a small company like Vitesse can be very effective at solving. So the cache controller strategy is really part of this communication strategy. Right now, the cache controller functions aren't really communication chips, they are controlling second level cache to provide a zero wait state solution, so that the processors can run as efficiently as possible with the very limited memory that you can afford to put on the processor chip itself. But eventually, if you look out a generation or so these massively parallel systems, require a bus structure that, when you connect many processors together, will access another memory block that will have to be coherent among the different processors. There are a few candidates vying for that kind of communication chip. Ira Deyhimy (VP Engineering) is personally leading our efforts to understand this area and bring our first products to market. The one that we're investing a considerable amount of effort in is called SCI, or Scalable Coherent Interface. SCI has a lot of the features of both our Fiber Channel datacom chipset and our cache controllers. It's actually a control node that can direct the communications to a specific target processor as well as arbitrate who goes on the bus now, and who doesn't, and how it eventually con-

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nects with the large main memory. JM: What new doors does the Pentium cache controller now open for you? LT: For both uniprocessors and multiprocessors, the cache controller product family has enabled us to learn a lot about "the conventional microprocessor e n v i r o n m e n t . G r a n t e d , these are all geared for Intel architecture-type of processors. But we've learned lot about how to connect these on buses, how bus structures actually work, and how to interface with microprocessors in general. It's a good product family in its own right, but it's also strategic in the sense that it's a piece of the puzzle that we need to really execute our long term strategic vision o f being able to supply all the communication needs, both for high and telecoms, and for computer-based comms, between each chip, between chips and I/0 devices, or on the central bus. JM: How do you characterize the change in your customer base from a few years ago? LT: Two to three years ago our customer base consisted of a few large companies that needed speed, at almost any price, to solve their problems. Today, the customer base is considerably broader. We don't have any single dominant customer as we did before. The volumes are much higher, the ASPs are much lower and that's good. On average,

the parts are also physically a lot smaller. They may have as many transistors as they to, but that's more a reflection of the generation change in process technology. We still have some customers that squeeze complexity to the max and we are shipping a reasonable n u m b e r o f circuits with substantially over 1 million transistors.

Two years ago the percentage of parts we shipped that really stressed the process technology, was probably 50%. Today, it's p r o b a b l y 10% and the rest of the volume is relatively straightforward sized parts to build where yields are 75 - 80%, with some as high as 95%, where there's not any real pressure in physically making the parts. There it's an issue of getting yields up as high as you can to become as cost-effective as possible, to capture more and more of that business. In just the last few months, we've won two designs for relatively small ASICs, typically 20 or 30 thousand gates that, if they were done a year ago, would have probably gone to BiCMOS. These parts have clock rates that can't be done in conventional CMOS, and we can be built at the same price as BiCMOS. We've been able to get our yields up and our cost structurally where we can compete on a function by function basis with BiCMOS. Plus, we provide customers a speed advantage factor of two over BiCMOS, and in at least one case, somewhat lower power. Both of these design wins ship greater that 25 000 units a year, and p r o b a b l y represent more than a million dollars a year each. This is nice business with which to build a Continued on page 30

Cache System Schematic.

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