2D analytical model for surface potential based electric field and impact of wok function in DMG SB MOSFET

Accepted Manuscript 2D analytical model for surface potential based electric field and impact of wok function in DMG SB MOSFET

Prashanth Kumar, Brinda Bhowmick PII:

S0749-6036(17)31052-2

DOI:

10.1016/j.spmi.2017.06.001

Reference:

YSPMI 5048

To appear in:

Superlattices and Microstructures

Received Date:

03 May 2017

Revised Date:

31 May 2017

Accepted Date:

01 June 2017

Please cite this article as: Prashanth Kumar, Brinda Bhowmick, 2D analytical model for surface potential based electric field and impact of wok function in DMG SB MOSFET, Superlattices and Microstructures (2017), doi: 10.1016/j.spmi.2017.06.001

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ACCEPTED MANUSCRIPT

2D analytical model for surface potential based electric field and impact of wok function in DMG SB MOSFET Prashanth Kumar, Brinda Bhowmick Abstract - In this paper an analytical surface potential model of a dual material gate (DMG) Schottky Barrier (SB) metaloxide-semiconductor field effect transistor (MOSFET) is explored. The surface potential model is established by using twodimensional solution of Poisson’s equation, with essential boundary conditions near the drain and source ends. The proposed device has metal-semiconductor (Schottky) junction instead of p-n junction. In the DMG structure the effect of work function, drain to source voltage, gate to source voltage on the surface potential are observed. Furthermore, the simulation results of proposed DMG-SB-MOSFET shows good immunity to short channel effects(SCE) and is assessed by considering the draininduced barrier lowering(DIBL) and compared with equivalent single material gate (SMG) SB- MOSFET. Moreover, the DMG and SMG SB-MOSFET are compared in terms of ambipolar behavior, ON-state and OFF-state current of the device. The developed analytical model for surface potential along the channel length are in close agreement with the Silvaco Technology Computer Aided Design device simulator data. Index Terms— two-dimensional (2D) Poisson’s equation, Schottky-Barrier, Dual Metal Gate. Introduction When CMOS device dimensions are scaled down, the gate is unable to control the channel and short channel effects (SCEs) enhance [1-5]. To overcome this limitation, several device design, such as multiple gate and gate all around FETs [6-7], have been proposed that improve gate controllability and reduce SCEs. However, the fabrication of sharp junctions in source/drain (S/D) and semiconductor becomes difficult at the lower dimensions [8-10]. When the length of the channel for conventional multiple gate transistors is scaled down to extremely small lengths, the series resistance of source and drain enhances considerately in nanometer devices. According to international road map for semiconductor (ITRS) [11] reducing the parasitic source-drain resistance is a difficult challenge. An essential decrease in source-drain series resistance by using metal source/drain regions in nanometer devices. To overcome these limitations Schottky Barrier MOSFETs with excellent performance has been reported [12-13], whose Ion/Ioff ratio is 106 and subthreshold slope is 66mv/dec. Furthermore, a simple process fabrication of SB-MOSFET is possible to provide the smooth formation of ultra-sharp source-drain junction by replacing with metal in the region of doped S/D [13, 14]. Conventionally, the dual material gate Schottky Barrier devices have improved gate control and excellent short channel performance due to double gate has been stated in this paper [15, 16]. It has been reported from the literature that the gate engineering structures like dual material gate device the enhanced carrier transport efficiency has been achieved as compared to SMG structures [17]. Ryo tanabe et al, have reported an analytically modeled double gate SB device and threshold voltage model and achieved better SCEs [16]. Furthermore, a double material gate all around with high–k gate oxide, which conveys improved output conductance, transconductance and early voltage compared to SMG [18]. To surmount the ambipolar-state conduction problem in SB-MOSFET, numerous designs have been proposed such as Si3N4 oxide deposit between the source-channel and drain channel junction and using abundant doping in the drain/channel junction. However these specified designs reduce ambipolar-state conduction but increases the process complexity [19]. To overcome these problems, we introduced DMG SB-MOSFET. In this paper the analytical model for surface potential in dual material gate (DMG) silicon on insulator (SOI) structure is derived. The accuracy of the results assimilated by the use of analytical model and the results of Atlas simulator [20]. The SCEs, such as drain induced barrier lowering (DIBL) is examined as function of channel length. Moreover, we also examined the Ion/Ioff ratio, and ambipolarity characteristics of the proposed device. Device structure and Energy band t diagram ox

Metal M1

Metal M2 tox

Source Metal

x y

P-Substrate (1x1016cm-3 )

tsi

Buried Oxide Layer

tbox

Drain Metal

Fig. 1 Schematic cross-section of DMG SB-MOSFET with two different gate-metal work functions:

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(a)

(b) Fig. 2 Energy band diagram of DMG SB-MOSFET in (a) off-state (Vgs =0 V and Vds = 0.6 V) (b) on-state (Vgs =0.6V and Vds = 0.6 V). Fig. 1 shows cross-section of dual material gate Schottky Barrier (SB) MOSFET with different work functions in gate region. The work function ( m1 ) of gate Metal (M1) and work function ( m 2 ) Metal (M2) are taken as 4.6eV and 4.4eV respectively. The thickness of silicon is 10nm and boron doping concentration in the channel is (1x1016 cm-3). The channel length L (L = L1+L2) of the DMG structure is 80nm with metal (M1) length is 60nm and metal (M2) length is 20nm. The thickness of Silicon dioxide (tox) = 2nm and thickness of buried oxide tbox,b = 20nm. The work function of source/drain metals are considered as 4.46eV. The work function of single material gate (SMG) is taken as 4.3eV and all other dimensions are considered similar to DMG SB-MOSFET. The band diagram of channel region is pulled upwards at Vgs = 0V and Vds =0.6V as shown in Fig. 2(a). However, even at Vgs = 0 V carrier tunneling takes place at the drain side. As gate bias is increased the bands are pulled downwards as shown in Fig. 2(b) at Vgs = 0.6V and Vds = 0.6V. Therefore the distance between source/channel junctions reduces by increasing the carrier tunneling into the channel region, which increases the tunneling current. Formulation of surface potential distribution The channel surface potential for the DMG SB-MOSFET can be acquired by 2-D Poisson’s equation,

 2 (x,y)  2 (x,y) qN a   x 2 y 2 ε Si Where, Na is the doping in the silicon channel,  (x,y) is the 2-D potential profile in the silicon channel, q is the electron charge, and εsi is the dielectric permittivity of silicon. The 2-D parabolic potential in the silicon channel under the M1 and M2 is incorporated for the analysis [21]. Therefore, the potential along the channel length is given by

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1 ( x, y )   s1 ( x)  K 11 ( x) y  K 12 ( x) y 2 for 0 ≤ x ≤ L1, 0 ≤ y ≤ tsi

 2 ( x, y )   s 2 ( x)  K 21 ( x) y  K 22 ( x) y 2 for L2 ≤ x ≤ L, 0 ≤ y ≤ tsi Where the arbitrary coefficients K11(x), K12(x), K21(x) and K22(x) are the functions of x only and are calculated to the vertical and horizontal co-ordinates as shown in Fig. 1. The Poisson’s equation in the silicon channel region are solved under M1 and M2 by using following boundary conditions. The boundary conditions used are (i)

The potential at the source/channel junction is

1 (0,0)   s1 (0)  Vbi ,S / D  bS (ii)

(4)

The potential at the drain/channel junction is

 2 ( L1 ,0)   s 2 ( L1 )  Vbi ,S / D  bD  VDS Where bS and

(5)

bD are Schottky Barrier lowering at the source and drain [20, 22]. Vbi ,S / D is the built in potential at the

source/drain and Vds is drain to source voltage. Vbi , S / D   

Eg 2

 F  S / D

1

 q  2 1 bS     ES 2  4 s  1

 q  2 1 bD     ED 2  4 s  Here ES and ED are the electric field at source and drain side here  F  VT ln( N a / ni ) is the Fermi potential in silicon is

  1 and   1.5 are the fitting parameters and S / D is the work function of source/drain. At the interface of the gate- oxide the electric field is continuous; we obtain the subsequent boundary conditions [23],

Cox , f 1 ( x, y ) y 0  VGS  VFB1

 Si

Cox , f  2 ( x, y ) y 0  VGS  VFB 2

 Si





d 1( x, y ) dy

d  2 ( x, y ) dy

(6) y 0

(7) y 0

Where VFB ,1 and VFB 2 the front channel flat band voltage and εsi are the permittivity of the silicon, and Vgs is the gate-to-source voltage respectively. (iii)

The electric field at the interface of the back channel and buried oxide is

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Cbox VS  VFB ,b   B ( x)

 Si



Cbox VS  VFB ,b   B ( x)

 Si

d 1( x, y ) dy



(8) y t si

d  2 ( x, y ) dy

(9) y t si

Where  B (x) the potential along the back channel and buried oxide interface, VFB ,b is the back channel flat band voltage, and VS being the substrate voltage.

(iv)

The potential in entire channel is continuous; we may acquire the subsequent boundary conditions at the interface of the two different metals.

1 ( L1 ,0)   2 ( L1 ,0) (v)

(10)

The electric field is continuous at the interface of the two metals M1 and M2. d 1( x, y ) dx

 x  L1

d  2 ( x, y ) dx

(11) x  L1

using the equations from (6 - 9) we can obtain the coefficients k11(x), k12(x), k21(x) and k22(x). Then by replacing these coefficients into the expression for 1 ( x, y ) and setting y = 0, we can obtain 2 d 2 S 1 1 and d  S 2  1  ( x)     ( x )   1 2 dx 2  S1 dx 2  S2



1 

2 

qN a

 Si

qN a

 Si

t 2 Si C si (2C si  Cbox ) 2(C ox , f C Si  C ox , f Cbox  Cbox C Si )

 C ox , f (C Si  C box )  C box   2(V SUB  V FB ,b ) 2  2(V GS V FB1 , f ) 2  t Si C si (2C si  C box )  t Si C si (2C si  C box ) 

 C ox , f (C Si  C box )  C box   2(V SUB  V FB ,b ) 2  2(V GS V FB 2 , f ) 2  t C ( 2 C  C ) t C ( 2 C si  C box ) Si Si si si box  si 

(12)

(13)

(14)

(15)

Where CSi , Cox , f and Cbox are the capacitances of the, silicon layer, gate oxide and buried oxide. tbox,b is buried oxide thickness, tsi is silicon layer thicknesses εox and εsi are the permittivity of the silicon, is tox,f front oxide thickness    CSi  Si , C ox , f  ox and Cbox  ox t ox , f t box ,b tsi The solution of equation (12) must satisify the boundery conditions  01 (0)  Vbi ,S / D  bS

and  02 ( L1  L2 )  Vbi ,S / D  bD  VDS The second order inhomogeneous differential equation with a constant coefficient has the subsequent solution

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 S1 ( x)  U sk 1 exp(x)  U sk 2 exp(x)  1

 S 2 ( x)  U sk 3 exp( ( x  L1 ))  U sk 4 exp( ( x  L1 ))   2 where    , 1  we can obtain

(16)

(17)

1 2 and  2  by using boundary conditions (4), (5), (10) and (11) to solve Usk1, Usk2, Usk3 and Usk4   U sk 1 

(Vbi   2  bD  VDS )  a11  (Vbi  bS  1 )e  ( L1  L2 ) e  ( L1  L2 ) (1  e 2 ( L1  L2 ) )

U sk 2 

(Vbi   2  bD  VDS )  (Vbi  bS  1 )e  ( L1  L2 )  ( 1   2 ) cosh(L2 ) e  ( L1  L2 ) (1  e 2 ( L1  L2 ) )

U sk 3  U sk 1e U sk 4  U sk 2 e

L1

L1

(  2 )  1 2 (   2 )  1 2

(18)

(19) (20)

(21) Furthermore, the electric field profile along the channel length can be determined by differentiating the surface potential. The lateral electric field can be written as d1 ( x, y )  U sk 1 exp(x)  U sk 2 exp(x) 0  x  L1 dx d ( x, y ) E2 ( x )  2  U sk 3 exp( ( x  L1 )  U sk 4 exp( ( x  L1 )) 0  x  L2 dx E1 ( x) 

Results and Discussion The Dual Material Gate (DMG) Schottky Barrier (SB) MOSFET has been simulated using Silvaco ATLAS. The activated models during simulation are band gap narrowing, drift-diffusion, universal Schottky tunneling, and FLDMOB, CONMOB and SRH model [20]. The Universal Schottky-tunneling model has been used to capture tunneling through the metal semiconductor junction. The drift-diffusion model is mainly responsible for carrier flow in the channel. Shockley–Read– Hall recombination is considered for minority recombination effects. Concentration dependent carrier mobility (CONMOB) model is also activated to detail the low-field mobility for the impurity doping concentration along with high-field mobility reduction model (FLDMOB). Fig. 3 shows surface potential along the channel length region for 80 nm channel length. The surface potentials of the DMG-SB-MOSFET are compared with that of SMG Schottky Barrier device. The metal gate work function for the M1 and M2 are taken in such a way that the metal work function of M1 should be higher than the work function of the M2 as shown in Fig. 1. The increase in surface potential under metal M1 increases the transport efficiency and carrier velocity, therefore an enhancement in drain current is observed from simulation. The modeled results match in close agreement with the simulated data for both SMG and DMG-SB-MOSFET.

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Fig. 3 Comparison between the surface potential distribution of the DMG SB-MOSFET and conventional SMG SB-MOSFET.

Fig. 4 Surface potential as a function of channel length positions, obtained from our model (lines) and simulations (symbols) with varying Vds and Vgs =0.6 V. The variation of the surface potential at a fixed gate source voltage(Vgs) for a gate length of 80nm have been shown in Fig. 4 for different drain source voltages(Vds). An appreciable increase of surface potential at the drain/channel side with Vds is observed.

Fig. 5 Surface potential distribution of the DMG SB-MOSFET with varying gate-source voltage.

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Fig. 5 shows the surface potential along the channel position for different gate bias at Vds = 50mV and it has been observed that the modeled results are identical with the simulation. The surface potential enhances with increasing the gate bias but the tunneling width at the source/channel interface decreases with increasing gate bias. Therefore, proper gate bias is required to reduce potential barrier tunneling width in the on-state. The comparison of the electric field distribution of the DMG SBMOSFET and SMG SB-MOSFET is shown in Fig. 6. The peak electric field occurs at the tunneling region, causes extra band bending and hence increases the tunneling of the carriers. The electric field profile of the DMG is more at the tunneling region due to the presence of work function difference at metal gate M1 and M2.

. Fig. 6 Electric field distribution of the DMG SB-MOSFET and the conventional single metal gate SB-MOSFET. Fig. 7 shows the impact of different channel length (30nm, 40nm, 50nm, 60nm and 80nm) on the surface potential. It has been observed that a large barrier gap is present at the drain channel junction and hence the ambipolariry is reduced. In smaller channel lengths, the carriers will tunnel from drain region to the channel which increases the ambipolarity. The analytical and simulated results almost match with each other.

Fig. 7 Effect of channel length scaling on the DMG SBMOSFET at Vgs = Vds =0.6V. Table. 1 On-state and off-state current as function of work function (gate metal (M2)) of DMG –SB Structure Metal M2 work function ( m 2 )

3.9(eV)

4.1(eV)

4.3(eV)

4.5(eV)

Ion(A/µm) Ioff(A/µm)

2.617E-5 2.97E-11

2.812E-5 8.627E-10

2.53E-5 6.631E-10

2.765E-5 2.236E-9

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Table. 2 DIBL Variation as a function of channel length (L) of SMG and DMG –SB Structure Channel length(nm) 50 100 150

SMG SB Device DIBL(V) 0.4972 0.076 0.072

DMG SB Device DIBL(V) 0.2832 0.059 0.055

Fig. 8 Energy band diagram of (a) DMG SB-MOSFET for different work functions ( m 2 ) of Gate Metal (M2) at Vds =0.6V and Vgs = -0.5 and (b) SMG SB-MOSFET gate work function = 4.3eV at Vds =0.6 and Vgs = -0.5V. Fig. 8 shows the impact on energy band diagram of DMG SB-MOSFET by varying Metal (M2) work function and keeping the Metal (M2) work function constant in the ambipolar-state (Vgs=-0.5V and Vds=0.1V). From the band diagram, we can observe that the decreasing work function for Metal (M2=3.9eV) the tunneling width at drain/channel junction enhanced, which leads to reduction of tunneling of carriers in ambipolar-state. However, increasing the work function for Metal (M2=4.5eV) in drain/channel junction tunneling width is reduced. Due to increasing the Metal (M2) work function the electric field around the drain/channel junction decreases. Whereas, in the on state region the variation in Metal (M2) work function brings no change in the band diagram as shown in Fig. 2(b). Furthermore, Fig. 8(b) shows the band diagram of SMG SB-MOSFET in ambipolar region (Vgs=-0.5V and Vds=0.1V) the tunneling width at drain/channel junction reduced, which leads to increase in tunneling of holes and provides more ambipolar current as shown in Fig. 9.

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Fig.9 Transfer characteristics of the DMG SB-MOSFET (Metal (M1) = 4.6 eV, Metal (M2) = 4.4 eV, and Vds = 0.6 V) and SMG-SB-MOSFET gate metal work function is 4.3 eV, and Vds = 0.6 V).

Fig.10 Transfer characteristics of the DMG SB-MOSFET at different gate Metal (M2) work function at Vds = 0.6V Fig. 9 show the transfer characteristics of the DMG and SMG SB-MOSFET at Vds =0.6V. The dual material gate device shows a reduced ambipolar- state current of 10-11 A/μm and single material gate device have higher ambipolar - state current of 10-5A/μm at Vds = 0.6V and Vgs = -0.5V. Whereas, the Ion current of DMG SB-MOSFET is similar to that of SMG SB-MOSFET (Ion=2.53x10-5A/ μm). Fig. 10 show the transfer characteristics of the DMG SB-MOSFET for different work function of Metal (M2). The variation of Metal (M2) work function from 4.5 to 3.9 eV, while keeping the Metal (M1) work function constant the ambipolar state current is reduced. However, the increase in ambipolar-state current with increasing of Metal (M2) greater than 4.5eV is due to reduced tunneling width at drain/channel junction. Moreover, in the on current no apparent change has been observed. The table.1 summarizes the variations of Ion/Ioff of DMG SB-MOSFET at a gate length 80nm as a function of different values of metal gate (M2) work function. The Ion/Ioff ratio improves with reduction M2 work function. Furthermore, table. 2 shows the DIBL as a function of different gate length. DMG SB-MOSFET suffers from less DIBL effect. Conclusion In the present work a two-dimensional analytical model for the surface potential distribution of DMG SB-MOSFET has been developed by solving two-dimensional Poisson’s equation using parabolic approximation and proper boundary conditions. The analytical surface potential model has been used to determination the electric field. The developed analytical model has close agreement with numerically calculated results. Furthermore, the DMG SB-MOSFET has decreased ambipolar-state current, improved SCEs like DIBL and high Ion/Ioff ratio as compared to SMG SB-MOSFET. References [1] J.M. Larson, J.P. Snyder, Overview and status of metal S/D Schottky-barrier MOSFET technology, IEEE Transactions on Electron Devices. 53 (2006) 1048–1058. doi:10.1109/TED.2006.871842. [2] W. Saitoh, A. Itoh, S. Yamagami, M. Asada, Analysis of short-channel Schottky source/drain metal-oxidesemiconductor field-effect transistor on silicon-on-insulator substrate and demonstration of sub-50-nm n-type devices with metal gate, Japanese Journal of Applied Physics. 38 (1999) 6226. [3] M. Zhang, J. Knoch, J. Appenzeller, S. Mantl, Improved Carrier Injection in Ultrathin-Body SOI Schottky-Barrier MOSFETs, IEEE Electron Device Letters. 28 (2007) 223–225. doi:10.1109/LED.2007.891258. [4] D.J. Frank, Y. Taur, H.-S. Wong, Generalized scale length for two-dimensional effects in MOSFETs, IEEE Electron Device Letters. 19 (1998) 385–387. [5] K. Matsuzawa, K. Uchida, A. Nishiyama, A unified simulation of Schottky and ohmic contacts, IEEE Transactions on Electron Devices. 47 (2000) 103–108. [6] K.-C. Lin, W.-W. Ding, M.-H. Chiang, An Analytical Gate-All-Around MOSFET Model for Circuit Simulation, Advances in Materials Science and Engineering. 2015 (2015) 1–5. doi:10.1155/2015/320320. [7] S. Xiong, T.-J. King, J. Bokor, A Comparison Study of Symmetric Ultrathin-Body Double-Gate Devices with Metal Source/Drain and Doped Source/Drain, IEEE Transactions on Electron Devices. 52 (2005) 1859–1867.

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Highlights 1. The analytical model is based on the solution of two-dimensional 2D Poisson’s equation in the channel for proposed DMG Schottky barrier MOSFET. 2. Channel lengths, different work function of gate material have been optimized to minimize the SCE of the device. 3. Suppressing of ambipolar leakage using DMG Schottky MOSFET 4. The improved Ioff is stated hence increased Ion/Ioff ratio is obtained.