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A comparison of the performance of plastic and ceramic encapsulations based on evaluation of CMOS integrated circuits
Microelectronics and Reliability,
Vot.16, pp. 251 to 254.PergamonPress,1977.Printedin Great~ritain
A COMPARISON OF THE PERFORMANCE OF PLASTIC AND CERAMIC ENCAPSULATIONS BASED ON EVALUATION OF CMOS INTEGRATED CIRCUITS M. J. Fox Motorola Limited, Semiconductor Products Division, East Kilbride, Glasgow, Scotland
INTRODUCTION
possible change in encapsulating process or materials. Examples of these could be: Changes in plastic material, Changes in lead frame material, Changes in cleaning procedures, Changes in die passivation, Moisture barrier materials. The second application of the test programme is in regular monitoring of the quality of standard product from Motorola's various factories and lines. In this context the tests are performed to a prescribed inspection level and LTPD to products from each relevant line at a frequency varying between weekly and bi-monthly as defined for the individual test. In addition the basic materials, plastic, bonding wire ,and lead frames are subject to inspection as incoming materials before acceptance for production. In the case of the plastic itself, for example, these tests include: mouldability, spiral flow, hardness and particle size.
The object of this paper is to indicate the situations in which the choice of plastic or hermetic encapsulation can be expected to have no influence on device reliability and to contrast those situations with others where there is a known and marked difference between the behaviour of devices made using the two packaging systems. Other papers in this programme deal in some detail with the applicable failure mechanisms, and yet others will discuss appropriate testing and screening procedures. If I can add anything to this programme, I hope that it is by indicating how the reliability of encapsulation systems has been continuously monitored in large volume production and discussing some results with which I am familiar. In particular, by using the illustration of my company's CMOS manufacture, where data is gathered in parallel in large quantities of both ceramic and plastic encapsulated integrated circuits I can draw comparisons between the two.
RESULTS MATERIALS AND METHODS
The choice of materials for plastic encapsulation is subject to compromise in terms of the properties required. The optimum solution may differ from family to family of devices, because of the different types of stress which are anticipated. Thus, in so far as the major limiting factors on the reliability of P E P s have appeared to be: (1) (Intermittent) open circuits between wire and die due to differential thermal expansion and (2) Degradation (normally aluminium corrosion) of the die due to ingress of moisture, then it is clear that a plastic power transistor will be operating in a much more severe environment in relation to the first factor than will a low power M O S integrated circuit. The latter on the other hand will be more sensitive to the chemical purity of the encapsulating material. Table 1 presents the programme of tests which are used within Motorola to evaluate the performance of plastic encapsulated devices. They are used in two contexts. The first is to evaluate any proposed or
Table 2 summarizes the results of long-term operating lifetests of Motorola CMOS devices in both plastic and ceramic encapsulations. The CL and CP ranges are identical in electrical specification and operating temperature range, and the lifetests were conducted under identical conditions. It will be seen that under these conditions of dry heat and applied bias the performance of the plastic devices is in no way inferior to that of their ceramic counterparts. In fact, the CP (plastic) results appear to be slightly the better of the two, but this is simply a reflection of the better statistical confidence of the results on CP devices, where a larger number of lifetest hours have been accumulated. Tables 3, 4 and 5 present the results of tests which could be expected to show up problems related to temperature coefficient mismatch. Table 4 shows the results of thermal shock by liquid immersion, performed between temperatures - 6 5 ° C and + 150°C, where the current evaluation programme requires 100 cycles. For the less severe thermal cycling in air a sequence of !000 cycles is required. Table 5 refers to Thermal Intermittency Tests, to expose the presence of any open circuit bonds due to thermally 251
252
M . J . Fox Table 1. Plastic package evaluation Test
Method
Subgroup BI Solderability Subgroup B2 Lead fatigue Subgroup B4 Physical dimensions Subgroup B5 Marking permanency Subgroup CI Thermal shock Temperature cycle End points Continuity Visual Subgroup C2 Mechanical shock Vibration, variable frequency Constant acceleration End points Continuity Visual Subgroup C3 Salt atmosphere Subgroup C4 Temperature/humidity bias End points d.c. and functional
MIL-STD 883A Condition or Procedure
2003.1
Temperature 260°C + 10°C omit aging
2004.1
Condition B2
2016
Per case outline drawing
2015
Resistance to solvent
1011.1 1010.1
Condition A (15 cycles) Condition A (15 cycles) All pins at 125°C 4- 5°C Any crack at 10 x magnification
2002.1 2007 2001.1
Condition B (YI axis only) Condition A (Y axis only) Condition E (YI axis only) All pins at 125°C + 5°C Any cracks at 10 x magnification
1009.1
Condition A 85°C 85~o r.h./10V 25°C go/no go read and record rejects at 168hours. 500 hours, 1000 hours, 1250 hours, 1500 hours. All pins at 125°C
Continuity
Table 2. Device series CL (ceramic) CP (plastic)
Operating voltage
85°C failure rate
15 V 10 V 15 V 10 V
0.161 ~/o/1000hrs 0.0125~o/1000 hrs 0.120~/J1000 hrs 0"008~/o/1000hrs
Table 3. Temperature cycle. The ai~-to~air temperature cycle is conducted in accordance with MIL-STD-883, Method 1010, Test Conditions B and C
\"
Lots
Condition
17 6
- 6 5 ° C to +150°C - 5 5 ° c to +125°c.
S/S
Device cycles
R~ects
1174 459 '
914,400 71~800
I 3
Table 4. Thermal shock. The liquid-to-liquid thermal shock is conducted in accordance.with MIL-STD-883, .Method 1011, Test Conditions B and C ." • Condition - 6 5 ° C to +150°C - 5 5 ° C to + 125°C 0°C to + 100°C
: . Lots 9 1 2
" S/S
Device cycles
Rejects
416 100 44
34,380 50,000 1980
0 0 0
Comparison Performance of Plastic and Ceramic encapsulations
253
Table 5. High temperature continuity test summary digital and linear No. of lots
Failures (opens) per lot
Total quantity
Percent failure
54 7 3 1 1 1 67
0 1 2 3 4 6 26
344,184 28,014 10,636 11,075 3360 3658 400,927
0.0065%
Total
* Total cumulative failures ambient temperature = 125°C.
generated mechanical stress. The temperature of the device is raised from room temperature to + 125°C and monitored throughout for continuity. Incidentally, this test is also one of the post-test end-points for the results presented in Tables 3 and 4. I submit that these results dispose satisfactorily of thermal intermittency, once a major limitation of PEDs. Whereas no detectable difference between the performance of plastic and ceramic encapsulated devices emerged from the results of dry-heat operating lifetests, a different picture appears if the combined effects of bias, temperature and humidity are considered. Figure 1 records the standard accelerated temperature/humidity/bias conditions which are used. Of these, the "85/85/10" test is a generally recognized stressing condition. The "Pressure Cooker Test" is also a widely utilized test, highly accelerated evaluation of humidity resistance but its relative lack of controlability makes it more useful on a semi-quantitive basis, for comparison of different processes or lots. For most early programmes the industry utilized the 85°C, 85% r.h. test without the simultaneous application of bias; this is a much less stringent test. Without bias only galvanic corrosion can occur, whereas the application of voltage provides the opportunity for electrolytic action. The mechanism appears to be as follows: Moisture present within the system or penetrating into the package reaches the die surface. A solution is formed.
which, when the device is biased provides an electrolytic cell resulting in corrosion of the aluminium connections at the cathodes, i.e. those connected to the more negative voltages. The mechanism has been found to determine the maximum life expectancy in a number of independent investigations, involving many different manufacturers' products. The cumulative failure rate as a function of running time can be represented on a Weibull probability chart and is found to give a linear relationship. As illustrated in Fig. 2, since the failure rate is not constant with time a convenient figure of merit is the time to 50~o failures. It is also possible to establish a relationship between the temperature and humidity to which the components are subjected and the timeto-failure. The two accelerating factors, temperature and humidity, can be represented as a vapour pressure in which case an Arrhenius expression results, such as is depicted graphically in Fig. 3. Awareness of this potential failure mechanism will suggest various aspects of the design and processing of the PED which are critical to its performance under extended periods of operation at high tempera° ture/humidity. Some key ones are listed in Fig, 4 and Fig. 5 is an iillustration of a standard lead frame showing features which are designed to increase the length of path of moisture entering the package and CMOS plastic Weibull probability chart Based on temperature hurnidi~y bias testing 85°C/85%RH/IOV
Pressure temperature humidity bias vs temperature humidity bias 99.5, 99'9 f 95
.g 9o ~
PTHB 15psig
/
/
813
~ 4C 5o ._~
3G
"~ 2o 5
99,C 90£ , 70 C Medmn ~'" life 150,0 30C ~
THB
IO.( 6.( 4.c
85*C, 80%RH
2c
~ ~
0.~ 0.' 0.2
f
O. O.IN 0.0~
0.02 7891 0.1
I
i
I00
I000 Test hours
Fig. I.
I00
I1~ 2
I
I000 Age at failure,
Fig. 2.
hr
5 4 5 67091 10000
254
M.J. Fox /Die
CMOS plastic time to 5 0 % failures for THB testin(
J- -u o
/
pad
support
o
20 yr~.
15 yr',
[[~[~) ~ _ f i l l _ ~ ( l ~
~ _ _ Leadlock
5 yr.c
~
~ l t ~ ] ~ ~
Lead°ffsets
104 E
Fig. 5.
BO
I I
70
I
60
I
LI
50
40
I
I
30
I
20
I0
mE
I / (Vp- K)
Fig. 3. to resist separation of the plastic and metal by mechanical or thermally induced mechanical stresses. In the course of the manufacturing history of CMOS in plastic at Motorola certain refinements have been made to the process in the light of the factors described in Fig. 4.
Accelerated temperature/humidify/bias evaluationof plastic devices Factors affecting performanceThermalexpansioncharacteristicsof leadframe,wire, die andplastic Purityof encapsulant Adhesionof encapsulant. Shapeand dimensionsof lead frame. * Integrity of die passivationlayer. * Control of die passivationphosphoruscontent Fig. 4.
Although none of these were major material or process changes the improvement in performance under temperature/humidity/bias conditions can be seen from Fig. 2, giving the experimental data gathered up to early 1974, and up to early 1976. In summary: (1) Thermal intermittency as a problem is demonstrably avoided by correct choice of materials. (2) Under conditions of low humidity the results of extensive operating lifetests (in Motorola's case for CMOS, approximately 70 million device hours) show no inferiority in the performance of plastic devices relative to their hermetic counterparts. (3) Plastic encapsulated integrated circuits are, however, subject to a wear-our mechanism of aluminium corrosion by moisture which limits their life expectancy under operating conditions of combined high temperature and humidity. The published performance data extrapolated to more benign conditions should be compared with the operating conditions and life expectancy requirements of the individual application. Acknowledgements--This paper was read at the Royal Signals & Radar Establishment Symposium on Plastic encapsulated semiconductor devices Jot military use. May 18-19
1976, with acknowledgements t o RSRE and Motorola Limited.
Vot.16, pp. 251 to 254.PergamonPress,1977.Printedin Great~ritain
A COMPARISON OF THE PERFORMANCE OF PLASTIC AND CERAMIC ENCAPSULATIONS BASED ON EVALUATION OF CMOS INTEGRATED CIRCUITS M. J. Fox Motorola Limited, Semiconductor Products Division, East Kilbride, Glasgow, Scotland
INTRODUCTION
possible change in encapsulating process or materials. Examples of these could be: Changes in plastic material, Changes in lead frame material, Changes in cleaning procedures, Changes in die passivation, Moisture barrier materials. The second application of the test programme is in regular monitoring of the quality of standard product from Motorola's various factories and lines. In this context the tests are performed to a prescribed inspection level and LTPD to products from each relevant line at a frequency varying between weekly and bi-monthly as defined for the individual test. In addition the basic materials, plastic, bonding wire ,and lead frames are subject to inspection as incoming materials before acceptance for production. In the case of the plastic itself, for example, these tests include: mouldability, spiral flow, hardness and particle size.
The object of this paper is to indicate the situations in which the choice of plastic or hermetic encapsulation can be expected to have no influence on device reliability and to contrast those situations with others where there is a known and marked difference between the behaviour of devices made using the two packaging systems. Other papers in this programme deal in some detail with the applicable failure mechanisms, and yet others will discuss appropriate testing and screening procedures. If I can add anything to this programme, I hope that it is by indicating how the reliability of encapsulation systems has been continuously monitored in large volume production and discussing some results with which I am familiar. In particular, by using the illustration of my company's CMOS manufacture, where data is gathered in parallel in large quantities of both ceramic and plastic encapsulated integrated circuits I can draw comparisons between the two.
RESULTS MATERIALS AND METHODS
The choice of materials for plastic encapsulation is subject to compromise in terms of the properties required. The optimum solution may differ from family to family of devices, because of the different types of stress which are anticipated. Thus, in so far as the major limiting factors on the reliability of P E P s have appeared to be: (1) (Intermittent) open circuits between wire and die due to differential thermal expansion and (2) Degradation (normally aluminium corrosion) of the die due to ingress of moisture, then it is clear that a plastic power transistor will be operating in a much more severe environment in relation to the first factor than will a low power M O S integrated circuit. The latter on the other hand will be more sensitive to the chemical purity of the encapsulating material. Table 1 presents the programme of tests which are used within Motorola to evaluate the performance of plastic encapsulated devices. They are used in two contexts. The first is to evaluate any proposed or
Table 2 summarizes the results of long-term operating lifetests of Motorola CMOS devices in both plastic and ceramic encapsulations. The CL and CP ranges are identical in electrical specification and operating temperature range, and the lifetests were conducted under identical conditions. It will be seen that under these conditions of dry heat and applied bias the performance of the plastic devices is in no way inferior to that of their ceramic counterparts. In fact, the CP (plastic) results appear to be slightly the better of the two, but this is simply a reflection of the better statistical confidence of the results on CP devices, where a larger number of lifetest hours have been accumulated. Tables 3, 4 and 5 present the results of tests which could be expected to show up problems related to temperature coefficient mismatch. Table 4 shows the results of thermal shock by liquid immersion, performed between temperatures - 6 5 ° C and + 150°C, where the current evaluation programme requires 100 cycles. For the less severe thermal cycling in air a sequence of !000 cycles is required. Table 5 refers to Thermal Intermittency Tests, to expose the presence of any open circuit bonds due to thermally 251
252
M . J . Fox Table 1. Plastic package evaluation Test
Method
Subgroup BI Solderability Subgroup B2 Lead fatigue Subgroup B4 Physical dimensions Subgroup B5 Marking permanency Subgroup CI Thermal shock Temperature cycle End points Continuity Visual Subgroup C2 Mechanical shock Vibration, variable frequency Constant acceleration End points Continuity Visual Subgroup C3 Salt atmosphere Subgroup C4 Temperature/humidity bias End points d.c. and functional
MIL-STD 883A Condition or Procedure
2003.1
Temperature 260°C + 10°C omit aging
2004.1
Condition B2
2016
Per case outline drawing
2015
Resistance to solvent
1011.1 1010.1
Condition A (15 cycles) Condition A (15 cycles) All pins at 125°C 4- 5°C Any crack at 10 x magnification
2002.1 2007 2001.1
Condition B (YI axis only) Condition A (Y axis only) Condition E (YI axis only) All pins at 125°C + 5°C Any cracks at 10 x magnification
1009.1
Condition A 85°C 85~o r.h./10V 25°C go/no go read and record rejects at 168hours. 500 hours, 1000 hours, 1250 hours, 1500 hours. All pins at 125°C
Continuity
Table 2. Device series CL (ceramic) CP (plastic)
Operating voltage
85°C failure rate
15 V 10 V 15 V 10 V
0.161 ~/o/1000hrs 0.0125~o/1000 hrs 0.120~/J1000 hrs 0"008~/o/1000hrs
Table 3. Temperature cycle. The ai~-to~air temperature cycle is conducted in accordance with MIL-STD-883, Method 1010, Test Conditions B and C
\"
Lots
Condition
17 6
- 6 5 ° C to +150°C - 5 5 ° c to +125°c.
S/S
Device cycles
R~ects
1174 459 '
914,400 71~800
I 3
Table 4. Thermal shock. The liquid-to-liquid thermal shock is conducted in accordance.with MIL-STD-883, .Method 1011, Test Conditions B and C ." • Condition - 6 5 ° C to +150°C - 5 5 ° C to + 125°C 0°C to + 100°C
: . Lots 9 1 2
" S/S
Device cycles
Rejects
416 100 44
34,380 50,000 1980
0 0 0
Comparison Performance of Plastic and Ceramic encapsulations
253
Table 5. High temperature continuity test summary digital and linear No. of lots
Failures (opens) per lot
Total quantity
Percent failure
54 7 3 1 1 1 67
0 1 2 3 4 6 26
344,184 28,014 10,636 11,075 3360 3658 400,927
0.0065%
Total
* Total cumulative failures ambient temperature = 125°C.
generated mechanical stress. The temperature of the device is raised from room temperature to + 125°C and monitored throughout for continuity. Incidentally, this test is also one of the post-test end-points for the results presented in Tables 3 and 4. I submit that these results dispose satisfactorily of thermal intermittency, once a major limitation of PEDs. Whereas no detectable difference between the performance of plastic and ceramic encapsulated devices emerged from the results of dry-heat operating lifetests, a different picture appears if the combined effects of bias, temperature and humidity are considered. Figure 1 records the standard accelerated temperature/humidity/bias conditions which are used. Of these, the "85/85/10" test is a generally recognized stressing condition. The "Pressure Cooker Test" is also a widely utilized test, highly accelerated evaluation of humidity resistance but its relative lack of controlability makes it more useful on a semi-quantitive basis, for comparison of different processes or lots. For most early programmes the industry utilized the 85°C, 85% r.h. test without the simultaneous application of bias; this is a much less stringent test. Without bias only galvanic corrosion can occur, whereas the application of voltage provides the opportunity for electrolytic action. The mechanism appears to be as follows: Moisture present within the system or penetrating into the package reaches the die surface. A solution is formed.
which, when the device is biased provides an electrolytic cell resulting in corrosion of the aluminium connections at the cathodes, i.e. those connected to the more negative voltages. The mechanism has been found to determine the maximum life expectancy in a number of independent investigations, involving many different manufacturers' products. The cumulative failure rate as a function of running time can be represented on a Weibull probability chart and is found to give a linear relationship. As illustrated in Fig. 2, since the failure rate is not constant with time a convenient figure of merit is the time to 50~o failures. It is also possible to establish a relationship between the temperature and humidity to which the components are subjected and the timeto-failure. The two accelerating factors, temperature and humidity, can be represented as a vapour pressure in which case an Arrhenius expression results, such as is depicted graphically in Fig. 3. Awareness of this potential failure mechanism will suggest various aspects of the design and processing of the PED which are critical to its performance under extended periods of operation at high tempera° ture/humidity. Some key ones are listed in Fig, 4 and Fig. 5 is an iillustration of a standard lead frame showing features which are designed to increase the length of path of moisture entering the package and CMOS plastic Weibull probability chart Based on temperature hurnidi~y bias testing 85°C/85%RH/IOV
Pressure temperature humidity bias vs temperature humidity bias 99.5, 99'9 f 95
.g 9o ~
PTHB 15psig
/
/
813
~ 4C 5o ._~
3G
"~ 2o 5
99,C 90£ , 70 C Medmn ~'" life 150,0 30C ~
THB
IO.( 6.( 4.c
85*C, 80%RH
2c
~ ~
0.~ 0.' 0.2
f
O. O.IN 0.0~
0.02 7891 0.1
I
i
I00
I000 Test hours
Fig. I.
I00
I1~ 2
I
I000 Age at failure,
Fig. 2.
hr
5 4 5 67091 10000
254
M.J. Fox /Die
CMOS plastic time to 5 0 % failures for THB testin(
J- -u o
/
pad
support
o
20 yr~.
15 yr',
[[~[~) ~ _ f i l l _ ~ ( l ~
~ _ _ Leadlock
5 yr.c
~
~ l t ~ ] ~ ~
Lead°ffsets
104 E
Fig. 5.
BO
I I
70
I
60
I
LI
50
40
I
I
30
I
20
I0
mE
I / (Vp- K)
Fig. 3. to resist separation of the plastic and metal by mechanical or thermally induced mechanical stresses. In the course of the manufacturing history of CMOS in plastic at Motorola certain refinements have been made to the process in the light of the factors described in Fig. 4.
Accelerated temperature/humidify/bias evaluationof plastic devices Factors affecting performanceThermalexpansioncharacteristicsof leadframe,wire, die andplastic Purityof encapsulant Adhesionof encapsulant. Shapeand dimensionsof lead frame. * Integrity of die passivationlayer. * Control of die passivationphosphoruscontent Fig. 4.
Although none of these were major material or process changes the improvement in performance under temperature/humidity/bias conditions can be seen from Fig. 2, giving the experimental data gathered up to early 1974, and up to early 1976. In summary: (1) Thermal intermittency as a problem is demonstrably avoided by correct choice of materials. (2) Under conditions of low humidity the results of extensive operating lifetests (in Motorola's case for CMOS, approximately 70 million device hours) show no inferiority in the performance of plastic devices relative to their hermetic counterparts. (3) Plastic encapsulated integrated circuits are, however, subject to a wear-our mechanism of aluminium corrosion by moisture which limits their life expectancy under operating conditions of combined high temperature and humidity. The published performance data extrapolated to more benign conditions should be compared with the operating conditions and life expectancy requirements of the individual application. Acknowledgements--This paper was read at the Royal Signals & Radar Establishment Symposium on Plastic encapsulated semiconductor devices Jot military use. May 18-19
1976, with acknowledgements t o RSRE and Motorola Limited.