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Performance evaluation of ultra-thin gate-oxide CMOS circuits
Solid-State Electronics 48 (2004) 551–559 www.elsevier.com/locate/sse
Performance evaluation of ultra-thin gate-oxide CMOS circuits Alessandro Marras *, Ilaria De Munari, Davide Vescovi, Paolo Ciampolini Dip. di Ing. dell’Informazione, Universita di Parma, Parco Area delle Scienze 181/A, 43100 Parma, Italy Received 15 May 2003; received in revised form 3 July 2003; accepted 18 September 2003
Abstract Gate currents are becoming a major concern for ULSI circuit designers. A standard circuit design flow that takes into account such effects is needed in order to take advantage from nanometer-sized devices performance. Some suggestions on how to approach permeable-gate-device circuit simulation are proposed in this paper, focusing on gatecurrent-related effects on circuit performance. A simple, yet complete, standard CMOS circuit has been designed and its functional and performance indices have been evaluated, depending on the actual oxide thickness. To correlate performance directly to the fabrication parameters, a mixed-mode approach using both physical and circuit simulations has been adopted. Model parameters were calibrated on actual measurements. Simulation results have been compared for ideal- and permeable-gate devices. Although circuit functionality is not affected (within the considered technology range, at least), significant performance alterations are highlighted. 2003 Elsevier Ltd. All rights reserved. Keywords: Thin oxide; Direct tunneling; Gate current; CMOS; Circuit analysis
1. Introduction As the channel feature-size of IC technology decreases, scaling rules impose the thinning of the gate dielectric, down to the limit at which gate-leakage current become significant. According to the last revision of the International Technology Roadmap for Semiconductors (ITRS) oxide thickness in the order of 1 nm will be used in 2004–2005 for ultra-short CMOS [1]. Several limiting factors associated with ultra-thin gate oxides have been reported in literature [2,3]; among them, direct tunneling current exponentially depends on the oxide thickness and becomes relevant (i.e., non-negligible with respect to the drain–source current) when gate oxide decreases below 2 nm. In this paper, we focus on the influence of such currents on the behavior and performance of integrated systems, by investigating the circuit response of aggressively scaled-down circuits.
Direct-tunneling gate currents have been extensively studied, with reference to basic devices [4,5], or elementary circuit building blocks [6]. However, when gate currents come into play, coupling among interconnected circuit stages becomes more complex, and a more comprehensive modelling approach may be needed. Here, the simulation of a complete functional unit is discussed; a CMOS ring oscillator has been considered: the interaction between cascaded stages due to the gate current can be taken into account, whereas the circuit is still simple enough to allow for intuitive interpretation of the analysis results. In Section 2 below, a few details on the designed circuit, as well as on the reference fabrication technology, are given. Simulation tools and models are described in Section 3, whereas results are presented and discussed in Section 4; conclusions are drawn in Section 5.
2. Circuit design and technology *
Corresponding author. Tel.: +39-0521-905811; fax: +390521-905822. E-mail address: [email protected] (A. Marras).
A CMOS ring oscillator has been designed and simulated; actual fabrication is under way at the time of
0038-1101/$ - see front matter 2003 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2003.09.028
A. Marras et al. / Solid-State Electronics 48 (2004) 551–559
writing, at LETI facilities (Grenble, F). Details on the fabrication process are given in [7]: such a process allows for channel lengths down to 50 nm: nevertheless, in the following, fairly longer devices (200 nm) have been considered, to make discussion independent of too severe short-channel and punch-through effects. Test devices used for model calibration featured oxide thickness ranging from 2.2 nm down to 1.3 nm (even thinner SiO2 layers are actually being used in advanced production technologies [8]). A wider thickness range was modelled by extrapolating actual device measures. Appropriate doping profiles were inferred from experiments and information from the foundry. Device measures, used for model characterization have been performed directly at LETI and at the University of Udine, mostly on nMOS devices: measures of pMOS devices were not available, so that pMOS transistors have been fully characterized on the basis of simulation results. To this purpose, geometrical and physical parameters characterizing the CMOS fabrication process at hand were taken into account. Several CMOS oscillators were designed, in order to figure out which factors (device size, chain length, etc.) would emphasize gate-current impact on circuit performance; both dynamic and static behaviour have been considered, by properly controlling the feedback path.
3. Simulation models and circuit application In order to evaluate the performance of the oscillator, a comprehensive set of circuit simulations have been carried out, by using commercial CAD tools such as ELDO or SPECTRE. To this purpose, a compact MOSFET model, capable of taking into account the gate-leakage currents, should be adopted and properly characterized. Largely used compact models actually exist, which allow to perform circuit simulation of permeable-gate devices (most notably, Berkeley’s BSIM4 [9]): however, their formulation usually involves an extensive set of parameters, which not necessarily have a straightforward physical meaning and thus need to be fitted on actual device measurement. This makes these models unpractical for the prediction of technologyrelated performance. For this reason, a more physically oriented modelling strategy was adopted. A mixed-mode approach was exploited to this purpose: device simulation (in particular, DESSIS ISE-TCAD software [10]) was extensively used to characterize devices, investigating dependencies on main technological parameters. Full sets of current–voltage ðID ðVG ; VD ; VS Þ; IG ðVG ; VD ; VS ÞÞ characteristics were computed, and validated against available experimental results. Curves were then extrapolated and parametrized with respect to oxide thickness. Eventually, device simulation results have been transferred to the compact model used for circuit
D IGD(VGS,VDS ) physical simulation
EKV
G
B
IGS(VGS,VDS ) IGB(VGS,VDS ) S Fig. 1. Sketch of the macro-circuit model defined.
simulation, the basic scheme of which is illustrated in Fig. 1. The model core is the conventional (i.e., not accounting for gate current) EKV model [11]: parameters were extracted from measurements (when actual device prototypes were available) or from device simulation (for projected technologies). Gate current, instead, has been introduced by means of the set of additional voltage-controlled current sources shown in Fig. 1. Current sources have been implemented as HDL (Hardware Description Language) blocks, describing distinct gate-current components, as previously modelled by DESSIS simulations. An overall good fit was obtained indeed for the technologies at hand as shown, for instance, in Figs. 2–4. Here, for the sake of conciseness, only data for a given device size are reported: the numerical model has actually been preliminarily validated on the whole range of device sizes investigated below. pMOS gate currents, predicted from the simulation, are instead reported in Fig. 5. Although such an approach is computationally expensive, and hence unpractical for routinely performing complex
I G (nA)
552
80 70 60 50 40 30 20 10 0
measurement simulation
VDS
0.0
0.5 1.0 VGS (V)
1.5
Fig. 2. Comparison between simulations and measurements performed on a 10 lm · 0.2 lm, 1.5 nm gate-oxide nMOS device: gate current (IG ) vs. gate–source voltage ðVGS Þ@VDS ¼ 0:1 V, 0.5 V, 1.0 V, 1.5 V.
A. Marras et al. / Solid-State Electronics 48 (2004) 551–559
553
2.5 1.5
measurement simulation
2.0
IG (nA)
I D (mA)
1.0
VDS
1.5 1.0
0.5
|VDS|
0.5 0.0
0.0 0.0
0.5
1.0
1.5
0.0
0.5
VGS (V) Fig. 3. Comparison between simulations and measurements performed on a 10 lm · 0.2 lm, 1.5 nm gate-oxide nMOS device: drain current (ID ) vs. gate–source voltage ðVGS Þ@VDS ¼ 0:1 V, 0.5 V, 1.0 V, 1.5 V.
45
physical model circuit model
40
C (pF)
35 30 25 20 15 10 5 0.0
0.5 1.0 VGS (V)
1.0
1.5
VSG (V)
1.5
Fig. 4. Comparison between physically simulated and circuitmodel-simulated gate capacitance for a 10 lm · 0.2 lm, 1.5 nm gate-oxide nMOS device.
circuit simulations, it allows for straightforward correlation of gate-leakage currents with main fabrication parameters, and make it possible to extrapolate results even for hypothetical technologies, for which an experimental characterization is not yet available. Moreover, straightforward evaluation of the gate-current impact on the overall circuit performance can be easily achieved by comparing results obtained with additional gate-current sources switched on and off, respectively.
Fig. 5. Simulated behaviour of a 10 lm · 0.2 m, 1.5 nm gateoxide pMOS device: gate current (IG ) vs. source–gate voltage ðVSG Þ@VDS ¼ 0:1 V, )0.45 V, )0.8 V, )1.15 V, )1.5 V.
based study of a complete ring-oscillator circuit has been carried out: aiming at evaluating main merit figures (average power consumption (P ), logic swing (LS), Noise Margin (NM), oscillation frequency (f )) and their dependence on oxide thickness (tox ) and gate-leakage current (IG ). Results underline that, due to gate-leakage effects, even the basic properties of standard CMOS gates are to be reconsidered. Gate current, in fact, typically flows from the input of one gate into the output of the preceding one (or vice versa), thus introducing static coupling between cascaded stages. Thus, strictly speaking, logic gates are no longer ratioless, since areadependent gate currents coming from adjacent gates may contrast pull-up and pull-down networks (Fig. 6). This, in principle, may lead, when aggressively scaled-down oxides are used, to the need of revising device-sizing criteria used in conventional CMOS architectures.
VL
VH
VL
VH
4. Discussion Once the model illustrated in previous section has been validated against measurements, the simulation-
Fig. 6. Sketch describing gate-current-related coupling effects.
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4.1. Power dissipation Tunneling current effects enhances circuit average power dissipation: in Fig. 7, circuit simulated responses for permeable-gate and ideal-gate devices at different oxide thicknesses are compared. The absolute variation of average power dissipation DP has been found to depend on tox in an exponential way: DP ¼ AP expðBtox Þ where parameters AP and B have been fitted on simulation results. As shown in Fig. 8, this relationship is similar to the dependency of static gate currents on oxide thickness:
Average Power (mW)
25
permeable ideal
20 15 10 5 0 0.8
1.0
1.2
1.4
1.6
tox (nm) Fig. 7. Whole circuit average power dissipation as a function of oxide thickness. Data refer to a 101-stages ring oscillator composed of 10 lm · 200 nm devices, at constant power supply (Vdd ¼ 1:5 V). Triangles represent permeable-gate circuit behaviour, while circles are related to ideal ones.
∆P (µW)
100
10
10
1
1
IG (µA)
∆P IG exponential fitting
100
0.1
0.1 0.9
1.1 1.3 tox (nm)
1.5
Fig. 8. Absolute average power variation (due to a single stage) between permeable and ideal case vs. oxide thickness @ Vdd ¼ 1:5 V. Data for a ring oscillator designed using 10 lm · 200 nm devices. For comparison, gate current has also been reported.
Table 1 Fitting parameters describing exponential behaviour for a 101stages ring oscillator composed of 10 lm · 200 nm devices, at constant power supply (Vdd ¼ 1:5 V) DP DLS DVOH DVOL Df IG
A
B
30 W 20.5 KV 15 KV 5.5 KV 600 GHz 37 lA
1.3 · 1010 1.3 · 1010 1.3 · 1010 1.3 · 1010 1.3 · 1010 1.3 · 1010
m1 m1 m1 m1 m1 m1
IG ¼ AG expðBtox Þ In particular, the damping factor B is the same, making it evident the straightforward correlation between static gate-current and average power increase. Fitting parameters are reported in Table 1 for a 101-stages ring oscillator composed of 10 lm · 200 nm (W L) devices, at constant power supply (Vdd ¼ 1:5 V). In the CMOS ideal case, power dissipation is usually dominated by the frequency-dependent, dynamic contribution of the capacitive load current. Here, instead, additional contributions, both dynamic and static, come from the gate currents exchanged with adjacent stages: in the case at hand, actually, static component becomes dominant. In fact, due to the relatively long inverter chain analysed (101 stages), switching at each stage takes only a small fraction of the oscillating period: we can thus estimate the static power consumption for a n-stages oscillator by assuming that n=2 nMOSFET’s and n=2 pMOSFET’s are in the on-state. The static power dissipated by each stage (PS ) thus reads: PS ¼ ðIG;n þ IG;p Þ Vdd =2 where IG;n and IG;p are the asymptotic values of current tunneling through nMOSFET and pMOSFET, respectively. By comparing PS with the increase of the overall power DP (Table 2), it is confirmed that such an increase is mostly to be ascribed to static power consumption. Such a contribution may easily exceed dynamic power, thus deeply affecting the way CMOS power constraints are customarily taken into account. As this static comTable 2 Single-stage average power variation between permeable-gate and non-permeable-gate (DP ) and static power consumption (PS ) as a function of the oxide thickness tox (nm)
DP (lW)
PS (lW)
1.5 1.3 1.1 0.9
0.078 1.432 15.406 228.386
0.060 1.446 15.800 233.570
A. Marras et al. / Solid-State Electronics 48 (2004) 551–559
1
W= 1µm W= 10 µm
∆P (µW)
relative variation
100
10
∆f/f ∆ LS/LS ∆P/P
0.1
0.01 0.9
1.1
555
1.3
1.5
1
2
6
8 10
W (µm)
Vdd (V) Fig. 9. Absolute average power variation (due to a single stage) between permeable and ideal case vs. supply voltage. Data for a 101-stages ring oscillator composed of 10 lm · 200 nm devices with a 0.9 nm gate oxide (crosses), and for another 101-stages ring oscillator composed of narrower (1 lm · 200 nm) devices with a 0.9 nm gate oxide (circles).
4
Fig. 10. Ring oscillator performance variation (normalized values) between permeable and ideal case vs. device width when using 0.9 nm gate oxide devices @ Vdd ¼ 0:9 V.
1.0
4.2. Logic swing degradation As observed in the preliminary remarks above, gate currents now flow into pull-up and pull-down networks of neighbouring logic gates. The situation is sketched in
0.8
∆P/P
ponent depends on coupling effects between cascaded stages, an estimation of dissipated power based on a single-stage stand-alone analysis would neglect it, giving far lower values. In a relative sense, lowering the supply voltage does not modify the picture: both components (static and dynamic) decrease, and the ratio between them is not significantly affected (Fig. 9). At 0.9 nm oxide-thickness, 0.9 V power supply, 87.5% of the dissipated power still comes from static gate currents. Since gate current depends on the gate area (and thus is proportional to the channel width W ), using narrower devices significantly reduces static power dissipation (Fig. 9). However, when decreasing channel width, dynamic power dissipation is also reduced, as a consequence of a lower drain current. For this reason the relative weight of the leakage-related power component remains basically the same, as it is shown in Fig. 10. Power dependence on the ring length also confirms that the nature of the power increase is static. Power contribution due to switching transients, in fact, is mainly dynamic: by shortening the inverter chain, the switching transient time becomes a more relevant fraction of the oscillation period, thus reducing the relative weight of static dissipation, as shown in Fig. 11. Nevertheless, even for very short chains, gate-current impact remains not negligible at all.
0.6 0.5 0.3 21
41
61
81
101
number of stages Fig. 11. Static power contribution to global dissipation (normalized values) vs. chain length for a ring oscillator using 1 lm · 200 nm, 0.9 nm gate oxide devices @ Vdd ¼ 0:9 V.
Fig. 6: due to the static currents flowing through gate dielectric in adjacent stages, a voltage drop occurs at the pull-up or pull-down devices, thus reducing the overall swing. Thus, node voltages depend on the ratio between on-state-MOSFET drain current (ID ) and area-depending gate current tunneling through oxide (IG ). Off-state devices also contribute to gate current because of electrons flowing from drain overlap diffusion to polysilicon gate; however, simulations shows that such a contribution is actually negligible, with respect to gate current coming from switched-on devices; literature [12] confirm such an expectation. Voltage drops at the channel is basically ohmic in this current range, so that, by comparing performance of the actual (i.e., leaky-gate) circuit with ideal one, an
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exponential dependence of the swing lowering (DLS) on the oxide thickness is found in this case too:
0.1
as shown in Fig. 12; fitting parameters are reported in Table 1. As a consequence, noise margins degrade as well: Fig. 13 shows lowering of both margins. The effect is slightly more pronounced on the high-level margin: this can be understood by looking at Fig. 14, which refers to the actual shift in high and low values; as illustrated in Fig. 6, VOH decreases due to the channel voltage drop originated by an n-channel device gate current, whereas VOL increase is due to a p-channel device gate current. Since
∆LS IG exponential fitting
2
10
1
∆VL ∆VH exponential fitting
-0.1
-0.2
0.9
1.1
1.3
1.5
tox (nm) Fig. 14. High (DVOH , triangles) and low (DVOL , squares) logic values variations between the permeable and the ideal cases vs. oxide thickness.
5
10
4
10
2
-1
10
-2
10
-3
10
-4
10
10
IG (µ A)
3
0
10
1
10
0
10
-1
10
0.9
1.1 1.3 tox (nm)
1.5
Fig. 12. Ring oscillator absolute logic swing variation between permeable and ideal case vs. oxide thickness @ Vdd ¼ 1:5 V when using 10 lm · 200 nm devices. For comparison, the gate current vs. oxide thickness has also been reported.
700 Noise Margin (mV)
0.0
10
10 ∆LS (mV)
∆VH , ∆VL (V)
DLS ¼ ALS expðBtox Þ
600 500 High Noise Margin Low Noise Margin ideal case
400 0.9
1.1
1.3 tox (nm)
1.5
Fig. 13. Permeable- and ideal-device ring oscillator Noise Margins (high and low) vs. oxide thickness. Data refer to a 101stages ring oscillator composed of 10 lm · 200 nm (pMOS) and 5 lm · 200 nm (nMOS) devices, at constant power supply (Vdd ¼ 1:5 V).
tunnel probability exponentially depends on the inverse pffiffiffiffi of the carrier effective mass (Prtunnel / expð mÞ, [13]), nMOS gate current (for a given bias) is appreciably larger than pMOS gate current (at equivalent bias). Furthermore, the (larger) nMOS gate current flows on the pMOS, pull-up network (usually more resistive), whereas (smaller) pMOS gate current flows on the nMOS (usually less resistive) pull-down network. Again, exponential dependence of this effect on the oxide thickness is found: DVOH ¼ AOH expðBtox Þ
DVOL ¼ AOL expðBtox Þ where AOH , AOL and B are fitting parameters (Table 1). In the worst case analysed, a 14% logic swing reduction was found. By scaling-own supply voltage as well (Fig. 15), a 7% decrease is still found. Although channel resistance depends on the channelwidth W , scaling-down homogeneously W in the whole circuit does not imply significant change in the overall balance: narrowing device channels increases on-state channel resistance; at the same time, however, gate current decreases with gate area, and thus with W , so that the voltage drop is almost invariant, as shown in Fig. 10. It is worth stressing again the inherent coupling between adjacent stages arising from gate-currents: currents flowing through channel and gate oxide resistances in Fig. 6 depend, in turn, on the actual voltage/ current regimes in the preceding and subsequent stages. Thus, also due to feedback, the (simpler) analysis of a single stage cannot reliably predict the actual swing reduction, as shown in Fig. 16.
A. Marras et al. / Solid-State Electronics 48 (2004) 551–559
70
Frequency (MHz)
∆ LS
1
0.1
0.01 0.8
557
60 50 40 30 20 0.8
1.0
1.2
1.4
permeable ideal
1.0
Vdd (V) Fig. 15. Absolute logic swing variation vs. supply voltage. Data refer to a 101-stages ring oscillator composed of 10 lm · 200 nm devices with a 0.9 nm gate oxide.
1.2
1.4
1.6
tox (nm)
1.6
Fig. 17. Frequency vs. oxide thickness. Data refer to a 101stages ring oscillator composed of 10 lm · 200 nm devices, at constant power supply (Vdd ¼ 1:5 V). Triangles represent permeable-gate circuit behaviour, while circles are related to ideal ones.
1.50
LS (V)
I G pmos
I D pmos
1.46 1.42
single stage analysis full chain analysis
1.38
I D nmos
C
I G nmos
1.34 1.30 0.8
1.0
1.2
1.4
1.6
tox (nm) Fig. 16. Logic swing predictions from a single-stage and a fullcircuit analysis vs. oxide thickness @ Vdd ¼ 1:5 V for a ring oscillator designed using 10 lm · 200 nm devices.
4.3. Frequency shift In principle, by reducing the oxide thickness, an increase of the oscillating frequency can be expected anyway (since no threshold-voltage adjustment is accounted for, drain-current increase overcompensates the output capacitance increase); if gate currents are taken into account, anyway, such an increase is actually more pronounced, as shown in Fig. 17. In this case, influence of gate currents is more complicated: from the one hand, in fact, oxide thinning leads to an increase of drain currents; on the other hand, however, gate and drain currents depend on the input and output node swings, which suffer from the degradation discussed above. Moreover, gate currents sum up with drain ones,
Fig. 18. Schematic of currents charging and discharging gate capacitance of a logic block: pMOSFET drain current (ID pmos), pMOSFET gate current (IG pmos), nMOSFET gate current (IG nmos), nMOSFET drain current (ID nmos).
according to the scheme depicted in Fig. 18; depending on the actual transient phase, gate current may speed-up or slow-down the transient itself. For instance, different current components are extracted from the simulation and shown in Fig. 19, with reference to a pull-up transient: in this case, the most significant parasitic component appears to be the gate current flowing through the nMOS of the downstream-inverter, which competes with pull-up current coming from the pMOS of the preceding inverter. The combined influence of these effects does not lends itself to a straightforward, simple interpretation; again, however, frequency shift can be empirically modelled by means of an exponential trend: Df ¼ Af expðBtox Þ where Af and B are reported in Table 1.
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1.4 I D nmos I D pmos I G nmos I G pmos
1.2
I (mA)
1.0 0.8 0.6 0.4 0.2 0.0 3.506
3.507
3.508
3.509
t (µsec) Fig. 19. Drain and gate currents charging/discharging a node during a VL ! VH transition. Data refer to a 101-stages ring oscillator composed of 10 lm · 200 nm devices with a 0.9 nm gate oxide @ Vdd ¼ 1:5 V.
6
∆f (MHz)
5 4 3 2 1 0.8
1.0
1.2
1.4
1.6
Vdd (V) Fig. 20. Frequency shift vs. supply voltage. Data refer to a 101stages ring oscillator composed of 10 lm · 200 nm devices with a 0.9 nm gate oxide.
A non-negligible increase of the frequency was found, which reached about 8% for the thinner oxide (0.9 nm). If supply-voltage scaling-down (Fig. 20) is accounted for, the magnitude of the frequency shift decreases, yet it remains significant (4%). Dependency of the frequency shift on device width is also illustrated in Fig. 10; in this case too, the shift only weakly depends on W , since parasitic gate currents and main drain currents scale in the same way.
5. Conclusions In this paper, the analysis of a relatively complex circuit, designed in a decananometric CMOS technol-
ogy, has been presented. The analysis aimed at checking functional and performance parameters in aggressively scaled-down circuits, with reference to standard CMOS implementation style and design flow. By intermixing device- and circuit-simulation approaches, sensitivity of circuit performance to fabrication parameters (i.e., oxide-thickness) was evaluated. Results of the analyses show that, even at significant levels of gate currents, the functionality of the considered circuit is not compromised. Within the considered range (corresponding to the ITRS prediction for the next 3–4 years, approximately) the circuit keeps working, although many design constraints (noise margins, power consumption, propagation delay) are significantly affected by the gatecurrent regime and hence should be carefully reconsidered by designers. Of course, such a picture cannot be straightforwardly extended to different class of circuits, in which the sensitivity to gate-leakage current is inherently much larger, such as dynamic gates or capacitive samplers: work is being carried out to characterize such architectures as well. Further work being carried out concerns a more comprehensive view of technology scaling-down: here, for the sake of simplicity, we have limited ourselves to account for the oxide thickness and the supply-voltage reduction. According again to the ITRS, the adoption of alternative dielectric materials (such as high-k or heavily nitrited oxy-nitride layers) is to be considered to mitigate the degradation induced by gate leakage. The simulation environment discussed in Section 3 above can be profitably exploited to obtain design hints in this case too.
Acknowledgements This work has been partially supported by M.I.U.R., within the framework of COFIN 2000 funding initiative. The authors also acknowledge contributions from LETI laboratory (Grenoble, France) and Udine University.
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Performance evaluation of ultra-thin gate-oxide CMOS circuits Alessandro Marras *, Ilaria De Munari, Davide Vescovi, Paolo Ciampolini Dip. di Ing. dell’Informazione, Universita di Parma, Parco Area delle Scienze 181/A, 43100 Parma, Italy Received 15 May 2003; received in revised form 3 July 2003; accepted 18 September 2003
Abstract Gate currents are becoming a major concern for ULSI circuit designers. A standard circuit design flow that takes into account such effects is needed in order to take advantage from nanometer-sized devices performance. Some suggestions on how to approach permeable-gate-device circuit simulation are proposed in this paper, focusing on gatecurrent-related effects on circuit performance. A simple, yet complete, standard CMOS circuit has been designed and its functional and performance indices have been evaluated, depending on the actual oxide thickness. To correlate performance directly to the fabrication parameters, a mixed-mode approach using both physical and circuit simulations has been adopted. Model parameters were calibrated on actual measurements. Simulation results have been compared for ideal- and permeable-gate devices. Although circuit functionality is not affected (within the considered technology range, at least), significant performance alterations are highlighted. 2003 Elsevier Ltd. All rights reserved. Keywords: Thin oxide; Direct tunneling; Gate current; CMOS; Circuit analysis
1. Introduction As the channel feature-size of IC technology decreases, scaling rules impose the thinning of the gate dielectric, down to the limit at which gate-leakage current become significant. According to the last revision of the International Technology Roadmap for Semiconductors (ITRS) oxide thickness in the order of 1 nm will be used in 2004–2005 for ultra-short CMOS [1]. Several limiting factors associated with ultra-thin gate oxides have been reported in literature [2,3]; among them, direct tunneling current exponentially depends on the oxide thickness and becomes relevant (i.e., non-negligible with respect to the drain–source current) when gate oxide decreases below 2 nm. In this paper, we focus on the influence of such currents on the behavior and performance of integrated systems, by investigating the circuit response of aggressively scaled-down circuits.
Direct-tunneling gate currents have been extensively studied, with reference to basic devices [4,5], or elementary circuit building blocks [6]. However, when gate currents come into play, coupling among interconnected circuit stages becomes more complex, and a more comprehensive modelling approach may be needed. Here, the simulation of a complete functional unit is discussed; a CMOS ring oscillator has been considered: the interaction between cascaded stages due to the gate current can be taken into account, whereas the circuit is still simple enough to allow for intuitive interpretation of the analysis results. In Section 2 below, a few details on the designed circuit, as well as on the reference fabrication technology, are given. Simulation tools and models are described in Section 3, whereas results are presented and discussed in Section 4; conclusions are drawn in Section 5.
2. Circuit design and technology *
Corresponding author. Tel.: +39-0521-905811; fax: +390521-905822. E-mail address: [email protected] (A. Marras).
A CMOS ring oscillator has been designed and simulated; actual fabrication is under way at the time of
0038-1101/$ - see front matter 2003 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2003.09.028
A. Marras et al. / Solid-State Electronics 48 (2004) 551–559
writing, at LETI facilities (Grenble, F). Details on the fabrication process are given in [7]: such a process allows for channel lengths down to 50 nm: nevertheless, in the following, fairly longer devices (200 nm) have been considered, to make discussion independent of too severe short-channel and punch-through effects. Test devices used for model calibration featured oxide thickness ranging from 2.2 nm down to 1.3 nm (even thinner SiO2 layers are actually being used in advanced production technologies [8]). A wider thickness range was modelled by extrapolating actual device measures. Appropriate doping profiles were inferred from experiments and information from the foundry. Device measures, used for model characterization have been performed directly at LETI and at the University of Udine, mostly on nMOS devices: measures of pMOS devices were not available, so that pMOS transistors have been fully characterized on the basis of simulation results. To this purpose, geometrical and physical parameters characterizing the CMOS fabrication process at hand were taken into account. Several CMOS oscillators were designed, in order to figure out which factors (device size, chain length, etc.) would emphasize gate-current impact on circuit performance; both dynamic and static behaviour have been considered, by properly controlling the feedback path.
3. Simulation models and circuit application In order to evaluate the performance of the oscillator, a comprehensive set of circuit simulations have been carried out, by using commercial CAD tools such as ELDO or SPECTRE. To this purpose, a compact MOSFET model, capable of taking into account the gate-leakage currents, should be adopted and properly characterized. Largely used compact models actually exist, which allow to perform circuit simulation of permeable-gate devices (most notably, Berkeley’s BSIM4 [9]): however, their formulation usually involves an extensive set of parameters, which not necessarily have a straightforward physical meaning and thus need to be fitted on actual device measurement. This makes these models unpractical for the prediction of technologyrelated performance. For this reason, a more physically oriented modelling strategy was adopted. A mixed-mode approach was exploited to this purpose: device simulation (in particular, DESSIS ISE-TCAD software [10]) was extensively used to characterize devices, investigating dependencies on main technological parameters. Full sets of current–voltage ðID ðVG ; VD ; VS Þ; IG ðVG ; VD ; VS ÞÞ characteristics were computed, and validated against available experimental results. Curves were then extrapolated and parametrized with respect to oxide thickness. Eventually, device simulation results have been transferred to the compact model used for circuit
D IGD(VGS,VDS ) physical simulation
EKV
G
B
IGS(VGS,VDS ) IGB(VGS,VDS ) S Fig. 1. Sketch of the macro-circuit model defined.
simulation, the basic scheme of which is illustrated in Fig. 1. The model core is the conventional (i.e., not accounting for gate current) EKV model [11]: parameters were extracted from measurements (when actual device prototypes were available) or from device simulation (for projected technologies). Gate current, instead, has been introduced by means of the set of additional voltage-controlled current sources shown in Fig. 1. Current sources have been implemented as HDL (Hardware Description Language) blocks, describing distinct gate-current components, as previously modelled by DESSIS simulations. An overall good fit was obtained indeed for the technologies at hand as shown, for instance, in Figs. 2–4. Here, for the sake of conciseness, only data for a given device size are reported: the numerical model has actually been preliminarily validated on the whole range of device sizes investigated below. pMOS gate currents, predicted from the simulation, are instead reported in Fig. 5. Although such an approach is computationally expensive, and hence unpractical for routinely performing complex
I G (nA)
552
80 70 60 50 40 30 20 10 0
measurement simulation
VDS
0.0
0.5 1.0 VGS (V)
1.5
Fig. 2. Comparison between simulations and measurements performed on a 10 lm · 0.2 lm, 1.5 nm gate-oxide nMOS device: gate current (IG ) vs. gate–source voltage ðVGS Þ@VDS ¼ 0:1 V, 0.5 V, 1.0 V, 1.5 V.
A. Marras et al. / Solid-State Electronics 48 (2004) 551–559
553
2.5 1.5
measurement simulation
2.0
IG (nA)
I D (mA)
1.0
VDS
1.5 1.0
0.5
|VDS|
0.5 0.0
0.0 0.0
0.5
1.0
1.5
0.0
0.5
VGS (V) Fig. 3. Comparison between simulations and measurements performed on a 10 lm · 0.2 lm, 1.5 nm gate-oxide nMOS device: drain current (ID ) vs. gate–source voltage ðVGS Þ@VDS ¼ 0:1 V, 0.5 V, 1.0 V, 1.5 V.
45
physical model circuit model
40
C (pF)
35 30 25 20 15 10 5 0.0
0.5 1.0 VGS (V)
1.0
1.5
VSG (V)
1.5
Fig. 4. Comparison between physically simulated and circuitmodel-simulated gate capacitance for a 10 lm · 0.2 lm, 1.5 nm gate-oxide nMOS device.
circuit simulations, it allows for straightforward correlation of gate-leakage currents with main fabrication parameters, and make it possible to extrapolate results even for hypothetical technologies, for which an experimental characterization is not yet available. Moreover, straightforward evaluation of the gate-current impact on the overall circuit performance can be easily achieved by comparing results obtained with additional gate-current sources switched on and off, respectively.
Fig. 5. Simulated behaviour of a 10 lm · 0.2 m, 1.5 nm gateoxide pMOS device: gate current (IG ) vs. source–gate voltage ðVSG Þ@VDS ¼ 0:1 V, )0.45 V, )0.8 V, )1.15 V, )1.5 V.
based study of a complete ring-oscillator circuit has been carried out: aiming at evaluating main merit figures (average power consumption (P ), logic swing (LS), Noise Margin (NM), oscillation frequency (f )) and their dependence on oxide thickness (tox ) and gate-leakage current (IG ). Results underline that, due to gate-leakage effects, even the basic properties of standard CMOS gates are to be reconsidered. Gate current, in fact, typically flows from the input of one gate into the output of the preceding one (or vice versa), thus introducing static coupling between cascaded stages. Thus, strictly speaking, logic gates are no longer ratioless, since areadependent gate currents coming from adjacent gates may contrast pull-up and pull-down networks (Fig. 6). This, in principle, may lead, when aggressively scaled-down oxides are used, to the need of revising device-sizing criteria used in conventional CMOS architectures.
VL
VH
VL
VH
4. Discussion Once the model illustrated in previous section has been validated against measurements, the simulation-
Fig. 6. Sketch describing gate-current-related coupling effects.
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4.1. Power dissipation Tunneling current effects enhances circuit average power dissipation: in Fig. 7, circuit simulated responses for permeable-gate and ideal-gate devices at different oxide thicknesses are compared. The absolute variation of average power dissipation DP has been found to depend on tox in an exponential way: DP ¼ AP expðBtox Þ where parameters AP and B have been fitted on simulation results. As shown in Fig. 8, this relationship is similar to the dependency of static gate currents on oxide thickness:
Average Power (mW)
25
permeable ideal
20 15 10 5 0 0.8
1.0
1.2
1.4
1.6
tox (nm) Fig. 7. Whole circuit average power dissipation as a function of oxide thickness. Data refer to a 101-stages ring oscillator composed of 10 lm · 200 nm devices, at constant power supply (Vdd ¼ 1:5 V). Triangles represent permeable-gate circuit behaviour, while circles are related to ideal ones.
∆P (µW)
100
10
10
1
1
IG (µA)
∆P IG exponential fitting
100
0.1
0.1 0.9
1.1 1.3 tox (nm)
1.5
Fig. 8. Absolute average power variation (due to a single stage) between permeable and ideal case vs. oxide thickness @ Vdd ¼ 1:5 V. Data for a ring oscillator designed using 10 lm · 200 nm devices. For comparison, gate current has also been reported.
Table 1 Fitting parameters describing exponential behaviour for a 101stages ring oscillator composed of 10 lm · 200 nm devices, at constant power supply (Vdd ¼ 1:5 V) DP DLS DVOH DVOL Df IG
A
B
30 W 20.5 KV 15 KV 5.5 KV 600 GHz 37 lA
1.3 · 1010 1.3 · 1010 1.3 · 1010 1.3 · 1010 1.3 · 1010 1.3 · 1010
m1 m1 m1 m1 m1 m1
IG ¼ AG expðBtox Þ In particular, the damping factor B is the same, making it evident the straightforward correlation between static gate-current and average power increase. Fitting parameters are reported in Table 1 for a 101-stages ring oscillator composed of 10 lm · 200 nm (W L) devices, at constant power supply (Vdd ¼ 1:5 V). In the CMOS ideal case, power dissipation is usually dominated by the frequency-dependent, dynamic contribution of the capacitive load current. Here, instead, additional contributions, both dynamic and static, come from the gate currents exchanged with adjacent stages: in the case at hand, actually, static component becomes dominant. In fact, due to the relatively long inverter chain analysed (101 stages), switching at each stage takes only a small fraction of the oscillating period: we can thus estimate the static power consumption for a n-stages oscillator by assuming that n=2 nMOSFET’s and n=2 pMOSFET’s are in the on-state. The static power dissipated by each stage (PS ) thus reads: PS ¼ ðIG;n þ IG;p Þ Vdd =2 where IG;n and IG;p are the asymptotic values of current tunneling through nMOSFET and pMOSFET, respectively. By comparing PS with the increase of the overall power DP (Table 2), it is confirmed that such an increase is mostly to be ascribed to static power consumption. Such a contribution may easily exceed dynamic power, thus deeply affecting the way CMOS power constraints are customarily taken into account. As this static comTable 2 Single-stage average power variation between permeable-gate and non-permeable-gate (DP ) and static power consumption (PS ) as a function of the oxide thickness tox (nm)
DP (lW)
PS (lW)
1.5 1.3 1.1 0.9
0.078 1.432 15.406 228.386
0.060 1.446 15.800 233.570
A. Marras et al. / Solid-State Electronics 48 (2004) 551–559
1
W= 1µm W= 10 µm
∆P (µW)
relative variation
100
10
∆f/f ∆ LS/LS ∆P/P
0.1
0.01 0.9
1.1
555
1.3
1.5
1
2
6
8 10
W (µm)
Vdd (V) Fig. 9. Absolute average power variation (due to a single stage) between permeable and ideal case vs. supply voltage. Data for a 101-stages ring oscillator composed of 10 lm · 200 nm devices with a 0.9 nm gate oxide (crosses), and for another 101-stages ring oscillator composed of narrower (1 lm · 200 nm) devices with a 0.9 nm gate oxide (circles).
4
Fig. 10. Ring oscillator performance variation (normalized values) between permeable and ideal case vs. device width when using 0.9 nm gate oxide devices @ Vdd ¼ 0:9 V.
1.0
4.2. Logic swing degradation As observed in the preliminary remarks above, gate currents now flow into pull-up and pull-down networks of neighbouring logic gates. The situation is sketched in
0.8
∆P/P
ponent depends on coupling effects between cascaded stages, an estimation of dissipated power based on a single-stage stand-alone analysis would neglect it, giving far lower values. In a relative sense, lowering the supply voltage does not modify the picture: both components (static and dynamic) decrease, and the ratio between them is not significantly affected (Fig. 9). At 0.9 nm oxide-thickness, 0.9 V power supply, 87.5% of the dissipated power still comes from static gate currents. Since gate current depends on the gate area (and thus is proportional to the channel width W ), using narrower devices significantly reduces static power dissipation (Fig. 9). However, when decreasing channel width, dynamic power dissipation is also reduced, as a consequence of a lower drain current. For this reason the relative weight of the leakage-related power component remains basically the same, as it is shown in Fig. 10. Power dependence on the ring length also confirms that the nature of the power increase is static. Power contribution due to switching transients, in fact, is mainly dynamic: by shortening the inverter chain, the switching transient time becomes a more relevant fraction of the oscillation period, thus reducing the relative weight of static dissipation, as shown in Fig. 11. Nevertheless, even for very short chains, gate-current impact remains not negligible at all.
0.6 0.5 0.3 21
41
61
81
101
number of stages Fig. 11. Static power contribution to global dissipation (normalized values) vs. chain length for a ring oscillator using 1 lm · 200 nm, 0.9 nm gate oxide devices @ Vdd ¼ 0:9 V.
Fig. 6: due to the static currents flowing through gate dielectric in adjacent stages, a voltage drop occurs at the pull-up or pull-down devices, thus reducing the overall swing. Thus, node voltages depend on the ratio between on-state-MOSFET drain current (ID ) and area-depending gate current tunneling through oxide (IG ). Off-state devices also contribute to gate current because of electrons flowing from drain overlap diffusion to polysilicon gate; however, simulations shows that such a contribution is actually negligible, with respect to gate current coming from switched-on devices; literature [12] confirm such an expectation. Voltage drops at the channel is basically ohmic in this current range, so that, by comparing performance of the actual (i.e., leaky-gate) circuit with ideal one, an
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exponential dependence of the swing lowering (DLS) on the oxide thickness is found in this case too:
0.1
as shown in Fig. 12; fitting parameters are reported in Table 1. As a consequence, noise margins degrade as well: Fig. 13 shows lowering of both margins. The effect is slightly more pronounced on the high-level margin: this can be understood by looking at Fig. 14, which refers to the actual shift in high and low values; as illustrated in Fig. 6, VOH decreases due to the channel voltage drop originated by an n-channel device gate current, whereas VOL increase is due to a p-channel device gate current. Since
∆LS IG exponential fitting
2
10
1
∆VL ∆VH exponential fitting
-0.1
-0.2
0.9
1.1
1.3
1.5
tox (nm) Fig. 14. High (DVOH , triangles) and low (DVOL , squares) logic values variations between the permeable and the ideal cases vs. oxide thickness.
5
10
4
10
2
-1
10
-2
10
-3
10
-4
10
10
IG (µ A)
3
0
10
1
10
0
10
-1
10
0.9
1.1 1.3 tox (nm)
1.5
Fig. 12. Ring oscillator absolute logic swing variation between permeable and ideal case vs. oxide thickness @ Vdd ¼ 1:5 V when using 10 lm · 200 nm devices. For comparison, the gate current vs. oxide thickness has also been reported.
700 Noise Margin (mV)
0.0
10
10 ∆LS (mV)
∆VH , ∆VL (V)
DLS ¼ ALS expðBtox Þ
600 500 High Noise Margin Low Noise Margin ideal case
400 0.9
1.1
1.3 tox (nm)
1.5
Fig. 13. Permeable- and ideal-device ring oscillator Noise Margins (high and low) vs. oxide thickness. Data refer to a 101stages ring oscillator composed of 10 lm · 200 nm (pMOS) and 5 lm · 200 nm (nMOS) devices, at constant power supply (Vdd ¼ 1:5 V).
tunnel probability exponentially depends on the inverse pffiffiffiffi of the carrier effective mass (Prtunnel / expð mÞ, [13]), nMOS gate current (for a given bias) is appreciably larger than pMOS gate current (at equivalent bias). Furthermore, the (larger) nMOS gate current flows on the pMOS, pull-up network (usually more resistive), whereas (smaller) pMOS gate current flows on the nMOS (usually less resistive) pull-down network. Again, exponential dependence of this effect on the oxide thickness is found: DVOH ¼ AOH expðBtox Þ
DVOL ¼ AOL expðBtox Þ where AOH , AOL and B are fitting parameters (Table 1). In the worst case analysed, a 14% logic swing reduction was found. By scaling-own supply voltage as well (Fig. 15), a 7% decrease is still found. Although channel resistance depends on the channelwidth W , scaling-down homogeneously W in the whole circuit does not imply significant change in the overall balance: narrowing device channels increases on-state channel resistance; at the same time, however, gate current decreases with gate area, and thus with W , so that the voltage drop is almost invariant, as shown in Fig. 10. It is worth stressing again the inherent coupling between adjacent stages arising from gate-currents: currents flowing through channel and gate oxide resistances in Fig. 6 depend, in turn, on the actual voltage/ current regimes in the preceding and subsequent stages. Thus, also due to feedback, the (simpler) analysis of a single stage cannot reliably predict the actual swing reduction, as shown in Fig. 16.
A. Marras et al. / Solid-State Electronics 48 (2004) 551–559
70
Frequency (MHz)
∆ LS
1
0.1
0.01 0.8
557
60 50 40 30 20 0.8
1.0
1.2
1.4
permeable ideal
1.0
Vdd (V) Fig. 15. Absolute logic swing variation vs. supply voltage. Data refer to a 101-stages ring oscillator composed of 10 lm · 200 nm devices with a 0.9 nm gate oxide.
1.2
1.4
1.6
tox (nm)
1.6
Fig. 17. Frequency vs. oxide thickness. Data refer to a 101stages ring oscillator composed of 10 lm · 200 nm devices, at constant power supply (Vdd ¼ 1:5 V). Triangles represent permeable-gate circuit behaviour, while circles are related to ideal ones.
1.50
LS (V)
I G pmos
I D pmos
1.46 1.42
single stage analysis full chain analysis
1.38
I D nmos
C
I G nmos
1.34 1.30 0.8
1.0
1.2
1.4
1.6
tox (nm) Fig. 16. Logic swing predictions from a single-stage and a fullcircuit analysis vs. oxide thickness @ Vdd ¼ 1:5 V for a ring oscillator designed using 10 lm · 200 nm devices.
4.3. Frequency shift In principle, by reducing the oxide thickness, an increase of the oscillating frequency can be expected anyway (since no threshold-voltage adjustment is accounted for, drain-current increase overcompensates the output capacitance increase); if gate currents are taken into account, anyway, such an increase is actually more pronounced, as shown in Fig. 17. In this case, influence of gate currents is more complicated: from the one hand, in fact, oxide thinning leads to an increase of drain currents; on the other hand, however, gate and drain currents depend on the input and output node swings, which suffer from the degradation discussed above. Moreover, gate currents sum up with drain ones,
Fig. 18. Schematic of currents charging and discharging gate capacitance of a logic block: pMOSFET drain current (ID pmos), pMOSFET gate current (IG pmos), nMOSFET gate current (IG nmos), nMOSFET drain current (ID nmos).
according to the scheme depicted in Fig. 18; depending on the actual transient phase, gate current may speed-up or slow-down the transient itself. For instance, different current components are extracted from the simulation and shown in Fig. 19, with reference to a pull-up transient: in this case, the most significant parasitic component appears to be the gate current flowing through the nMOS of the downstream-inverter, which competes with pull-up current coming from the pMOS of the preceding inverter. The combined influence of these effects does not lends itself to a straightforward, simple interpretation; again, however, frequency shift can be empirically modelled by means of an exponential trend: Df ¼ Af expðBtox Þ where Af and B are reported in Table 1.
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1.4 I D nmos I D pmos I G nmos I G pmos
1.2
I (mA)
1.0 0.8 0.6 0.4 0.2 0.0 3.506
3.507
3.508
3.509
t (µsec) Fig. 19. Drain and gate currents charging/discharging a node during a VL ! VH transition. Data refer to a 101-stages ring oscillator composed of 10 lm · 200 nm devices with a 0.9 nm gate oxide @ Vdd ¼ 1:5 V.
6
∆f (MHz)
5 4 3 2 1 0.8
1.0
1.2
1.4
1.6
Vdd (V) Fig. 20. Frequency shift vs. supply voltage. Data refer to a 101stages ring oscillator composed of 10 lm · 200 nm devices with a 0.9 nm gate oxide.
A non-negligible increase of the frequency was found, which reached about 8% for the thinner oxide (0.9 nm). If supply-voltage scaling-down (Fig. 20) is accounted for, the magnitude of the frequency shift decreases, yet it remains significant (4%). Dependency of the frequency shift on device width is also illustrated in Fig. 10; in this case too, the shift only weakly depends on W , since parasitic gate currents and main drain currents scale in the same way.
5. Conclusions In this paper, the analysis of a relatively complex circuit, designed in a decananometric CMOS technol-
ogy, has been presented. The analysis aimed at checking functional and performance parameters in aggressively scaled-down circuits, with reference to standard CMOS implementation style and design flow. By intermixing device- and circuit-simulation approaches, sensitivity of circuit performance to fabrication parameters (i.e., oxide-thickness) was evaluated. Results of the analyses show that, even at significant levels of gate currents, the functionality of the considered circuit is not compromised. Within the considered range (corresponding to the ITRS prediction for the next 3–4 years, approximately) the circuit keeps working, although many design constraints (noise margins, power consumption, propagation delay) are significantly affected by the gatecurrent regime and hence should be carefully reconsidered by designers. Of course, such a picture cannot be straightforwardly extended to different class of circuits, in which the sensitivity to gate-leakage current is inherently much larger, such as dynamic gates or capacitive samplers: work is being carried out to characterize such architectures as well. Further work being carried out concerns a more comprehensive view of technology scaling-down: here, for the sake of simplicity, we have limited ourselves to account for the oxide thickness and the supply-voltage reduction. According again to the ITRS, the adoption of alternative dielectric materials (such as high-k or heavily nitrited oxy-nitride layers) is to be considered to mitigate the degradation induced by gate leakage. The simulation environment discussed in Section 3 above can be profitably exploited to obtain design hints in this case too.
Acknowledgements This work has been partially supported by M.I.U.R., within the framework of COFIN 2000 funding initiative. The authors also acknowledge contributions from LETI laboratory (Grenoble, France) and Udine University.
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