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A nullor approach to the design of analog circuits for a desirable performance
Microelectronics Journal 78 (2018) 54–62
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A nullor approach to the design of analog circuits for a desirable performance Rohith Krishnan Radhakrishnan a, *, Krishnakumar Sukumarapillai a, Reza Hashemian b a b
Department of Electronics, School of Technology and Applied Sciences, Mahatma Gandhi University Regional Centre, Edappally Kochi, 682024, Kerala, India Department of Electrical Engineering, Northern Illinois University, DeKalb, IL, 60115, USA
A R T I C L E I N F O
A B S T R A C T
Keywords: Analog circuits Amplifiers Bode plot Fixator- norator pair Nullor Performance design
A method for the performance design of analog amplifier circuits based on nullors is discussed. It covers the design of AC parameters of the amplifier viz. input and output resistance, gain and bandwidth. Fixator-norator pair, which is a combination of nullor and sources, is the key element in this method. The complete performance design is considered as a two step process. Fixator-norator pair along with the linear equivalent model of the target circuit together does the first step, which is the design for input and output resistance and gain. The second step performs the design for bandwidth, i.e., mainly the cut-off frequencies. This is based on Bode plot analysis, which requires a reference circuit having the same frequency response as that of the desired one. The reference circuit is required only for simulation and it can be removed after the final design is met. Four examples are worked out for better understanding of the method.
1. Introduction The design of amplifier circuits deserves careful attention, as the designer is responsible to keep a desired frequency response and at the same time, the amplification should be faithful. That means the design should be intact with DC biasing design as well as the AC design. The task becomes complex, considering the fact that even the coupling capacitors which are used to keep the biasing of active devices unchanged have their own role in the frequency response of the amplifier. Thus automation of fault detection, circuit analysis and design are getting attraction [1,2]. DC biasing design aims at the proper operation of active devices at the desired operating points. The DC sources along with power conducting components (resistors) normally do this role. It is already proved that, Fixator-norator pair (FNP) [3,4] is an effective tool for the accurate design of bias supporting components. The proposed method aims at the AC design of amplifiers. That is to fix input resistance, output resistance, gain and the cut-off frequencies as per the design requirements. Direct analytical and FNP approaches are the two possible solutions for the design problem. In this manuscript, we discuss about both approaches and the FNP approach is seen to be more effective due to its flexibility in operation for dealing with nonlinearities. Recently, researchers are interested in new approaches towards the
design of analog circuits [5,6]. Nullor elements [7–11] are getting wide applications in analog designs. Tlelo-Cuautle [12] developed methods for the modeling of active devices. Symbolic analysis of analog circuits [13] with the help of nullor elements is getting attraction. Nullors find applications in computer aided deigns [14] and is an emerging field. Local sourcing [15] and local biasing [16] are proposed as the methods for the biasing design of active devices. Later, the technique is modified and uses FNP [3,4] as the tools for the design. FNPs can be realized using controlled sources or ideal op-amps [8]. FNPs find applications in fields not limited to biasing design, source allocation, design of active loads and current mirrors. Majority of the papers are based on resistive circuits and are not dealing with frequency response studies. Recently works are progressing on the scope of FNPs for frequency response designs of analog circuits. It was proposed a method [17] to modify a given circuit so that the frequency response of the circuit become close to a model response. Later, a nullor approach was proposed [18] and the methodology used in it compels an analog circuit to follow a model response. It uses only a single nullor and the study is limited to bandwidth design of analog amplifier/filter circuits. In this paper, our objective is to fix the AC parameters of an amplifier circuit with the help of FNPs. The designing is performed as a two-step process. First step designs the input and output resistance and gain of the amplifier, whereas second step deals with the cut-off frequencies. The
* Corresponding author. E-mail addresses: [email protected] (R.K. Radhakrishnan), [email protected] (K. Sukumarapillai), [email protected] (R. Hashemian). https://doi.org/10.1016/j.mejo.2018.06.005 Received 9 May 2017; Received in revised form 10 April 2018; Accepted 8 June 2018 0026-2692/© 2018 Elsevier Ltd. All rights reserved.
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remaining part of the paper is arranged as follows. Section 2 discusses about the proposed methodology. Section 3 gives four examples. Section 4 gives the discussion and finally section 5 concludes the methodology. 5) 2. Methodology The proposed method consists of two parts. The first part deals with design for input resistance, output resistance and gain, which is followed by the second part that deals with cut-off frequencies (bandwidth). As discussed, we have two approaches to deal with the design issue. Either the analytical method or by using the FNPs. With analytical approach, we need a close idea about the linear circuit and relationships between its various circuit parameters. The task becomes complex as the number of critical design specs increases. The FNP approach is direct and it can render a design spec into proper circuit component, which implies the analysis problem is now minimized to a design problem. A comparison between the two approaches is portrayed in example1, which proves the efficiency of proposed method. Using the FNP approach, the first part of the design needs the linear equivalent models of amplifiers. Proper FNPs may be applied to such linear circuits so as to fix the amplifier parameters, say, input resistance, output resistance and gain. Pairing norators reside along the feedback path to define the feedback network for accommodating the new values for amplifier parameters. The feedback should be DC isolated with the help of proper isolating capacitors. To get fruitful results from FNPs, they should be applied according to their governing rules [3]. An important question here arise is where to add the feedback. Purely, it depends on the skill and knowledge of designer. The isolation capacitors should be AC short at the frequencies of operation of the amplifiers. This is followed by the second part, the design for cut-off frequencies (bandwidth). It requires a model circuit, which possesses the same response as the one we expecting. Output terminals of model circuit and circuit under test are to be connected in series through a nullator, which acts as a fixator. Its pairing norator should replace one of the capacitor, which has an effect on the cut-off frequency to be set. In some other cases, we may require adding an extra component(s) to get the desired response, which may be a resistor, a capacitor, an inductor or a combination of these. Here we define the component(s) with the help of pairing norator. The overall design process is portrayed in algorithm 1. Note: Frequency response of amplifiers depends on two sets of capacitors; they are bypass and coupling capacitors and transistor capacitors (which are internal to the active device). A capacitor which is connected in series to the signal flow can affect the lower cut-off frequency; they include the first category. Bypass and coupling capacitors have effect on lower frequencies, at those frequencies device capacitors are open. At high frequencies coupling and bypass capacitors are short, but transistor capacitors are effective and they affect gain and even produce phase shifts. Thus altering the values of bypass or coupling capacitors may vary the overall gain of the amplifier at lower and mid frequencies, but they don't affect high frequency gain. However parasitic capacitors (low value) affect the high frequency gain. All these factors must be taken into consideration while dealing with frequency response design.
6)
7)
8)
capacitors should be AC short at the region of operation of amplifier ‘A’. That is all about of the first part of design. Now we go for second part. Make changes in the circuit ‘A’ to accommodate the results of part 1 of the design. Now we get circuit ‘B’. Take a model circuit, which having the same frequency response as that of the one we required. Connect the output of model circuit to that of circuit ‘B’ through a nullator. Select a capacitor in circuit ‘B’, which having an effect on the cut-off frequency to be fixed. Connect the pairing norator in place of the selected capacitor. In some cases, instead of a capacitor, we need to add an extra sub-circuit to fix the cut-off frequency. Such sub-circuit may consist of resistor, capacitor, inductor or their combinations. In such cases, norators should be placed in between the points where the sub-circuit is to be added. Simulate the circuit and analyze the Bode plot (impedance function) of norator, so that the designer can identify the new value for capacitor or component(s) in the sub-circuit. Next, accommodate the result of part 2 of the design into the circuit ‘B’. The circuit ‘B’ now possesses all the desired AC characteristics. Finally, analyze the Bode plots, both magnitude and phase plots of the redesigned circuit for correctness in the bandwidth and stability.
The procedure for first and second part of the design is shown in Fig. 1(a) and (b) respectively. In Fig. 1(a), X1 and X2 denotes the points where the fixator is to be applied to fix a particular parameter. Y1 and Y2 represent the position of a norator, which defines the feedback component(s) to set the corresponding AC parameter. In Fig. 1(b), the circuit B is forced to follow the frequency response of reference circuit, at the same time, the norator redefines the value of one of the capacitor or defines a two terminal sub-circuit, addition of which in network B makes the frequency response of both the same. Note: The selection of capacitor or position of sub-circuit must be done with utmost care to make sure that the selected component or port has effect on the cut-off frequency to be fixed. In addition, the selection of capacitor must make sure that the redesign should result in only a slight variation of gain. Moreover, care should be taken to avoid biasing corrections made by the modifications made on circuit B. 3. Case study In this section, four examples are worked out, which demonstrate the methodology. Example 1 is a basic transistor amplifier in common emitter (CE) configuration. Example 2 is a two stage BJT bio-amplifier. Example 3 is a MOS amplifier and Example 4 is a two stage BJT amplifier. Example 1. A basic common emitter amplifier [19] as shown in Fig. 2(a) is considered in this example for performance design. The design requirements are, the amplifier should have a voltage gain of 150 V/V and input resistance close to 4 kΩ. In addition, the amplifier should be able to amplify signals from 800 Hz up to its higher cut-off frequency. As stated above, we have two methods to solve this design issue; direct analytical method and FNP method.
2.1. Algorithm 1
3.1. Direct analytical method
1) Consider the amplifier circuit ‘A’ which needs to be designed for its AC parameters. Define the desired values for those parameters. 2) Take the linear equivalent model of ‘A’, analyze the circuit and identify the position to add feedback path for fixing each of the parameters; input resistance, output resistance and gain. 3) Apply proper FNP in to the linear circuit. Norator lies along the designated feedback path and defines the feedback components. 4) Simulate the circuit and find each of the feedback components. DC isolate the feedback component using isolating capacitors. Such
The designing process consists of two parts. In this example, we need a gain of 150 V/V and input resistance of about 4 kΩ. These two requirements are fulfilled in the first part of design. The linear equivalent model of the basic amplifier, as Shown in Fig. 2(b) is required for the process. We can add a feedback resistance RF between nodes 1 and 2 for providing a shunt-shunt feedback. Such a feedback reduces both the gain and input resistance of the amplifier. Considering the gain as critical parameter, we can go for the design of RF. With the basic feedback theory, voltage gain of the shunt-shunt feedback amplifier is,
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Fig. 1. (a) Design of feedback components; (b) Design of capacitor or two terminal sub-circuit.
Fig. 2. (a). A basic CE amplifier; (b) linear equivalent circuit of the CE amplifier.
AV ¼
A 1 þ Aβ
where Rin is the equivalent input resistance of the amplifier, its value is found to be 4kΩ. Hence we can calculate the value of CC1 as 0.05 μF. However, the design becomes tedious if we need to set higher cut-off frequency as the designing want to modify transistor capacitors. In such cases the direct analytical method is not recommended.
(1)
where A is the gain of the amplifier without feedback and β is the feedback factor. A further analysis of the original circuit shows that the amplifier gain A ¼ 240 V/V and its input resistance is 10 kΩ. The value of β is now turned out to be 0.0025. Here, β can be related as the ratio of RS to RF. Hence a further calculation gives the value for RF as 800 kΩ. Yet we have not considered about input resistance of the amplifier. Analyzing the linear circuit with feedback, we get, Rin ¼
R 1þA
4. FNP approach In order to perform part 1 of the design, we need the linear model of the amplifier as shown in Fig. 2(b). A proper FNP is then applied to the output port of amplifier which sets the voltage gain of the amplifier at desired value; whereas it’s pairing norator defines the feedback component. Fig. 3 shows the designing process. With gm ¼ 0.05 A/V, simulation shows that the value of RF is 800 kΩ. Now we can remove the FNP and place RF of 800 kΩ instead of norator.
(2)
Here R denotes the ratio of output voltage to input current. Further, we can calculate Rin as 4kΩ. Here we can conclude first part of the design. But the design become even complex if we need a different Rin or need to fix more amplifier parameters. In such cases we can depend on Circuit Conductance Matrix (CCM) [20,21] which takes the form GV ¼ I, where G is the conductance matrix. If we have n number of design specs, it can be related to n port voltages belong to vector V. Further, vector I which represents their respective current sources should be re-evaluated for satisfying the critical design specs. With more number of critical specs, solving of CCM is often tedious and time consuming, as it needs linearization and cannot directly implemented in circuit simulators. Second part of the design deals with cut-off frequency. In this case we need to fix lower cut-off frequency of the amplifier at 800 Hz. This can be done by redesigning one of the coupling or bypass capacitor. Here we are redesigning the value of CC1. Analyzing the circuit, we can relate lower cut-off frequency as, FL ¼
1 2π Rin Cc1
Fig. 3. Redesign of basic CE amplifier for a voltage gain of 150 V/V. Small-signal characteristics V (VO)/V_V1 ¼ 1.491Eþ02 Input resistance AT V_V1 ¼ 4.006 Eþ03 Output resistance AT V (VO) ¼ 3.735Eþ03
(3)
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FL ¼ 3.7 kHz and FH ¼ 169 kHz. Now we can go for the second part of design, i.e., we must reduce FL to 800 Hz. We now need a reference circuit which has FL ¼ 800 Hz and gain ¼ 149 V/V. A band pass filter (BPF) is an ideal candidate to perform this task. Fig. 4 shows the circuit arrangement. Here, RF ¼ 800 kΩ and other resistor values and gm are as same as in Fig. 3. Also, the transistor parameter βF ¼ 80. The output of BPF and CE amplifiers should be connected together through a nullator. CC1 should be replaced with its pairing norator. Now we can perform AC sweep analysis, and by analyzing impedance function Z(s) of norator as shown in Fig. 5(a), it shows a magnitude of 33.1 dB at 70 kHz. Therefore, we can calculate the value of CC1 as, 1/(Z (ω) ω) ¼ 0.05 μF. The final circuit diagram of the basic CE amplifier after redesign is shown in Fig. 5(b). It is now vital to analyze the final frequency response Bode plots of the amplifier. It is shown in Fig. 6(a) and (b). The redesigned amplifier has a gain of 43.38 dB or 147.5 V/V, FL ¼ 803 Hz and FH ¼ 158.5 kHz. Also, its phase shift is within the limit as the phase angle is close to 270 when gain is 0 dB and it provides stable operation. Note: In the first part of the design, our primary aim is to set the input resistance of the amplifier at 4 kΩ. Thus we have derived an additional feedback resistance of value 800 kΩ to meet this design criterion. Originally, the equivalent input resistance of the amplifier is at RS þ Ri ¼ 10 kΩ, we are altering it by means of a feedback resistance. The accurate value of RF is designed with the help of FNP. Working of FNPs is explained extensively in literature [3,4]. In the second part of design, our requirement is to make the lower cut-off frequency FL ¼ 800 Hz. As discussed earlier, coupling and bypass capacitors affect the lower cut-off frequency of amplifiers. Thus, we considered CC1 and redesigned its value with the help of FNP to get the desired FL. If we want to alter the
Fig. 4. Redesign of CC1 for a given cut-off frequency.
To avoid the effect of RF on the DC biasing, it should be DC isolated using a coupling capacitor. The capacitor is of 100 nF so that it is AC short at the region of operation of the amplifier. The result of small signal analysis of the amplifier with RF is shown below. This validates our design. To perform the AC sweep analysis, we must consider all the internal capacitors and the coupling capacitors. Let them be, Co ¼ 1 pF, Ci ¼ 5 pF, Cbc ¼ 3.32 pF, CC1 ¼ 0.01 μF, CC2 ¼ 0.04 μF. Considering all the capacitive effects, the AC sweep analysis is performed with the basic CE amplifier and the results show that the amplifier have a gain of 142 V/V,
Fig. 5. (a) Bode plot of norator; (b) final circuit diagram of the basic CE amplifier.
Fig. 6. Bode plots of modified CE amplifier; (a) magnitude (b) phase. 57
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separately programmed, or to it must be done by hand calculation. So, it is only good for smaller circuits. Second, the circuit must be linearized before applying the method. On the other hand, FNP approach is more flexible and easily adhered with nonlinear and linear circuits. In addition, the pair allows the target circuit to follow the desired response provided by the model circuit. This, as far as we know, cannot be done by the direct approach. FNP can be implemented in circuit simulators with ideal controlled sources with very high gain or using op-amps. Thus the FNP approach is well suited and effective for analog circuit design. Remaining three examples confirms our statement. Example 2. In this example, our requirement is to design a bioamplifier for amplifying spikes from the nerves of cockroaches. The two design requirements are, the amplifier should amplify an input signal 150 times for obtaining a recognizable output signal. In addition, the filter setting should be such that the circuit needs to amplify the signals of 300Hz and above. This will effectively filter out other unwanted electrical noises. For realizing the bio-amplifier, we can use the topology [22] as shown in Fig. 7, which is an amplifier with voltage gain of 300 V/V with a different lower cut-off frequency.
Fig. 7. Topology for bio-amplifier.
As stated above, our design parameters are voltage gain and lower cut-off frequency. A voltage gain of 150 can be obtained from the bioamplifier by adding an extra feedback resistance RF between the base and collector terminals of Q2. So in first part of the design, our aim is to design the value of RF and it can be done with the help of the FNP arrangement as depicted in Fig. 8. In Fig. 8, gm1 ¼ gm2 ¼ 0.036 A/V, RA1 ¼ R1jjR2jjRi1 ¼ 695Ω, RA2 ¼ RC1jjRO1jjR3jjR4 ¼ 696Ω, RA3 ¼ RE2jjRE3 ¼ 167Ω and RA4 ¼ RC2jj RO2jjRL ¼ 2.36 kΩ. On simulating the circuit, we get value of RF as 11.78 kΩ. This is all about part 1 of the design and second part is the design for lower cut-off frequency FL. Fig. 9(a) shows the circuit arrangement for the design of FL. As we want to design lower cut-off frequency, we need to redesign the value of one of the coupling or bypass capacitor. In this case we can redesign C3 by employing the FNP arrangement. Here, the reference circuit and nullator together act as a fixator and at the same time its pairing norator replaces C3. Fig. 9(b) shows the impedance function of norator. Here reference circuit may be a band pass filter with voltage gain 150 and FL ¼ 300 Hz. A further analysis on the Bode plot of norator reveals that the plot has a magnitude of 24.216 dB at 500 Hz. This implies that the required value for C3 ¼ 19.6 μF. It is now necessary to check the correctness of the final circuit. Fig. 10 shows the Bode plots of the redesigned circuit. Magnitude plot shows that gain and lower cut-off frequency are very much close to the design and phase plot proves that the circuit is stable.
Fig. 8. Design of RF with the help of FNPs.
higher cut-off frequency FH, we must consider varying the transistor capacitors. Here, the second part of design uses a combination of reference circuit and nullor to lock to the desired frequency response. The pairing norator resides at the place of CC1. Then the AC sweep analysis is performed. This is valid because the arrangement is similar to that in first part of the design except that the simulation continues to a time ‘T’ as defined by the designer and norator generates data for each of the time steps ‘t’. Similarly we can explain the remaining three examples and the same theory is applicable for them. Comparing the two approaches, we can see that theoretically they respond similarly, but there are differences in their implementation. First, there is no commercially available circuit simulator so programmed to handle the direct analytical method. Thus, the method needs to be
Fig. 9. (a). Design of C3; (b) Bode plot for norator. 58
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Fig. 10. Bode plots of bio-amplifier; (a) magnitude; (b) phase.
Fig. 11. (a) Two stage MOS amplifier; (b) design of RF for a given input resistance.
Example 3. Here a two stage MOS amplifier [19] as shown in Fig. 11(a) is considered for redesigning. The amplifier originally has an input resistance of 50 kΩ, output resistance of 3.33 kΩ and a voltage gain of 23.7 V/V. In addition, it amplifies signals of all frequencies in between 585 Hz and 186 MHz. Our aim is to reduce its input resistance to 30 kΩ and higher cut-off frequency to 14 MHz without altering its voltage gain.
shows a wide bandwidth of (1.1 kHz–22.4 MHz) 22.39 MHz with a gain of 367 V/V. We require a bandwidth of 855 kHz without varying FL, i.e., FH should be reduced to 853.9 kHz. The design process starts by taking the linear equivalent model of two stage BJT amplifier. As we need to fix two parameters, viz. input resistance and gain, we need to apply two FNPs into the circuit, which can define two feedback components. One of the norator defines a feedback component, which is connected from collector of Q2 to base of Q1, and it can fix the input resistance at 1 kΩ. The second norator is connected between collector and base of Q2. The design arrangement is depicted in Fig. 15, where gm1 ¼ 0.0714 A/V and gm2 ¼ 0.1071 A/V.
The design process starts with creation of linear equivalent circuit, where we need to apply proper FNPs. The circuit arrangement is shown in Fig. 11(b), where, gm1 ¼ gm2 ¼ 0.01 A ⁄ V and remaining values of resistors are same as that in Fig. 11(a). The input fixator VS (1 V, 33.33 μA) fixes the input resistance of MOS amplifier at 30 kΩ, at the same time its pairing norator finds the feedback resistance RF to meet the design. Here simulation shows that value of RF is 21.74 kΩ. In the second part, we need to reduce the bandwidth of the MOS amplifier, so that it eliminates the signals above 14 MHz. Following the design procedure, we need a reference circuit with FH ¼ 14 MHz and gain 23.7 V/V. Here we have to design an extra capacitor to reduce the overall bandwidth. It can be placed in between gate and drain terminals of M2. Circuit arrangement for the design is shown in Fig. 12(a); where RF ¼ 21.74 kΩ, and CF ¼ 100 nF. All other components have values same as that in Fig. 11(a). Here the reference circuit and nullator together act as the fixator, and its pairing norator defines the capacitor. Simulating this circuit and analyzing the Z(s) plot for norator as shown in Fig. 12(b), we can conclude that the value of extra capacitor C3 is 1.85 pF. Finally, it is vital to analyze the Bode plots of redesigned circuit. They are shown in Fig. 13(a) and (b). Magnitude plot implies that the gain is 27.485 dB or 23.67 V/V and FH ¼ 14.3 MHz. Phase plot shows that the redesigned circuit is stable as per the feedback stability theory.
Fixator VS (1 V, 1 mA) fixes the input resistance at 1kΩ, at the same time, its pairing norator finds the value of RF1. Similarly, output fixator VO (300 V, 0) fixes the gain of the amplifier at 300 V/V, and its pairing norator finds the value of RF2. Simulation shows that value of RF1 and RF2 are 801.5 kΩ and 47.82 kΩ respectively. Now we can go for the second part of the design; ie, we need to reduce FH to 853.9 kHz from an undesired value of 22.4 MHz. We can. use a BPF of FL ¼ 1.1 kHz and FH ¼ 853.9 kHz as the reference circuit and follow the procedures as discussed in algorithm 2. A feedback capacitor CF is to be inserted parallel to RF1 and such a capacitor can decrease the higher cut-off frequency of the amplifier. The circuit setup for the design of CF is shown in Fig. 16(a) and the impedance function plot for norator is shown in Fig. 16(b). The transistor parameters βF1 ¼ 100 and βF2 ¼ 150. Here the norator corresponds to CF and by analyzing the Bode plot shown in Fig. 16(b), it is clear that Z(s) pass through 95.26 dB at 1 MHz. Therefore, we can find the value of CF for the desired FH as 2.75 pF. It is now necessary to check the Bode plots of the final circuit. Fig. 17(a) shows the magnitude plot and Fig. 17(b) shows the phase angle plot of the modified amplifier. Magnitude plot satisfies the gain and bandwidth, as it shows a gain of 49.54 dB or 300 V/V, FL ¼ 1.05 kHz and
Example 4. Here, a two stage common emitter-common base (CE-CB) BJT amplifier [19] as shown in Fig. 14 is considered for redesigning. The design requirements are, the amplifier should have a voltage gain of 300 V/V and its input resistance should be 1 kΩ. Originally, the amplifier 59
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Fig. 12. (a). Design of C3 for a given cut-off frequency; (b) Bode plot of norator.
Fig. 13. Bode plots of modified MOS amplifier; (a) magnitude; (b) phase.
FH ¼ 855 kHz. Phase plot indicates that the amplifier is stable, since it satisfies feedback stability theory.
makes a futile result with this approach by an improper application of FNPs into the target circuit, which means empirical skill of the designer plays an important role in getting fruitful designs. For fixing ‘x’ number of parameters, we need ‘x’ number of FNPs. Here ‘x’ number of norators denotes ‘x’ number of unknowns or components to be redesigned. Sometimes, a careful analysis of the circuit directly gives us the value(s) of one or more unknowns with less number of FNPs, which mean reduction in the designing time and effort. Again, the ‘unknown’ must have a close relationship with the parameter to be fixed, otherwise, the
5. Discussion This section portrays some of the key points of this study. Even though the proposed method produces affirmative results, a designer can
Fig. 14. Two stage CE-CB BJT amplifier.
Fig. 15. Design of RF1 and RF2. 60
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Fig. 16. a). Design of CF; (b) Bode plot for norator.
Fig. 17. Bode plots of modified two stage CE-CB BJT amplifier; (a) magnitude (b) phase.
‘feedback’ effect between fixator and norator preclude and thus the method fails. While talking about frequency response designs, there exist the classical low frequency techniques such as design using coupling capacitors and poles and zeros technique. Dealing with phase angle, magnitude and frequency of a system is difficult with the traditional coupling capacitor approach and it was proposed to go for poles and zeros to realize such designs [23]. However, extraction of poles and zeros from a circuit is still a difficult task [24]. That is the reason we go for Bode-plot approach in this work. Finally, Table 1 gives a comparison between the proposed work and other relevant works in this domain. This proves the importance of the work. The application of nullors as fixators is relatively new and is still under development. The FNPs are not adhered to a certain limited areas. Its scope is wide and a skillful designer can render the pair to a form
which is helpful to one's design tasks. The basic idea is to define the value of an unknown which is necessary to keep the parameter under consideration at a desired level without violating the laws and concepts in analog circuits. 6. Conclusions A method for the AC performance design of amplifier circuits is presented. This method uses fixator-norator pair for rendering an AC parameter into a proper supporting element say resistor, capacitor, or a two terminal sub-circuit containing passive elements. Such element(s) must be replaced with an existing circuit component, or added into the original circuit at proper place. The AC performance design process consists of two parts. First part deals with input and output resistance of the amplifier and its gain. Linear equivalent circuit of the targeted amplifier is vital for this part of the design. FNPs are inserted to such linear circuits in cohesion with the parameters to be fixed and it results in new feedback networks containing one or more passive component for each AC parameter. They should be DC isolated with capacitors which are AC short at the operating frequencies of the amplifier. Cut-off frequency and obviously the bandwidth are designed in the second part of the design. A reactive component is redesigned or an additional two terminal network containing reactive component is defined at the second part of the design by making use of a reference circuit. A conspicuous point to be noted is that, the reference circuit should possess a frequency response, which is closed to the expected response. Four examples have been worked out in this paper for better understanding of the proposed technique.
Table 1 Comparison between the proposed work and other relevant works. Author
Tool used
Details of work
Verhoeven et al. (2003) [15] Hashemian (2008) [16] Hashemian (2012) [3] Hashemian (2017) [18] Proposed work
Controlled sources Coupling capacitors Fixatornorator pair Fixatornorator pair Fixatornorator pair
Local sourcing, results in scattered supplies. Local biasing, results in scattered supplies. Biasing design, only resistive circuit is considered with no frequency component. Study limited to design of bandwidth. Design of AC parameters viz. input and output resistance, gain and bandwidth (cutoff frequencies).
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References
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A nullor approach to the design of analog circuits for a desirable performance Rohith Krishnan Radhakrishnan a, *, Krishnakumar Sukumarapillai a, Reza Hashemian b a b
Department of Electronics, School of Technology and Applied Sciences, Mahatma Gandhi University Regional Centre, Edappally Kochi, 682024, Kerala, India Department of Electrical Engineering, Northern Illinois University, DeKalb, IL, 60115, USA
A R T I C L E I N F O
A B S T R A C T
Keywords: Analog circuits Amplifiers Bode plot Fixator- norator pair Nullor Performance design
A method for the performance design of analog amplifier circuits based on nullors is discussed. It covers the design of AC parameters of the amplifier viz. input and output resistance, gain and bandwidth. Fixator-norator pair, which is a combination of nullor and sources, is the key element in this method. The complete performance design is considered as a two step process. Fixator-norator pair along with the linear equivalent model of the target circuit together does the first step, which is the design for input and output resistance and gain. The second step performs the design for bandwidth, i.e., mainly the cut-off frequencies. This is based on Bode plot analysis, which requires a reference circuit having the same frequency response as that of the desired one. The reference circuit is required only for simulation and it can be removed after the final design is met. Four examples are worked out for better understanding of the method.
1. Introduction The design of amplifier circuits deserves careful attention, as the designer is responsible to keep a desired frequency response and at the same time, the amplification should be faithful. That means the design should be intact with DC biasing design as well as the AC design. The task becomes complex, considering the fact that even the coupling capacitors which are used to keep the biasing of active devices unchanged have their own role in the frequency response of the amplifier. Thus automation of fault detection, circuit analysis and design are getting attraction [1,2]. DC biasing design aims at the proper operation of active devices at the desired operating points. The DC sources along with power conducting components (resistors) normally do this role. It is already proved that, Fixator-norator pair (FNP) [3,4] is an effective tool for the accurate design of bias supporting components. The proposed method aims at the AC design of amplifiers. That is to fix input resistance, output resistance, gain and the cut-off frequencies as per the design requirements. Direct analytical and FNP approaches are the two possible solutions for the design problem. In this manuscript, we discuss about both approaches and the FNP approach is seen to be more effective due to its flexibility in operation for dealing with nonlinearities. Recently, researchers are interested in new approaches towards the
design of analog circuits [5,6]. Nullor elements [7–11] are getting wide applications in analog designs. Tlelo-Cuautle [12] developed methods for the modeling of active devices. Symbolic analysis of analog circuits [13] with the help of nullor elements is getting attraction. Nullors find applications in computer aided deigns [14] and is an emerging field. Local sourcing [15] and local biasing [16] are proposed as the methods for the biasing design of active devices. Later, the technique is modified and uses FNP [3,4] as the tools for the design. FNPs can be realized using controlled sources or ideal op-amps [8]. FNPs find applications in fields not limited to biasing design, source allocation, design of active loads and current mirrors. Majority of the papers are based on resistive circuits and are not dealing with frequency response studies. Recently works are progressing on the scope of FNPs for frequency response designs of analog circuits. It was proposed a method [17] to modify a given circuit so that the frequency response of the circuit become close to a model response. Later, a nullor approach was proposed [18] and the methodology used in it compels an analog circuit to follow a model response. It uses only a single nullor and the study is limited to bandwidth design of analog amplifier/filter circuits. In this paper, our objective is to fix the AC parameters of an amplifier circuit with the help of FNPs. The designing is performed as a two-step process. First step designs the input and output resistance and gain of the amplifier, whereas second step deals with the cut-off frequencies. The
* Corresponding author. E-mail addresses: [email protected] (R.K. Radhakrishnan), [email protected] (K. Sukumarapillai), [email protected] (R. Hashemian). https://doi.org/10.1016/j.mejo.2018.06.005 Received 9 May 2017; Received in revised form 10 April 2018; Accepted 8 June 2018 0026-2692/© 2018 Elsevier Ltd. All rights reserved.
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remaining part of the paper is arranged as follows. Section 2 discusses about the proposed methodology. Section 3 gives four examples. Section 4 gives the discussion and finally section 5 concludes the methodology. 5) 2. Methodology The proposed method consists of two parts. The first part deals with design for input resistance, output resistance and gain, which is followed by the second part that deals with cut-off frequencies (bandwidth). As discussed, we have two approaches to deal with the design issue. Either the analytical method or by using the FNPs. With analytical approach, we need a close idea about the linear circuit and relationships between its various circuit parameters. The task becomes complex as the number of critical design specs increases. The FNP approach is direct and it can render a design spec into proper circuit component, which implies the analysis problem is now minimized to a design problem. A comparison between the two approaches is portrayed in example1, which proves the efficiency of proposed method. Using the FNP approach, the first part of the design needs the linear equivalent models of amplifiers. Proper FNPs may be applied to such linear circuits so as to fix the amplifier parameters, say, input resistance, output resistance and gain. Pairing norators reside along the feedback path to define the feedback network for accommodating the new values for amplifier parameters. The feedback should be DC isolated with the help of proper isolating capacitors. To get fruitful results from FNPs, they should be applied according to their governing rules [3]. An important question here arise is where to add the feedback. Purely, it depends on the skill and knowledge of designer. The isolation capacitors should be AC short at the frequencies of operation of the amplifiers. This is followed by the second part, the design for cut-off frequencies (bandwidth). It requires a model circuit, which possesses the same response as the one we expecting. Output terminals of model circuit and circuit under test are to be connected in series through a nullator, which acts as a fixator. Its pairing norator should replace one of the capacitor, which has an effect on the cut-off frequency to be set. In some other cases, we may require adding an extra component(s) to get the desired response, which may be a resistor, a capacitor, an inductor or a combination of these. Here we define the component(s) with the help of pairing norator. The overall design process is portrayed in algorithm 1. Note: Frequency response of amplifiers depends on two sets of capacitors; they are bypass and coupling capacitors and transistor capacitors (which are internal to the active device). A capacitor which is connected in series to the signal flow can affect the lower cut-off frequency; they include the first category. Bypass and coupling capacitors have effect on lower frequencies, at those frequencies device capacitors are open. At high frequencies coupling and bypass capacitors are short, but transistor capacitors are effective and they affect gain and even produce phase shifts. Thus altering the values of bypass or coupling capacitors may vary the overall gain of the amplifier at lower and mid frequencies, but they don't affect high frequency gain. However parasitic capacitors (low value) affect the high frequency gain. All these factors must be taken into consideration while dealing with frequency response design.
6)
7)
8)
capacitors should be AC short at the region of operation of amplifier ‘A’. That is all about of the first part of design. Now we go for second part. Make changes in the circuit ‘A’ to accommodate the results of part 1 of the design. Now we get circuit ‘B’. Take a model circuit, which having the same frequency response as that of the one we required. Connect the output of model circuit to that of circuit ‘B’ through a nullator. Select a capacitor in circuit ‘B’, which having an effect on the cut-off frequency to be fixed. Connect the pairing norator in place of the selected capacitor. In some cases, instead of a capacitor, we need to add an extra sub-circuit to fix the cut-off frequency. Such sub-circuit may consist of resistor, capacitor, inductor or their combinations. In such cases, norators should be placed in between the points where the sub-circuit is to be added. Simulate the circuit and analyze the Bode plot (impedance function) of norator, so that the designer can identify the new value for capacitor or component(s) in the sub-circuit. Next, accommodate the result of part 2 of the design into the circuit ‘B’. The circuit ‘B’ now possesses all the desired AC characteristics. Finally, analyze the Bode plots, both magnitude and phase plots of the redesigned circuit for correctness in the bandwidth and stability.
The procedure for first and second part of the design is shown in Fig. 1(a) and (b) respectively. In Fig. 1(a), X1 and X2 denotes the points where the fixator is to be applied to fix a particular parameter. Y1 and Y2 represent the position of a norator, which defines the feedback component(s) to set the corresponding AC parameter. In Fig. 1(b), the circuit B is forced to follow the frequency response of reference circuit, at the same time, the norator redefines the value of one of the capacitor or defines a two terminal sub-circuit, addition of which in network B makes the frequency response of both the same. Note: The selection of capacitor or position of sub-circuit must be done with utmost care to make sure that the selected component or port has effect on the cut-off frequency to be fixed. In addition, the selection of capacitor must make sure that the redesign should result in only a slight variation of gain. Moreover, care should be taken to avoid biasing corrections made by the modifications made on circuit B. 3. Case study In this section, four examples are worked out, which demonstrate the methodology. Example 1 is a basic transistor amplifier in common emitter (CE) configuration. Example 2 is a two stage BJT bio-amplifier. Example 3 is a MOS amplifier and Example 4 is a two stage BJT amplifier. Example 1. A basic common emitter amplifier [19] as shown in Fig. 2(a) is considered in this example for performance design. The design requirements are, the amplifier should have a voltage gain of 150 V/V and input resistance close to 4 kΩ. In addition, the amplifier should be able to amplify signals from 800 Hz up to its higher cut-off frequency. As stated above, we have two methods to solve this design issue; direct analytical method and FNP method.
2.1. Algorithm 1
3.1. Direct analytical method
1) Consider the amplifier circuit ‘A’ which needs to be designed for its AC parameters. Define the desired values for those parameters. 2) Take the linear equivalent model of ‘A’, analyze the circuit and identify the position to add feedback path for fixing each of the parameters; input resistance, output resistance and gain. 3) Apply proper FNP in to the linear circuit. Norator lies along the designated feedback path and defines the feedback components. 4) Simulate the circuit and find each of the feedback components. DC isolate the feedback component using isolating capacitors. Such
The designing process consists of two parts. In this example, we need a gain of 150 V/V and input resistance of about 4 kΩ. These two requirements are fulfilled in the first part of design. The linear equivalent model of the basic amplifier, as Shown in Fig. 2(b) is required for the process. We can add a feedback resistance RF between nodes 1 and 2 for providing a shunt-shunt feedback. Such a feedback reduces both the gain and input resistance of the amplifier. Considering the gain as critical parameter, we can go for the design of RF. With the basic feedback theory, voltage gain of the shunt-shunt feedback amplifier is,
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Fig. 1. (a) Design of feedback components; (b) Design of capacitor or two terminal sub-circuit.
Fig. 2. (a). A basic CE amplifier; (b) linear equivalent circuit of the CE amplifier.
AV ¼
A 1 þ Aβ
where Rin is the equivalent input resistance of the amplifier, its value is found to be 4kΩ. Hence we can calculate the value of CC1 as 0.05 μF. However, the design becomes tedious if we need to set higher cut-off frequency as the designing want to modify transistor capacitors. In such cases the direct analytical method is not recommended.
(1)
where A is the gain of the amplifier without feedback and β is the feedback factor. A further analysis of the original circuit shows that the amplifier gain A ¼ 240 V/V and its input resistance is 10 kΩ. The value of β is now turned out to be 0.0025. Here, β can be related as the ratio of RS to RF. Hence a further calculation gives the value for RF as 800 kΩ. Yet we have not considered about input resistance of the amplifier. Analyzing the linear circuit with feedback, we get, Rin ¼
R 1þA
4. FNP approach In order to perform part 1 of the design, we need the linear model of the amplifier as shown in Fig. 2(b). A proper FNP is then applied to the output port of amplifier which sets the voltage gain of the amplifier at desired value; whereas it’s pairing norator defines the feedback component. Fig. 3 shows the designing process. With gm ¼ 0.05 A/V, simulation shows that the value of RF is 800 kΩ. Now we can remove the FNP and place RF of 800 kΩ instead of norator.
(2)
Here R denotes the ratio of output voltage to input current. Further, we can calculate Rin as 4kΩ. Here we can conclude first part of the design. But the design become even complex if we need a different Rin or need to fix more amplifier parameters. In such cases we can depend on Circuit Conductance Matrix (CCM) [20,21] which takes the form GV ¼ I, where G is the conductance matrix. If we have n number of design specs, it can be related to n port voltages belong to vector V. Further, vector I which represents their respective current sources should be re-evaluated for satisfying the critical design specs. With more number of critical specs, solving of CCM is often tedious and time consuming, as it needs linearization and cannot directly implemented in circuit simulators. Second part of the design deals with cut-off frequency. In this case we need to fix lower cut-off frequency of the amplifier at 800 Hz. This can be done by redesigning one of the coupling or bypass capacitor. Here we are redesigning the value of CC1. Analyzing the circuit, we can relate lower cut-off frequency as, FL ¼
1 2π Rin Cc1
Fig. 3. Redesign of basic CE amplifier for a voltage gain of 150 V/V. Small-signal characteristics V (VO)/V_V1 ¼ 1.491Eþ02 Input resistance AT V_V1 ¼ 4.006 Eþ03 Output resistance AT V (VO) ¼ 3.735Eþ03
(3)
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FL ¼ 3.7 kHz and FH ¼ 169 kHz. Now we can go for the second part of design, i.e., we must reduce FL to 800 Hz. We now need a reference circuit which has FL ¼ 800 Hz and gain ¼ 149 V/V. A band pass filter (BPF) is an ideal candidate to perform this task. Fig. 4 shows the circuit arrangement. Here, RF ¼ 800 kΩ and other resistor values and gm are as same as in Fig. 3. Also, the transistor parameter βF ¼ 80. The output of BPF and CE amplifiers should be connected together through a nullator. CC1 should be replaced with its pairing norator. Now we can perform AC sweep analysis, and by analyzing impedance function Z(s) of norator as shown in Fig. 5(a), it shows a magnitude of 33.1 dB at 70 kHz. Therefore, we can calculate the value of CC1 as, 1/(Z (ω) ω) ¼ 0.05 μF. The final circuit diagram of the basic CE amplifier after redesign is shown in Fig. 5(b). It is now vital to analyze the final frequency response Bode plots of the amplifier. It is shown in Fig. 6(a) and (b). The redesigned amplifier has a gain of 43.38 dB or 147.5 V/V, FL ¼ 803 Hz and FH ¼ 158.5 kHz. Also, its phase shift is within the limit as the phase angle is close to 270 when gain is 0 dB and it provides stable operation. Note: In the first part of the design, our primary aim is to set the input resistance of the amplifier at 4 kΩ. Thus we have derived an additional feedback resistance of value 800 kΩ to meet this design criterion. Originally, the equivalent input resistance of the amplifier is at RS þ Ri ¼ 10 kΩ, we are altering it by means of a feedback resistance. The accurate value of RF is designed with the help of FNP. Working of FNPs is explained extensively in literature [3,4]. In the second part of design, our requirement is to make the lower cut-off frequency FL ¼ 800 Hz. As discussed earlier, coupling and bypass capacitors affect the lower cut-off frequency of amplifiers. Thus, we considered CC1 and redesigned its value with the help of FNP to get the desired FL. If we want to alter the
Fig. 4. Redesign of CC1 for a given cut-off frequency.
To avoid the effect of RF on the DC biasing, it should be DC isolated using a coupling capacitor. The capacitor is of 100 nF so that it is AC short at the region of operation of the amplifier. The result of small signal analysis of the amplifier with RF is shown below. This validates our design. To perform the AC sweep analysis, we must consider all the internal capacitors and the coupling capacitors. Let them be, Co ¼ 1 pF, Ci ¼ 5 pF, Cbc ¼ 3.32 pF, CC1 ¼ 0.01 μF, CC2 ¼ 0.04 μF. Considering all the capacitive effects, the AC sweep analysis is performed with the basic CE amplifier and the results show that the amplifier have a gain of 142 V/V,
Fig. 5. (a) Bode plot of norator; (b) final circuit diagram of the basic CE amplifier.
Fig. 6. Bode plots of modified CE amplifier; (a) magnitude (b) phase. 57
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separately programmed, or to it must be done by hand calculation. So, it is only good for smaller circuits. Second, the circuit must be linearized before applying the method. On the other hand, FNP approach is more flexible and easily adhered with nonlinear and linear circuits. In addition, the pair allows the target circuit to follow the desired response provided by the model circuit. This, as far as we know, cannot be done by the direct approach. FNP can be implemented in circuit simulators with ideal controlled sources with very high gain or using op-amps. Thus the FNP approach is well suited and effective for analog circuit design. Remaining three examples confirms our statement. Example 2. In this example, our requirement is to design a bioamplifier for amplifying spikes from the nerves of cockroaches. The two design requirements are, the amplifier should amplify an input signal 150 times for obtaining a recognizable output signal. In addition, the filter setting should be such that the circuit needs to amplify the signals of 300Hz and above. This will effectively filter out other unwanted electrical noises. For realizing the bio-amplifier, we can use the topology [22] as shown in Fig. 7, which is an amplifier with voltage gain of 300 V/V with a different lower cut-off frequency.
Fig. 7. Topology for bio-amplifier.
As stated above, our design parameters are voltage gain and lower cut-off frequency. A voltage gain of 150 can be obtained from the bioamplifier by adding an extra feedback resistance RF between the base and collector terminals of Q2. So in first part of the design, our aim is to design the value of RF and it can be done with the help of the FNP arrangement as depicted in Fig. 8. In Fig. 8, gm1 ¼ gm2 ¼ 0.036 A/V, RA1 ¼ R1jjR2jjRi1 ¼ 695Ω, RA2 ¼ RC1jjRO1jjR3jjR4 ¼ 696Ω, RA3 ¼ RE2jjRE3 ¼ 167Ω and RA4 ¼ RC2jj RO2jjRL ¼ 2.36 kΩ. On simulating the circuit, we get value of RF as 11.78 kΩ. This is all about part 1 of the design and second part is the design for lower cut-off frequency FL. Fig. 9(a) shows the circuit arrangement for the design of FL. As we want to design lower cut-off frequency, we need to redesign the value of one of the coupling or bypass capacitor. In this case we can redesign C3 by employing the FNP arrangement. Here, the reference circuit and nullator together act as a fixator and at the same time its pairing norator replaces C3. Fig. 9(b) shows the impedance function of norator. Here reference circuit may be a band pass filter with voltage gain 150 and FL ¼ 300 Hz. A further analysis on the Bode plot of norator reveals that the plot has a magnitude of 24.216 dB at 500 Hz. This implies that the required value for C3 ¼ 19.6 μF. It is now necessary to check the correctness of the final circuit. Fig. 10 shows the Bode plots of the redesigned circuit. Magnitude plot shows that gain and lower cut-off frequency are very much close to the design and phase plot proves that the circuit is stable.
Fig. 8. Design of RF with the help of FNPs.
higher cut-off frequency FH, we must consider varying the transistor capacitors. Here, the second part of design uses a combination of reference circuit and nullor to lock to the desired frequency response. The pairing norator resides at the place of CC1. Then the AC sweep analysis is performed. This is valid because the arrangement is similar to that in first part of the design except that the simulation continues to a time ‘T’ as defined by the designer and norator generates data for each of the time steps ‘t’. Similarly we can explain the remaining three examples and the same theory is applicable for them. Comparing the two approaches, we can see that theoretically they respond similarly, but there are differences in their implementation. First, there is no commercially available circuit simulator so programmed to handle the direct analytical method. Thus, the method needs to be
Fig. 9. (a). Design of C3; (b) Bode plot for norator. 58
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Fig. 10. Bode plots of bio-amplifier; (a) magnitude; (b) phase.
Fig. 11. (a) Two stage MOS amplifier; (b) design of RF for a given input resistance.
Example 3. Here a two stage MOS amplifier [19] as shown in Fig. 11(a) is considered for redesigning. The amplifier originally has an input resistance of 50 kΩ, output resistance of 3.33 kΩ and a voltage gain of 23.7 V/V. In addition, it amplifies signals of all frequencies in between 585 Hz and 186 MHz. Our aim is to reduce its input resistance to 30 kΩ and higher cut-off frequency to 14 MHz without altering its voltage gain.
shows a wide bandwidth of (1.1 kHz–22.4 MHz) 22.39 MHz with a gain of 367 V/V. We require a bandwidth of 855 kHz without varying FL, i.e., FH should be reduced to 853.9 kHz. The design process starts by taking the linear equivalent model of two stage BJT amplifier. As we need to fix two parameters, viz. input resistance and gain, we need to apply two FNPs into the circuit, which can define two feedback components. One of the norator defines a feedback component, which is connected from collector of Q2 to base of Q1, and it can fix the input resistance at 1 kΩ. The second norator is connected between collector and base of Q2. The design arrangement is depicted in Fig. 15, where gm1 ¼ 0.0714 A/V and gm2 ¼ 0.1071 A/V.
The design process starts with creation of linear equivalent circuit, where we need to apply proper FNPs. The circuit arrangement is shown in Fig. 11(b), where, gm1 ¼ gm2 ¼ 0.01 A ⁄ V and remaining values of resistors are same as that in Fig. 11(a). The input fixator VS (1 V, 33.33 μA) fixes the input resistance of MOS amplifier at 30 kΩ, at the same time its pairing norator finds the feedback resistance RF to meet the design. Here simulation shows that value of RF is 21.74 kΩ. In the second part, we need to reduce the bandwidth of the MOS amplifier, so that it eliminates the signals above 14 MHz. Following the design procedure, we need a reference circuit with FH ¼ 14 MHz and gain 23.7 V/V. Here we have to design an extra capacitor to reduce the overall bandwidth. It can be placed in between gate and drain terminals of M2. Circuit arrangement for the design is shown in Fig. 12(a); where RF ¼ 21.74 kΩ, and CF ¼ 100 nF. All other components have values same as that in Fig. 11(a). Here the reference circuit and nullator together act as the fixator, and its pairing norator defines the capacitor. Simulating this circuit and analyzing the Z(s) plot for norator as shown in Fig. 12(b), we can conclude that the value of extra capacitor C3 is 1.85 pF. Finally, it is vital to analyze the Bode plots of redesigned circuit. They are shown in Fig. 13(a) and (b). Magnitude plot implies that the gain is 27.485 dB or 23.67 V/V and FH ¼ 14.3 MHz. Phase plot shows that the redesigned circuit is stable as per the feedback stability theory.
Fixator VS (1 V, 1 mA) fixes the input resistance at 1kΩ, at the same time, its pairing norator finds the value of RF1. Similarly, output fixator VO (300 V, 0) fixes the gain of the amplifier at 300 V/V, and its pairing norator finds the value of RF2. Simulation shows that value of RF1 and RF2 are 801.5 kΩ and 47.82 kΩ respectively. Now we can go for the second part of the design; ie, we need to reduce FH to 853.9 kHz from an undesired value of 22.4 MHz. We can. use a BPF of FL ¼ 1.1 kHz and FH ¼ 853.9 kHz as the reference circuit and follow the procedures as discussed in algorithm 2. A feedback capacitor CF is to be inserted parallel to RF1 and such a capacitor can decrease the higher cut-off frequency of the amplifier. The circuit setup for the design of CF is shown in Fig. 16(a) and the impedance function plot for norator is shown in Fig. 16(b). The transistor parameters βF1 ¼ 100 and βF2 ¼ 150. Here the norator corresponds to CF and by analyzing the Bode plot shown in Fig. 16(b), it is clear that Z(s) pass through 95.26 dB at 1 MHz. Therefore, we can find the value of CF for the desired FH as 2.75 pF. It is now necessary to check the Bode plots of the final circuit. Fig. 17(a) shows the magnitude plot and Fig. 17(b) shows the phase angle plot of the modified amplifier. Magnitude plot satisfies the gain and bandwidth, as it shows a gain of 49.54 dB or 300 V/V, FL ¼ 1.05 kHz and
Example 4. Here, a two stage common emitter-common base (CE-CB) BJT amplifier [19] as shown in Fig. 14 is considered for redesigning. The design requirements are, the amplifier should have a voltage gain of 300 V/V and its input resistance should be 1 kΩ. Originally, the amplifier 59
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Fig. 12. (a). Design of C3 for a given cut-off frequency; (b) Bode plot of norator.
Fig. 13. Bode plots of modified MOS amplifier; (a) magnitude; (b) phase.
FH ¼ 855 kHz. Phase plot indicates that the amplifier is stable, since it satisfies feedback stability theory.
makes a futile result with this approach by an improper application of FNPs into the target circuit, which means empirical skill of the designer plays an important role in getting fruitful designs. For fixing ‘x’ number of parameters, we need ‘x’ number of FNPs. Here ‘x’ number of norators denotes ‘x’ number of unknowns or components to be redesigned. Sometimes, a careful analysis of the circuit directly gives us the value(s) of one or more unknowns with less number of FNPs, which mean reduction in the designing time and effort. Again, the ‘unknown’ must have a close relationship with the parameter to be fixed, otherwise, the
5. Discussion This section portrays some of the key points of this study. Even though the proposed method produces affirmative results, a designer can
Fig. 14. Two stage CE-CB BJT amplifier.
Fig. 15. Design of RF1 and RF2. 60
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Fig. 16. a). Design of CF; (b) Bode plot for norator.
Fig. 17. Bode plots of modified two stage CE-CB BJT amplifier; (a) magnitude (b) phase.
‘feedback’ effect between fixator and norator preclude and thus the method fails. While talking about frequency response designs, there exist the classical low frequency techniques such as design using coupling capacitors and poles and zeros technique. Dealing with phase angle, magnitude and frequency of a system is difficult with the traditional coupling capacitor approach and it was proposed to go for poles and zeros to realize such designs [23]. However, extraction of poles and zeros from a circuit is still a difficult task [24]. That is the reason we go for Bode-plot approach in this work. Finally, Table 1 gives a comparison between the proposed work and other relevant works in this domain. This proves the importance of the work. The application of nullors as fixators is relatively new and is still under development. The FNPs are not adhered to a certain limited areas. Its scope is wide and a skillful designer can render the pair to a form
which is helpful to one's design tasks. The basic idea is to define the value of an unknown which is necessary to keep the parameter under consideration at a desired level without violating the laws and concepts in analog circuits. 6. Conclusions A method for the AC performance design of amplifier circuits is presented. This method uses fixator-norator pair for rendering an AC parameter into a proper supporting element say resistor, capacitor, or a two terminal sub-circuit containing passive elements. Such element(s) must be replaced with an existing circuit component, or added into the original circuit at proper place. The AC performance design process consists of two parts. First part deals with input and output resistance of the amplifier and its gain. Linear equivalent circuit of the targeted amplifier is vital for this part of the design. FNPs are inserted to such linear circuits in cohesion with the parameters to be fixed and it results in new feedback networks containing one or more passive component for each AC parameter. They should be DC isolated with capacitors which are AC short at the operating frequencies of the amplifier. Cut-off frequency and obviously the bandwidth are designed in the second part of the design. A reactive component is redesigned or an additional two terminal network containing reactive component is defined at the second part of the design by making use of a reference circuit. A conspicuous point to be noted is that, the reference circuit should possess a frequency response, which is closed to the expected response. Four examples have been worked out in this paper for better understanding of the proposed technique.
Table 1 Comparison between the proposed work and other relevant works. Author
Tool used
Details of work
Verhoeven et al. (2003) [15] Hashemian (2008) [16] Hashemian (2012) [3] Hashemian (2017) [18] Proposed work
Controlled sources Coupling capacitors Fixatornorator pair Fixatornorator pair Fixatornorator pair
Local sourcing, results in scattered supplies. Local biasing, results in scattered supplies. Biasing design, only resistive circuit is considered with no frequency component. Study limited to design of bandwidth. Design of AC parameters viz. input and output resistance, gain and bandwidth (cutoff frequencies).
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