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Assessment of technological and geometrical device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs
Solid-State Electronics 108 (2015) 36–41
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Assessment of technological and geometrical device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs M. Koyama a,b,⇑, M. Cassé a, S. Barraud a, G. Ghibaudo c, H. Iwai b, O. Faynot a, G. Reimbold a a b c
CEA LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France Frontier Research Center, Tokyo Institute of Technology, 4259 Nagatsuta-cho, Midori-ku, Yokohama 226-8502, Japan IMEP-LAHC, INPG-MINATEC, 3 Parvis Louis Neel, 38016 Grenoble Cedex 1, France
a r t i c l e
i n f o
Article history: Available online 11 February 2015 The review of this paper was arranged by B. Gunnar Malm Keywords: Si nanowire MOSFETs Omega-gate Strained-SOI Surface orientation Low-frequency noise Oxide trap density
a b s t r a c t A study of the gate oxide/channel interface quality in ultra-scaled SOI omega-gate nanowire NMOS FETs with cross-section as small as 10 nm 10 nm is experimentally presented by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, additional hydrogen anneal, or channel orientation difference. A method for rigorous contribution assessment of the two oxide/channel interfaces (top surface vs. side-walls) is also demonstrated. Quality of the interface is slightly altered among the 4-types of technological parameters and the structural variety down to nanowire. However, an excellent quality of Hf-based high-k/metal gate stack is observed and sustained in all the devices. In particular, efficient tensile strain stressor is demonstrated with high enhancement of the NMOS FET performance and preserved 1/f noise performance fulfilling the requirement for future CMOS logic node stated in the international technology roadmap for semiconductors. Ó 2015 Published by Elsevier Ltd.
1. Introduction One of the solutions for sustainable development of future CMOS technology nodes is multi-gate (MG) architectures, such as nanowire (NW) FETs [1–14]. These 3D devices provide greater electrostatic performance than conventional 2D MOSFETs. In addition, the strain technology introduced to the channel is a key feature for further enhancement of the FET performances [4–7]. At the same time, the quality and controllability of the multiple interfaces could be a serious issue. The channel surfaces with different crystallographic orientation among the interfaces (e.g. top surface vs. side-walls of NW, cf. Fig. 1) as well as the large channel surface/ volume ratio may contribute to the electrical characteristics in aggressively scaled MG devices. Moreover, the strain introduction to the channel may also influence the interface quality. Measurement of low-frequency noise (LFN) appearing in the drain current Id is a powerful diagnosis tool to evaluate the electrical properties of FET, even in the complex and scaled MG architectures [8–15]. In general, LFN spectra contain frequency, f dependent 1/f and 1/f2 ⇑ Corresponding author at: CEA LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France. Tel.: +334 38 78 18 43; fax: +334 38 78 51 40. E-mail address: [email protected] (M. Koyama). http://dx.doi.org/10.1016/j.sse.2014.12.010 0038-1101/Ó 2015 Published by Elsevier Ltd.
components, which are mainly dominated by charge traps in the gate oxide. Concerning 1/f noise, the origin is attributed to carrier number fluctuations with correlated mobility fluctuations (CNF + CMF) [16,17]. The LFN study based on CNF + CMF model in ultra-scaled NW FET has been effectively demonstrated, and the impact of device downscaling has been also investigated in our previous studies [13,14]. In this work, we present an experimental investigation of the oxide/channel interface quality by LFN characterization in omega-gate (X-gate) NW NMOS FETs with various technological splits. We demonstrate how the oxide trap density is influenced by the technological parameters: channel orientation ([1 1 0] or [1 0 0]), additional H2 anneal process, and tensile strained Si channel. 2. Devices and measurements The X-gate NW NMOS FETs (Fig. 1) were fabricated starting from undoped (0 0 1) SOI or strained-SOI (sSOI) wafers with 11 nm-thick Si or sSi and 145 nm-thick BOX, using the top-down approach [3–7]. The Si thickness is thus equivalent to the NW height (HNW). After etching, FET structures with top width Wtop from 10 lm (wide FET) down to 10 nm (the narrowest NW) have
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M. Koyama et al. / Solid-State Electronics 108 (2015) 36–41
been obtained. The gate length Lg is varying from 413 nm down to 22 nm. All the devices have a high-j/metal gate stack (HfSiON/TiN) leading to the EOT = 1.25 nm and the gate oxide capacitance
Cox 0.02 F/m2, which are both maintained down to the narrowest NWs. For sSOI substrate, 1.4 GPa biaxial tensile stress has been initially introduced. The NWs have finally a uniaxial tensile strain along the channel direction due to lateral strain relaxation [4–7]. Two different channel orientations ([1 1 0] or [1 0 0]) and additional H2 anneal have also been processed, and their impacts were investigated (Fig. 1). Id–Vg characteristics of the narrowest NW FETs with Lg 110 nm for all the technological splits are shown in Fig. 2. The Id data are normalized by the total effective width Wtot, which is simply given by Wtot = Wtop + 2HNW. The shift of threshold voltage Vt occurs from the variety of technological parameters. Meanwhile, almost ideal values of subthreshold slope (SS) and drain induced barrier lowering (DIBL) are maintained. The uniaxially strained NW demonstrates large Id enhancement of +100% compared to SOI case. LFN measurements were performed at room temperature under a probe level using a semi-automatic noise measurement system by Synergie Concept [18]. The power spectral density (PSD) of drain current noise SId was measured mainly in linear region of drain bias (Vd = 40 mV), and then up to saturation region (Vd = 0.9 V). Gate bias Vg varied from subthreshold to strong inversion regions. 3. Results and discussion
Fig. 1. Descriptions of the SOI X-gate NWs studied in this work, with a crosssectional TEM picture of the referential SOI NW. The table summarizes all the technological parameters for NMOS FETs.
Normalized drain current noise SId/Id2 as a function of frequency in SOI X-gate NWs is shown in Fig. 3. Although single devices show dispersion of noise curves, the averaged spectrum measured for 5 devices exhibits good 1/f noise behavior from threshold up to strong inversion regions. LFN characteristics showing 1/f noise can be interpreted by CNF + CMF model given by [16,17]:
SId I2d
4
10
Vd=0.9V Vd=40mV
Id (µA/µm)
10
SOI H2 anneal [100] -oriented sSOI
-2
10
-5
10
Lg=107-113nm Narrowest NW
-8
10 -0.5
2 2 gm Id 1 þ asc leff C ox SVfb Id gm
0.0
0.5
1.0
-5
10
1.5
Vg=Vt=0.46V
Vg (V)
0.46V
SS (mV/dec)
Id gain on SOI
61.2
324µA/µm (Vg=Vt=0.9V)
2
SOI ([110]-oriented)
DIBL (mV/V)
SId/Id (/Hz)
Vt
-9
10
Vg=0.9V -11
SOI with H2 anneal
0.42V
[100]-oriented SOI
0.48V
Strained-SOI (sSOI)
0.40V
62.5
+13.7%
60.8
+4.8%
SOI Ω-gate NW 1/f 5 devices Wtop=13nm, Lg=113nm
10
~23 -13
10
1
10
61.2
+98.8%
Fig. 2. Id–Vg characteristics of the narrowest NW FETs with Lg 110 nm for all the technological parameters. Basic properties for FET performance characterization are summarized in a table.
Vd=40mV Average
-7
10 Ω-gate NW FETs (Lg~110nm)
ð1Þ
where gm is the transconductance, asc is the Coulomb scattering coefficient, and SVfb is the PSD of flat-band voltage noise. The SId/ Id2 extracted at frequency f = 10 Hz as a function of Id is shown in Fig. 4. Actually, very good agreement between SId/Id2 plot and the corresponding (gm/Id)2 curve with normalization by the channel area parameters (Wtot and Lg) is observed. This indicates that the LFN properties in all the technological parameters are well described by CNF + CMF model. Moreover, the almost merged LFN data in Fig. 4a indicates that there is no significant influence of orientation difference ([1 1 0] vs. [1 0 0], and (0 0 1) top surface vs.
Normalized with Wtot=Wtop+2HNW
1
¼
2
10
3
10
4
10
Frequency, f (Hz) Fig. 3. Normalized drain current noise SId/Id2 as a function of frequency in the narrowest SOI NW FETs with Lg = 113 nm (bold line: average on 5 devices). This shows 1/f noise behavior in low-frequency region from threshold up to strong inversion regions.
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M. Koyama et al. / Solid-State Electronics 108 (2015) 36–41 -7
10
f=10Hz Vd=40mV
-12
10
-9
10
-8
10
-7
10
-6
2
SIdWtotLg/Id (µm /Hz)
10
2
-10
1/Wtot f=10Hz Vd=40mV Lg=107-113nm
-11
-12
-4
0.01
0.1
1
10
Wtot (µm)
-7
10
f=10Hz Vd=40mV
-8
2
-9
-10
-11
-12
10
SOI (Lg=113nm) Wtop=13nm Wtop=223nm with H2 anneal (Lg=107nm) Wtop=11nm Wtop=221nm -9
10
-8
10
-7
10
-6
10
-5
-7
f=10Hz Vd=40mV
(b) 10
10
10
2
10
-5
2
10
10
2
10
10
βWtotLg(gm/Id) (µm /V )
10
10
10
(b) 10
-9
10
-8
-9
2
10
[100]-oriented (Lg=108nm) Wtop=10nm Wtop=220nm
2
10
-11
10
-8
2
10
-10
SVfb (V /Hz)
10
[110]-oriented (Lg=113nm) Wtop=13nm Wtop=223nm
(V /Hz)
2 2
-9
2
SIdWtotLg/Id (µm /Hz)
10
10
βWtotLg(gm/Id) (µm /V )
10
SOI H2 anneal [100]-oriented sSOI
(a)
Vfb
(a) -8
-7
S
10
10
10
-4
-10
-11
1/Lg SOIsSOI Wtop=223nm Wtop=13nm
Wtop=221nm Wtop=11nm
-12
10
100
1000
Lg (nm) -7
10
-8
2
-9
2
10
-10
10
SOI (Lg=113nm) Wtop=13nm Wtop=223nm
2
2
-11
10
-12
10
10
sSOI (Lg=107nm) Wtop=11nm Wtop=221nm -9
10
-8
10
-7
2
SIdWtotLg/Id (µm /Hz)
10
βWtotLg(gm/Id) (µm /V )
f=10Hz Vd=40mV
(c)
Fig. 5. Flat-band voltage noise SVfb as a function of (a) the total effective channel width Wtot for all the technological splits at Lg 110 nm and (b) the gate length Lg for reference SOI and sSOI FETs. The SVfb increases simply in inverse proportion to both Wtot and Lg decrease.
regime, CNF factor is predominant, whereas CMF component is negligible, i.e. the coefficient (1 + ascleffCoxId/gm) in (1) reduces to 1. The proportionality constants b used in Fig. 4 thereby corresponds to the value of SVfb in the plateau region, where CNF noise can be approximated as [14]:
SId 10
-6
10
-5
10
-4
IdLg/Wtot (A) Fig. 4. Id dependent (symbols) drain current noise SId/Id2 and (lines) corresponding (gm/Id)2 curve characteristics normalized by channel area parameters (Wtot and Lg) for the narrowest NW and wide FETs with Lg 110 nm, comparing (a) [1 1 0]- with [1 0 0]-oriented SOI, (b) w/o with w/additional H2 anneal, and (c) SOI with sSOI devices.
(1 1 0) side-walls in [1 1 0]-oriented SOI) [15,19]. The wide FET processed with additional H2 anneal shows larger noise level in subthreshold (plateau-like) region, whereas the noise curve of NW perfectly agrees with the case w/o H2 anneal (Fig. 4b). In Fig. 4c, sSOI devices show slight noise level increase in the entire region for both wide and the narrowest NW cases. This can be partly attributed to the Id enhancement. For more detailed investigations, the SVfb value can be simply extracted by direct fitting of SId/Id2 versus (gm/Id)2 curves, in the subthreshold region showing the plateaued noise level. In this
I2d
2 2 g g b m SVfb m Id Id
ð2Þ
Extracted flat-band voltage noise SVfb shows roughly simple channel scaling effect, i.e. the noise level increases as the inverse of Wtot and Lg, without any large deviation from the different technological parameters in Fig. 5. It can be noticed that the noise level decrease due to the volume inversion, reported in SOI tri-gate NW FETs with SiO2/poly-Si gate stack [10], and in gate-all-around (GAA) Si NW FETs with in-situ steam-generated (ISSG) oxide/TiN gate stack [11], has not a large impact in our case. In our SOI-based X-gate NWs, the scaling regularity with both Wtot and Lg, without much quantum effect, could be attributed to the use of Hf-based high-j gate oxide (HfSiON) inducing more carrier trapping/de-trapping processes even in volume inversion. Since a direct tunneling process can be considered as the mechanism of physical carrier trapping and de-trapping between gate oxide and channel interfaces, then, the gate oxide trap density Nt (eV1 cm3) around quasi-Fermi energy level can be derived by using SVfb as [17,20]:
Nt ¼
fW tot Lg C 2ox SVfb q2 kTk
ð3Þ
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M. Koyama et al. / Solid-State Electronics 108 (2015) 36–41
where q is the elementary charge, kT is the thermal energy, and k is the tunnel attenuation length of the electron wave function in the gate oxide (0.1 nm for the Si/HfO2 system with SiO2 interfacial layer (IL) [21,22]). The Nt is thereby defined as an indicator of CNF influence, and the behavior computed from SVfb data (Fig. 5) for all the device parameters is shown in Fig. 6. The values are not significantly altered by the scaling effect of both Wtot and Lg. For the extracted Nt as a function of the Wtot in FETs with Lg 110 nm (Fig. 6a), slightly higher values of Nt are measured for sSOI and SOI with H2 anneal relative to reference SOI (nearly twice higher). This result is in agreement with previous work reporting higher interface trap density for H2 anneal in 3D-stacked Si NW FETs [2]. However, the Nt in both SOI and sSOI devices as a function of Lg is distributed with one decade of the Nt range due to device-to-device dispersion, especially in the narrowest NWs, (Fig. 6b). Some sSOI NWs thus have similar or lower Nt as compared to SOI NWs. For the oxide trap characteristics in strained Si FETs, both negative [23] and positive results [24] have been reported. Thus, the extrinsic process parameters are dominant compared with intrinsic tensile strain impact. Moreover, the Nt values from all the splits lie in similar order (1017–1018 eV1 cm3) as the values published for stateof-the-art Hf-based high-j/metal gate stack technology [21,25–28] and our previous works [13,14]. As a consequence, it is concluded that excellent oxide/interface quality is maintained in all our devices down to the narrowest NW FETs. For better assessment of the interface quality, a method of the Nt separation between top surface and side-wall contributions could be introduced as follows: top
þ
10
2HNW Nt W tot
SOI H2 anneal [100]-oriented sSOI
-1
-3
Nt (eV cm )
10
17
10
60
SVfb
ð5Þ
0.01
Intercept: Nt_side-wall
(a)
SOI H2 anneal [100] -oriented sSOI
50 40 30 20
Nt_top/2HNW
10
f=10Hz Vd=40mV Lg=107-113nm
16
2
70
(a)
18
Id gm
ð4Þ
sidewall
19
10
1 þ asc leff C ox
-3
W top Nt W tot
-1
¼
SId ¼ g 2m
17
tot
SVg ¼
(Wtot/2HNW)×Nt (×10 eV cm )
Nt
In our case, this relation of the Nt contribution can be approximated as Nt_tot 1/3Nt_top + 2/3Nt_side-wall for all the narrowest NW FETs. The method demonstration and extracted values of Nt_top and Nt_side-wall for devices with Lg 110 nm are shown in Fig. 7. The (1 0 0) plane, which corresponds to surface orientation of the top surface of reference [1 1 0]-oriented SOI, and to the orientation of both the top and side-walls of [1 0 0]-oriented SOI (cf. Fig. 1), show almost same the values. This similar value in (1 0 0) planes therefore confirms the reliability of the separating method. Surprisingly, the (1 1 0) plane in side-walls of [1 1 0]-oriented NW is moderately better than the (1 0 0) top. In the devices performed with additional H2 anneal, the (1 0 0) top surfaces degrades, whereas the quality of (1 1 0) side-walls are improved. Tensile strain relatively deteriorates both the top and side-wall surfaces compared to reference SOI devices. This detailed analysis is also well correlated with results shown in Fig. 4. Then, it was also studied how Vd variation up to saturation region impact the LFN properties. Vd dependence of the SId/Id2–Id characteristic in both the SOI and sSOI narrowest NW devices shows constant noise level in subthreshold (plateau-like) region for each case (Fig. 8). This means that SVfb and Nt are also nearly independent of Vd variation. Finally, gate voltage noise SVg transformed from measured SId was compared with ITRS requirements for LFN showing 1/f behavior [29] in Fig. 9. The relationship between SId and SVg is expressed as [16,17]:
0 0.0
0.1
0.2
0.1
0.5 6
Wtot (µm)
Nt_top Nt_side-wall
(b) 5
19 -3 17
10
17
10
16
t
-1
-3
Nt (eV cm )
10
18
4
-1
f=10Hz Vd=40mV
(b)
N (×10 eV cm )
10
0.3
Wtop (µm)
3 2 1 0
I
]-o rie
nt ed
Fig. 6. Gate oxide trap density Nt as a function of (a) the total effective channel width Wtot for all the technological parameters at Lg 110 nm and (b) the gate length Lg for reference SOI and sSOI FETs.
al ne
1000
00
an
100
Lg (nm)
O sS
[1
Wtop=221nm Wtop=11nm
2
10
Wtop=223nm Wtop=13nm
H
15
sSOI I SO
10
SOI
Fig. 7. (a) The demonstration and (b) extracted Nt components based on the Nt separation concept expressed as (4) for all the technological device parameters at Lg 110 nm.
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M. Koyama et al. / Solid-State Electronics 108 (2015) 36–41 -4
10
10
10
10
2
2
f=10Hz Lg=113nm Wtop=13nm
-5
-6
2
SId/Id (/Hz)
10
-7
Linear to saturation
-9 -9
10
10
10
1
10
-8
10
-7
10
-6
10
-5
10
-4
ITRS_HP ITRS_LSTP NW (Lg=22nm) NW (Lg=27nm)
1000 (b) sSOI 2
2
WtotLgfSVg (µm µV )
f=10Hz Lg=107nm Wtop=11nm
-5
-6
100
Linear to saturation
-7
10
-8
2026
ITRS data High performance (HP) for MG logic
Vd=0.9V -9
Vd=0.3V
10
2015
Vd=0.2V
-9
Vd=0.4V
1
Vd=40mV
-8
10
2026
2015
-4
2
SId/Id (/Hz)
10
Vd=0.3V
Vd=0.9V
(b) sSOI
10
Vd=0.4V
Vd=0.2V
Id (A)
10
100
Vd=40mV
-8
10
10
ITRS_HP ITRS_LSTP NW (Lg=23nm) NW (Lg=28nm)
1000 (a) SOI
(a) SOI
WtotLgfSVg (µm µV )
10
Year
10
-7
10
-6
10
-5
10
-4
Id (A) 2
Fig. 8. Id dependent (symbols) drain current noise SId/Id and (lines) corresponding (gm/Id)2 curves characteristics for varied Vd from linear (Vd = 40 mV, 0.2 V) to saturation (Vd = 0.9 V) regions in the (a) SOI and (b) sSOI narrowest NW FETs. Plateaued noise levels in subthreshold region are steady with varying Vd in both SOI and sSOI cases.
Table in Fig. 9 summarizes the ITRS requirements data of Lg, power supply voltage Vdd, and Vd (defined as Vd = Vdd/2) for high performance (HP) and low standby power (LSTP) logics constituted with MG FETs in 2015 and 2026. The SVg properties are extracted at overdrive operation (Vg = Vt + 0.2 V), where CMF factor is predominant, and in saturation regime (Vd = 0.3–0.4 V). The results reveal that the shortest and narrowest NWs in both SOI and sSOI devices with Lg = 22–28 nm almost fulfill currently the requirements for future CMOS technology node by 2026. Consequently, it is concluded that tensile strain effect is efficient for enhancements of both Id and 1/f LFN behavior without significant degradation of the interface quality. 4. Conclusion Oxide/channel interface properties in ultra-scaled X-gate NW NMOS FETs with cross-section as small as 10 nm 10 nm have been studied by LFN measurements. The investigation based on CNF + CMF model is effectively applied for the evaluation of various technological and architectural splits. The geometrical variations with channel top width Wtop and channel length Lg (Lg down to 22 nm) alter the LFN properties with simple impact of device scaling, which is reciprocal to total effective width Wtot and Lg. The separation of the contributions between top surface and side-walls of the channel has been studied in order to strictly assess the difference. It reveals that the interface quality of (1 0 0) top plane is relatively deteriorated compared to the (1 1 0) side-walls in all the [1 1 0]-oriented devices (reference SOI, SOI
Lg (nm) Vdd (V)
Vd (V)
Low Standby power (LSTP) logic Lg (nm) Vdd (V)
Vd (V)
2015
17
0.8
0.4
19.2
0.81
0.41
2026
5.9
0.57
0.29
7
0.54
0.27
Fig. 9. Input gate voltage noise SVg normalized by channel area (Wtop Lg) in the (a) SOI and (b) sSOI narrowest and shortest NW FETs compared with the requirement for 1/f LFN in ITRS 2013 edition (table RFAMS1: RF CMOS technology requirements) for future high performance (HP) and low standby power (LSTP) logic multi-gate FETs [29]. The data extracted at f = 10 Hz, and at Vg = Vt + 0.2 V. The table shows the ITRS requirements of gate length Lg, power supply voltage Vdd, and drain voltage Vd defined as Vd = Vdd/2 in 2015 and 2026.
with H2 anneal, and sSOI). In addition, our additional fabrication processes (H2 anneal and tensile strain) tend to slightly degrade the interface quality, which however remains well below 1018 eV1 cm3 of oxide trap density Nt. Therefore, an excellent quality of the interface with Hf-based high-j/metal gate stack is sustained for all our technological and geometrical device parameters down to the narrowest NWs. Drain bias variation does not significantly influence the LFN behaviors (CNF + CMF model and oxide trap density) in SOI and sSOI NWs regardless Lg scaling. In particular, uniaxial strain in sSOI NW efficiently enhances Id characteristics, and accomplishes the 1/f LFN requirements for future CMOS logic node with MG FETs stated in ITRS. It is thus well demonstrated that sSOI technology is a powerful and important booster of the NW FET performances. Acknowledgement This work was partially carried out in the frame of the ST/IBM/ LETI joint program and by the French Public Authorities through NANO 2017 program. References [1] Ferain I, Colinge CA, Colinge J-P. Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors. Nature 2011;479:310–6. [2] Cassé M, Tachi K, Thiele S, Ernst T. Spectroscopic charge pumping in Si nanowire transistors with a high-k/metal gate. Appl. Phys. Lett. 2010;96:123506.
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[15] Bennamane K, Boutchacha T, Ghibaudo G, Mouis M, Collaert N. DC and low frequency noise characterization of FinFET devices. Solid-State Electron 2009;53:1263–7. [16] Ghibaudo G, Roux O, Nguyen-Duc Ch, Balestra F, Brini J. Improved analysis of low frequency noise in field-effect MOS transistors. Phys Status Solidi A 1991;124:571–81. [17] von Haartman M, Östling M. Low-frequency noise in advanced MOS devices. Dordrecht: Springer; 2007. [18] Chroboczek JA. Automatic, wafer-level, low frequency noise measurements for the interface slow trap density evaluation. Proc ICMTS 2003:95–8. [19] Gaubert P, Teramoto A, Cheng W, Ohmi T. Relation between the mobility, 1/f noise, and channel direction in MOSFETs fabricated on (100) and (110) siliconoriented wafers. IEEE Trans Electron Dev 2010;57:1597–607. [20] Kingston RH. Semiconductor surface physics. Philadelphia: Univ. Pennsylvania Press; 1957. [21] Wang BC, Wu SL, Lu YY, Chang SJ, Chen JF, Tsai SC, et al. Comparison of the trap behavior between ZrO2 and HfO2 gate stack nMOSFETs by 1/f noise and random telegraph noise. IEEE Electron Dev Lett 2013;34:151–3. [22] Simoen E, Veloso A, Higuchi Y, Horiguchi N, Claeys C. On the oxide trap density and profiles of 1-nm EOT metal-gate last CMOS transistors assessed by lowfrequency noise. IEEE Trans Electron Dev 2013;60:3849–55. [23] Wang YP, Wu SL, Chang SJ. Low-frequency noise characteristics in strained-Si nMOSFETs. IEEE Electron Dev Lett 2007;28:36–8. [24] Simoen E, Eneman G, Verheyen P, Loo R, De Meyer K, Claeys C. Processing aspects in the low-frequency noise of nMOSFETs on strained-silicon substrates. IEEE Trans Electron Dev 2006;53:1039–47. [25] Lopez D, Haendler S, Leyris C, Bidal G, Ghibaudo G. Low-frequency noise investigation and noise variability analysis in high-k/metal gate 32-nm CMOS transistors. IEEE Trans Electron Dev 2011;58:2310–6. [26] Ioannidis EG, Haendler S, Bajolet A, Pahron T, Planes N, Arnaud F, et al. Low frequency noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors. IEDM Technol Dig 2011:449–52. [27] Theodorou CG, Ioannidis EG, Haendler S, Planes N, Arnaud F, Andrieu F, et al. Front-back gate coupling effect on 1/f noise in ultra-thin Si film FDSOI MOSFETs. Proc ESSDERC 2012:223–6. [28] Ioannidis EG, Dimitriadis CA, Haendler S, Bianchi RA, Jomaah J, Ghibaudo G. Improved analysis and modeling of low-frequency noise in nanoscale MOSFETs. Solid-State Electron 2012;76:54–9. [29] ITRS 2013 ed., RF and analog/mixed-signal technologies (RFAMS) 2013 tables [Online]; 2013. [accessed on 30.06.14].
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Assessment of technological and geometrical device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs M. Koyama a,b,⇑, M. Cassé a, S. Barraud a, G. Ghibaudo c, H. Iwai b, O. Faynot a, G. Reimbold a a b c
CEA LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France Frontier Research Center, Tokyo Institute of Technology, 4259 Nagatsuta-cho, Midori-ku, Yokohama 226-8502, Japan IMEP-LAHC, INPG-MINATEC, 3 Parvis Louis Neel, 38016 Grenoble Cedex 1, France
a r t i c l e
i n f o
Article history: Available online 11 February 2015 The review of this paper was arranged by B. Gunnar Malm Keywords: Si nanowire MOSFETs Omega-gate Strained-SOI Surface orientation Low-frequency noise Oxide trap density
a b s t r a c t A study of the gate oxide/channel interface quality in ultra-scaled SOI omega-gate nanowire NMOS FETs with cross-section as small as 10 nm 10 nm is experimentally presented by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, additional hydrogen anneal, or channel orientation difference. A method for rigorous contribution assessment of the two oxide/channel interfaces (top surface vs. side-walls) is also demonstrated. Quality of the interface is slightly altered among the 4-types of technological parameters and the structural variety down to nanowire. However, an excellent quality of Hf-based high-k/metal gate stack is observed and sustained in all the devices. In particular, efficient tensile strain stressor is demonstrated with high enhancement of the NMOS FET performance and preserved 1/f noise performance fulfilling the requirement for future CMOS logic node stated in the international technology roadmap for semiconductors. Ó 2015 Published by Elsevier Ltd.
1. Introduction One of the solutions for sustainable development of future CMOS technology nodes is multi-gate (MG) architectures, such as nanowire (NW) FETs [1–14]. These 3D devices provide greater electrostatic performance than conventional 2D MOSFETs. In addition, the strain technology introduced to the channel is a key feature for further enhancement of the FET performances [4–7]. At the same time, the quality and controllability of the multiple interfaces could be a serious issue. The channel surfaces with different crystallographic orientation among the interfaces (e.g. top surface vs. side-walls of NW, cf. Fig. 1) as well as the large channel surface/ volume ratio may contribute to the electrical characteristics in aggressively scaled MG devices. Moreover, the strain introduction to the channel may also influence the interface quality. Measurement of low-frequency noise (LFN) appearing in the drain current Id is a powerful diagnosis tool to evaluate the electrical properties of FET, even in the complex and scaled MG architectures [8–15]. In general, LFN spectra contain frequency, f dependent 1/f and 1/f2 ⇑ Corresponding author at: CEA LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France. Tel.: +334 38 78 18 43; fax: +334 38 78 51 40. E-mail address: [email protected] (M. Koyama). http://dx.doi.org/10.1016/j.sse.2014.12.010 0038-1101/Ó 2015 Published by Elsevier Ltd.
components, which are mainly dominated by charge traps in the gate oxide. Concerning 1/f noise, the origin is attributed to carrier number fluctuations with correlated mobility fluctuations (CNF + CMF) [16,17]. The LFN study based on CNF + CMF model in ultra-scaled NW FET has been effectively demonstrated, and the impact of device downscaling has been also investigated in our previous studies [13,14]. In this work, we present an experimental investigation of the oxide/channel interface quality by LFN characterization in omega-gate (X-gate) NW NMOS FETs with various technological splits. We demonstrate how the oxide trap density is influenced by the technological parameters: channel orientation ([1 1 0] or [1 0 0]), additional H2 anneal process, and tensile strained Si channel. 2. Devices and measurements The X-gate NW NMOS FETs (Fig. 1) were fabricated starting from undoped (0 0 1) SOI or strained-SOI (sSOI) wafers with 11 nm-thick Si or sSi and 145 nm-thick BOX, using the top-down approach [3–7]. The Si thickness is thus equivalent to the NW height (HNW). After etching, FET structures with top width Wtop from 10 lm (wide FET) down to 10 nm (the narrowest NW) have
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M. Koyama et al. / Solid-State Electronics 108 (2015) 36–41
been obtained. The gate length Lg is varying from 413 nm down to 22 nm. All the devices have a high-j/metal gate stack (HfSiON/TiN) leading to the EOT = 1.25 nm and the gate oxide capacitance
Cox 0.02 F/m2, which are both maintained down to the narrowest NWs. For sSOI substrate, 1.4 GPa biaxial tensile stress has been initially introduced. The NWs have finally a uniaxial tensile strain along the channel direction due to lateral strain relaxation [4–7]. Two different channel orientations ([1 1 0] or [1 0 0]) and additional H2 anneal have also been processed, and their impacts were investigated (Fig. 1). Id–Vg characteristics of the narrowest NW FETs with Lg 110 nm for all the technological splits are shown in Fig. 2. The Id data are normalized by the total effective width Wtot, which is simply given by Wtot = Wtop + 2HNW. The shift of threshold voltage Vt occurs from the variety of technological parameters. Meanwhile, almost ideal values of subthreshold slope (SS) and drain induced barrier lowering (DIBL) are maintained. The uniaxially strained NW demonstrates large Id enhancement of +100% compared to SOI case. LFN measurements were performed at room temperature under a probe level using a semi-automatic noise measurement system by Synergie Concept [18]. The power spectral density (PSD) of drain current noise SId was measured mainly in linear region of drain bias (Vd = 40 mV), and then up to saturation region (Vd = 0.9 V). Gate bias Vg varied from subthreshold to strong inversion regions. 3. Results and discussion
Fig. 1. Descriptions of the SOI X-gate NWs studied in this work, with a crosssectional TEM picture of the referential SOI NW. The table summarizes all the technological parameters for NMOS FETs.
Normalized drain current noise SId/Id2 as a function of frequency in SOI X-gate NWs is shown in Fig. 3. Although single devices show dispersion of noise curves, the averaged spectrum measured for 5 devices exhibits good 1/f noise behavior from threshold up to strong inversion regions. LFN characteristics showing 1/f noise can be interpreted by CNF + CMF model given by [16,17]:
SId I2d
4
10
Vd=0.9V Vd=40mV
Id (µA/µm)
10
SOI H2 anneal [100] -oriented sSOI
-2
10
-5
10
Lg=107-113nm Narrowest NW
-8
10 -0.5
2 2 gm Id 1 þ asc leff C ox SVfb Id gm
0.0
0.5
1.0
-5
10
1.5
Vg=Vt=0.46V
Vg (V)
0.46V
SS (mV/dec)
Id gain on SOI
61.2
324µA/µm (Vg=Vt=0.9V)
2
SOI ([110]-oriented)
DIBL (mV/V)
SId/Id (/Hz)
Vt
-9
10
Vg=0.9V -11
SOI with H2 anneal
0.42V
[100]-oriented SOI
0.48V
Strained-SOI (sSOI)
0.40V
62.5
+13.7%
60.8
+4.8%
SOI Ω-gate NW 1/f 5 devices Wtop=13nm, Lg=113nm
10
~23 -13
10
1
10
61.2
+98.8%
Fig. 2. Id–Vg characteristics of the narrowest NW FETs with Lg 110 nm for all the technological parameters. Basic properties for FET performance characterization are summarized in a table.
Vd=40mV Average
-7
10 Ω-gate NW FETs (Lg~110nm)
ð1Þ
where gm is the transconductance, asc is the Coulomb scattering coefficient, and SVfb is the PSD of flat-band voltage noise. The SId/ Id2 extracted at frequency f = 10 Hz as a function of Id is shown in Fig. 4. Actually, very good agreement between SId/Id2 plot and the corresponding (gm/Id)2 curve with normalization by the channel area parameters (Wtot and Lg) is observed. This indicates that the LFN properties in all the technological parameters are well described by CNF + CMF model. Moreover, the almost merged LFN data in Fig. 4a indicates that there is no significant influence of orientation difference ([1 1 0] vs. [1 0 0], and (0 0 1) top surface vs.
Normalized with Wtot=Wtop+2HNW
1
¼
2
10
3
10
4
10
Frequency, f (Hz) Fig. 3. Normalized drain current noise SId/Id2 as a function of frequency in the narrowest SOI NW FETs with Lg = 113 nm (bold line: average on 5 devices). This shows 1/f noise behavior in low-frequency region from threshold up to strong inversion regions.
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M. Koyama et al. / Solid-State Electronics 108 (2015) 36–41 -7
10
f=10Hz Vd=40mV
-12
10
-9
10
-8
10
-7
10
-6
2
SIdWtotLg/Id (µm /Hz)
10
2
-10
1/Wtot f=10Hz Vd=40mV Lg=107-113nm
-11
-12
-4
0.01
0.1
1
10
Wtot (µm)
-7
10
f=10Hz Vd=40mV
-8
2
-9
-10
-11
-12
10
SOI (Lg=113nm) Wtop=13nm Wtop=223nm with H2 anneal (Lg=107nm) Wtop=11nm Wtop=221nm -9
10
-8
10
-7
10
-6
10
-5
-7
f=10Hz Vd=40mV
(b) 10
10
10
2
10
-5
2
10
10
2
10
10
βWtotLg(gm/Id) (µm /V )
10
10
10
(b) 10
-9
10
-8
-9
2
10
[100]-oriented (Lg=108nm) Wtop=10nm Wtop=220nm
2
10
-11
10
-8
2
10
-10
SVfb (V /Hz)
10
[110]-oriented (Lg=113nm) Wtop=13nm Wtop=223nm
(V /Hz)
2 2
-9
2
SIdWtotLg/Id (µm /Hz)
10
10
βWtotLg(gm/Id) (µm /V )
10
SOI H2 anneal [100]-oriented sSOI
(a)
Vfb
(a) -8
-7
S
10
10
10
-4
-10
-11
1/Lg SOIsSOI Wtop=223nm Wtop=13nm
Wtop=221nm Wtop=11nm
-12
10
100
1000
Lg (nm) -7
10
-8
2
-9
2
10
-10
10
SOI (Lg=113nm) Wtop=13nm Wtop=223nm
2
2
-11
10
-12
10
10
sSOI (Lg=107nm) Wtop=11nm Wtop=221nm -9
10
-8
10
-7
2
SIdWtotLg/Id (µm /Hz)
10
βWtotLg(gm/Id) (µm /V )
f=10Hz Vd=40mV
(c)
Fig. 5. Flat-band voltage noise SVfb as a function of (a) the total effective channel width Wtot for all the technological splits at Lg 110 nm and (b) the gate length Lg for reference SOI and sSOI FETs. The SVfb increases simply in inverse proportion to both Wtot and Lg decrease.
regime, CNF factor is predominant, whereas CMF component is negligible, i.e. the coefficient (1 + ascleffCoxId/gm) in (1) reduces to 1. The proportionality constants b used in Fig. 4 thereby corresponds to the value of SVfb in the plateau region, where CNF noise can be approximated as [14]:
SId 10
-6
10
-5
10
-4
IdLg/Wtot (A) Fig. 4. Id dependent (symbols) drain current noise SId/Id2 and (lines) corresponding (gm/Id)2 curve characteristics normalized by channel area parameters (Wtot and Lg) for the narrowest NW and wide FETs with Lg 110 nm, comparing (a) [1 1 0]- with [1 0 0]-oriented SOI, (b) w/o with w/additional H2 anneal, and (c) SOI with sSOI devices.
(1 1 0) side-walls in [1 1 0]-oriented SOI) [15,19]. The wide FET processed with additional H2 anneal shows larger noise level in subthreshold (plateau-like) region, whereas the noise curve of NW perfectly agrees with the case w/o H2 anneal (Fig. 4b). In Fig. 4c, sSOI devices show slight noise level increase in the entire region for both wide and the narrowest NW cases. This can be partly attributed to the Id enhancement. For more detailed investigations, the SVfb value can be simply extracted by direct fitting of SId/Id2 versus (gm/Id)2 curves, in the subthreshold region showing the plateaued noise level. In this
I2d
2 2 g g b m SVfb m Id Id
ð2Þ
Extracted flat-band voltage noise SVfb shows roughly simple channel scaling effect, i.e. the noise level increases as the inverse of Wtot and Lg, without any large deviation from the different technological parameters in Fig. 5. It can be noticed that the noise level decrease due to the volume inversion, reported in SOI tri-gate NW FETs with SiO2/poly-Si gate stack [10], and in gate-all-around (GAA) Si NW FETs with in-situ steam-generated (ISSG) oxide/TiN gate stack [11], has not a large impact in our case. In our SOI-based X-gate NWs, the scaling regularity with both Wtot and Lg, without much quantum effect, could be attributed to the use of Hf-based high-j gate oxide (HfSiON) inducing more carrier trapping/de-trapping processes even in volume inversion. Since a direct tunneling process can be considered as the mechanism of physical carrier trapping and de-trapping between gate oxide and channel interfaces, then, the gate oxide trap density Nt (eV1 cm3) around quasi-Fermi energy level can be derived by using SVfb as [17,20]:
Nt ¼
fW tot Lg C 2ox SVfb q2 kTk
ð3Þ
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M. Koyama et al. / Solid-State Electronics 108 (2015) 36–41
where q is the elementary charge, kT is the thermal energy, and k is the tunnel attenuation length of the electron wave function in the gate oxide (0.1 nm for the Si/HfO2 system with SiO2 interfacial layer (IL) [21,22]). The Nt is thereby defined as an indicator of CNF influence, and the behavior computed from SVfb data (Fig. 5) for all the device parameters is shown in Fig. 6. The values are not significantly altered by the scaling effect of both Wtot and Lg. For the extracted Nt as a function of the Wtot in FETs with Lg 110 nm (Fig. 6a), slightly higher values of Nt are measured for sSOI and SOI with H2 anneal relative to reference SOI (nearly twice higher). This result is in agreement with previous work reporting higher interface trap density for H2 anneal in 3D-stacked Si NW FETs [2]. However, the Nt in both SOI and sSOI devices as a function of Lg is distributed with one decade of the Nt range due to device-to-device dispersion, especially in the narrowest NWs, (Fig. 6b). Some sSOI NWs thus have similar or lower Nt as compared to SOI NWs. For the oxide trap characteristics in strained Si FETs, both negative [23] and positive results [24] have been reported. Thus, the extrinsic process parameters are dominant compared with intrinsic tensile strain impact. Moreover, the Nt values from all the splits lie in similar order (1017–1018 eV1 cm3) as the values published for stateof-the-art Hf-based high-j/metal gate stack technology [21,25–28] and our previous works [13,14]. As a consequence, it is concluded that excellent oxide/interface quality is maintained in all our devices down to the narrowest NW FETs. For better assessment of the interface quality, a method of the Nt separation between top surface and side-wall contributions could be introduced as follows: top
þ
10
2HNW Nt W tot
SOI H2 anneal [100]-oriented sSOI
-1
-3
Nt (eV cm )
10
17
10
60
SVfb
ð5Þ
0.01
Intercept: Nt_side-wall
(a)
SOI H2 anneal [100] -oriented sSOI
50 40 30 20
Nt_top/2HNW
10
f=10Hz Vd=40mV Lg=107-113nm
16
2
70
(a)
18
Id gm
ð4Þ
sidewall
19
10
1 þ asc leff C ox
-3
W top Nt W tot
-1
¼
SId ¼ g 2m
17
tot
SVg ¼
(Wtot/2HNW)×Nt (×10 eV cm )
Nt
In our case, this relation of the Nt contribution can be approximated as Nt_tot 1/3Nt_top + 2/3Nt_side-wall for all the narrowest NW FETs. The method demonstration and extracted values of Nt_top and Nt_side-wall for devices with Lg 110 nm are shown in Fig. 7. The (1 0 0) plane, which corresponds to surface orientation of the top surface of reference [1 1 0]-oriented SOI, and to the orientation of both the top and side-walls of [1 0 0]-oriented SOI (cf. Fig. 1), show almost same the values. This similar value in (1 0 0) planes therefore confirms the reliability of the separating method. Surprisingly, the (1 1 0) plane in side-walls of [1 1 0]-oriented NW is moderately better than the (1 0 0) top. In the devices performed with additional H2 anneal, the (1 0 0) top surfaces degrades, whereas the quality of (1 1 0) side-walls are improved. Tensile strain relatively deteriorates both the top and side-wall surfaces compared to reference SOI devices. This detailed analysis is also well correlated with results shown in Fig. 4. Then, it was also studied how Vd variation up to saturation region impact the LFN properties. Vd dependence of the SId/Id2–Id characteristic in both the SOI and sSOI narrowest NW devices shows constant noise level in subthreshold (plateau-like) region for each case (Fig. 8). This means that SVfb and Nt are also nearly independent of Vd variation. Finally, gate voltage noise SVg transformed from measured SId was compared with ITRS requirements for LFN showing 1/f behavior [29] in Fig. 9. The relationship between SId and SVg is expressed as [16,17]:
0 0.0
0.1
0.2
0.1
0.5 6
Wtot (µm)
Nt_top Nt_side-wall
(b) 5
19 -3 17
10
17
10
16
t
-1
-3
Nt (eV cm )
10
18
4
-1
f=10Hz Vd=40mV
(b)
N (×10 eV cm )
10
0.3
Wtop (µm)
3 2 1 0
I
]-o rie
nt ed
Fig. 6. Gate oxide trap density Nt as a function of (a) the total effective channel width Wtot for all the technological parameters at Lg 110 nm and (b) the gate length Lg for reference SOI and sSOI FETs.
al ne
1000
00
an
100
Lg (nm)
O sS
[1
Wtop=221nm Wtop=11nm
2
10
Wtop=223nm Wtop=13nm
H
15
sSOI I SO
10
SOI
Fig. 7. (a) The demonstration and (b) extracted Nt components based on the Nt separation concept expressed as (4) for all the technological device parameters at Lg 110 nm.
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M. Koyama et al. / Solid-State Electronics 108 (2015) 36–41 -4
10
10
10
10
2
2
f=10Hz Lg=113nm Wtop=13nm
-5
-6
2
SId/Id (/Hz)
10
-7
Linear to saturation
-9 -9
10
10
10
1
10
-8
10
-7
10
-6
10
-5
10
-4
ITRS_HP ITRS_LSTP NW (Lg=22nm) NW (Lg=27nm)
1000 (b) sSOI 2
2
WtotLgfSVg (µm µV )
f=10Hz Lg=107nm Wtop=11nm
-5
-6
100
Linear to saturation
-7
10
-8
2026
ITRS data High performance (HP) for MG logic
Vd=0.9V -9
Vd=0.3V
10
2015
Vd=0.2V
-9
Vd=0.4V
1
Vd=40mV
-8
10
2026
2015
-4
2
SId/Id (/Hz)
10
Vd=0.3V
Vd=0.9V
(b) sSOI
10
Vd=0.4V
Vd=0.2V
Id (A)
10
100
Vd=40mV
-8
10
10
ITRS_HP ITRS_LSTP NW (Lg=23nm) NW (Lg=28nm)
1000 (a) SOI
(a) SOI
WtotLgfSVg (µm µV )
10
Year
10
-7
10
-6
10
-5
10
-4
Id (A) 2
Fig. 8. Id dependent (symbols) drain current noise SId/Id and (lines) corresponding (gm/Id)2 curves characteristics for varied Vd from linear (Vd = 40 mV, 0.2 V) to saturation (Vd = 0.9 V) regions in the (a) SOI and (b) sSOI narrowest NW FETs. Plateaued noise levels in subthreshold region are steady with varying Vd in both SOI and sSOI cases.
Table in Fig. 9 summarizes the ITRS requirements data of Lg, power supply voltage Vdd, and Vd (defined as Vd = Vdd/2) for high performance (HP) and low standby power (LSTP) logics constituted with MG FETs in 2015 and 2026. The SVg properties are extracted at overdrive operation (Vg = Vt + 0.2 V), where CMF factor is predominant, and in saturation regime (Vd = 0.3–0.4 V). The results reveal that the shortest and narrowest NWs in both SOI and sSOI devices with Lg = 22–28 nm almost fulfill currently the requirements for future CMOS technology node by 2026. Consequently, it is concluded that tensile strain effect is efficient for enhancements of both Id and 1/f LFN behavior without significant degradation of the interface quality. 4. Conclusion Oxide/channel interface properties in ultra-scaled X-gate NW NMOS FETs with cross-section as small as 10 nm 10 nm have been studied by LFN measurements. The investigation based on CNF + CMF model is effectively applied for the evaluation of various technological and architectural splits. The geometrical variations with channel top width Wtop and channel length Lg (Lg down to 22 nm) alter the LFN properties with simple impact of device scaling, which is reciprocal to total effective width Wtot and Lg. The separation of the contributions between top surface and side-walls of the channel has been studied in order to strictly assess the difference. It reveals that the interface quality of (1 0 0) top plane is relatively deteriorated compared to the (1 1 0) side-walls in all the [1 1 0]-oriented devices (reference SOI, SOI
Lg (nm) Vdd (V)
Vd (V)
Low Standby power (LSTP) logic Lg (nm) Vdd (V)
Vd (V)
2015
17
0.8
0.4
19.2
0.81
0.41
2026
5.9
0.57
0.29
7
0.54
0.27
Fig. 9. Input gate voltage noise SVg normalized by channel area (Wtop Lg) in the (a) SOI and (b) sSOI narrowest and shortest NW FETs compared with the requirement for 1/f LFN in ITRS 2013 edition (table RFAMS1: RF CMOS technology requirements) for future high performance (HP) and low standby power (LSTP) logic multi-gate FETs [29]. The data extracted at f = 10 Hz, and at Vg = Vt + 0.2 V. The table shows the ITRS requirements of gate length Lg, power supply voltage Vdd, and drain voltage Vd defined as Vd = Vdd/2 in 2015 and 2026.
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