InP HEMTs

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Materials Science and Engineering C 28 (2008) 676 – 679 www.elsevier.com/locate/msec

Influence of interface states and deep levels on output characteristics of InAlAs/InGaAs/InP HEMTs S. Bouzgarrou a,⁎, Na. Sghaier c , M.M. Ben Salem b , A. Souifi d , A. Kalboussi a a

d

Laboratoire de Microélectronique et Instrumentation (LMI), Département de physique, Faculté des Sciences de Monastir, Avenue de l'environnement 5000 Monastir, Tunisia b Laboratoire de Physique des Semiconducteurs et des Composants Electroniques, Faculté des Sciences de Monastir, Tunisia c Equipe Photothermie, composants électroniques, Structures Mécaniques (PCSM), Institut Préparatoire aux Etudes d'Ingénieurs de Nabeul (IPEIN), Campus universitaire EL Merazka, 8000 Nabeul, Tunisia Institut de Nanotechnologie de Lyon (INL) « site INSA », INSA de Lyon, Avenue Jean Capelle, Bâtiment Blaise Pascal, 69621 Villeurbanne cedex, France Available online 18 October 2007

Abstract The aim of this work is to study the origin of parasitic effects observed on the output characteristics of InAlAs/InGaAs/InP HEMTs with various buffer layers. Ids − Vds measurements as a function of the temperature have first been performed. Several anomalies were observed such as kink and hysteresis effects. C-DLTS measurements have also been performed. From the obtained results, we have established a strong correlation between parasitic effects observed on the output characteristics and deep levels located near the buffer layer interface. © 2007 Elsevier B.V. All rights reserved. Keywords: HEMT; CDLTS; Kink effect; Hysteresis effect

1. Introduction High electron mobility transistors (HEMTs) are very interesting devices (since their introduction) [1] as active devices for high speed and high frequency integrated circuits. The low switching time and low power consumption resulting from superior electronic transport properties of the active channel, the large sheet carrier concentration and the good confinement of 2 DEG at the heterointerface make HEMTs suitable for high speed applications. Furthermore, large conduction band discontinuity leads to reduce impurity scattering resulting from high electron mobility and high saturation velocity. So the large conduction band discontinuity between InAlAs and InGaAs [2] compared to AlGaAs/GaAs is an important feature of InAlAs/ InGaAs heterostructure to improve device performance. Very high operation frequencies have already been obtained on InAlAs/InGaAs high electron mobility transistors (HEMTs), but trap-related parasitic effects are often the cause of performance

⁎ Corresponding author. Tel.: +216 95365171; fax: +216 73500278. E-mail address: [email protected] (S. Bouzgarrou). 0928-4931/$ - see front matter © 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.msec.2007.10.075

limitations. So the improvement of these devices' performance requires a good knowledge of the defects present in the structures. However, InAlAs deep levels are not well known yet, despite a great number of studies [3–6]. In this paper, we present a detailed study of electrically active defects present in InAlAs/InGaAs/InP heterostructure HEMT transistor grown by Metal Organic Chemical Vapor Deposition (MOCVD), using current deep level transient spectroscopy (CDLTS) technique. This investigation shows that we have achieved a substantial improvement in the quality of MOCVD In0.52Al0.48As by using a high quality buffer layer. Although these HEMTs are the most promising candidates for the active devices, they still have some drawbacks observed on the output characteristics that have to be eliminated. Kink effect and hysteresis effect are one of these anomalous find in Ids (Vds) characteristics. 2. Device fabrication The investigated transistors are fabricated on commercially supplied epitaxial structure grown by Metal Organic Chemical Vapor phase Deposition (MOCVD) on semi-insulating Fe-

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Fig. 1. Schematic cross-sectional diagram of the InAlAs/InGaAs/InP HEMT.

doped InP substrates. This structure presents a simple channel InGaAs/InP. Fig. 1 shows the structure of HEMT transistor which is mainly characterized in this paper. The lattice matched structure consists of a 1000 Å undoped InP buffer layer, a 500 Å sulphur doped InP channel (n = 2 × 1017 cm− 3), a 500 Å In0.52Al0.48As spacer layer, a 50 Å In0.53 Ga0.48As barrier, and a 100 Å greatly doped In0.53Ga0.48As (5 × 1018 cm− 3) contact layer. The transistor was realized by wet chemical etching followed by Au/Ge/Ni deposition and annealing for ohmic contacts. Silicon nitride (Si3N4) was then deposited by UV-CVD, leaving the device edges and substrate regions covered with dielectric. After

Fig. 3. Characteristics Ids − Vds at T = 120 K (A), T = 300 K (B) and T = 350 K (c).

the gate lithography, the InGaAs cap layer was selectively etched down to the InGaAs barrier layer with a citric acid/hydrogen peroxide solution. For gate contact (1 μm length) Ti and Au were evaporated and lifted-off [6]. Typical output characteristics present good pinch-off values (close to the expected value of −1 V) and a very low gate leakage current (Igs = 4 nA/mm). These excellent values make the transistor suitable for high sensitivity integrated photoreceiver applications. 3. Electrical characterization

Fig. 2. Ids (Vds) characteristics at T = 120 K (A) and T = 350 K (B) of the InAlAs/ InGaAs/InP HEMT transistor.

The drain source current–voltage Ids (Vds) characteristics of the InGaAs/InP simple channel HEMT transistor, have been performed at different temperatures (between 120 K and 350 K) and for different gate–source voltages (Vgs); the corresponding

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S. Bouzgarrou et al. / Materials Science and Engineering C 28 (2008) 676–679

Fig. 4. Current deep level transient spectroscopy spectrum.

Fig. 6. Variations of the kink current Δ Id0 as a function of temperature.

results are shown in Fig. 2. The pinced voltage “Vt” extracted from these last characteristics varies from − 0.5 V to − 0.8 V and it depends on the gate length and temperature. We notice however, that the drain–source current continues to increase even in the saturation region. This unusual variation of the drain–source current is well known as kink effect [8,9], which was previously observed on AlGAs/GaAs [7]. This anomaly consists of a sharp increase in the drain–source current at a certain drain–source voltage (Vds = Vkink). This variation of the drain current induces an increase of the drain/source output conductance (gds) and a decrease of the amplification factor. This effect is previously observed on AlGaAs/GaAs, AlGaAs/InGaAs HEMTs and HFETs and silicon-on-insulator metal-oxide-semiconductor FETs (SOI-MOSFETs) [10,11]. As we can easily observe, there is an important kink effect present in the Ids (Vds) characteristics using this structure, especially at low temperatures. Whereas for high temperatures this effect disappears and Ids − Vds characteristics show a classical variation without anomalies. Another parasitic effect is also present in the Ids (Vds) characteristics; it is characterized by a shift of the Ids − Vds curve when the gate tension varies in one way and then back. This shift is observed at low temperatures (100 K) as well as at room temperature (300 K), whereas at 350 K it is absent. Fig. 3 illustrates this effect for three different temperatures.

In order to study the possible origin of these parasitic effects observed in our structure, we propose in the next section a detailed analysis of deep levels using C-DLTS technique.

Fig. 5. Spectra Ids − Vds showing the kink current Δ Id0.

4. Deep levels analysis The gate surface of our transistor is very small (0.8 μm × 0.5 μm) and (1 μm × 0.5 μm), and thus, the gate capacitance is also very small. In such a case, it is not appropriate to use the Capacitance Transient Spectroscopy (DLTS) for deep level analysis; drain current Transient Spectroscopy (CDLTS) is a more reliable tool for our purpose [12,13]. This very sensitive technique allows us to determine the location of the traps in the structure. A reverse bias was applied on the gate and positive pulses were superimposed to probe the channel region and/or the barrier layer. We sweep temperature between 77 K and 400 K, and we use the boxcar technique (SULA Technologies CTS/DLTS unit). In Fig. 4 we show the normalized drain current DLTS spectrum of our sample. One electron trap is detected with an activation energy of Ec − 0.2 eV. 5. Discussion Ids − Vds measurement shows the apparition of a kink effect which is observed at a particular drain–source voltage named

Fig. 7. Variations of the area comprised between the two go–return Ids − Vds curves as a function of temperature.

S. Bouzgarrou et al. / Materials Science and Engineering C 28 (2008) 676–679 Table 1 Parameters of different traps observed in the transistor studied by CDLTS and Ids (Vds) measurements Defect

CDLTS

Δ Id0

Area

Ea = 0.2 eV –

T = 250 K –

T = 250 K T = 150 K

T = 250 K T = 150 K

kink voltage (Vkink). The value of Vkink depends on the kink temperature appearing. While increasing the temperature, the kink voltage (Vkink) shifts to higher values. The drain current depends on both the direction and the voltage variation. Hysteresis effects are also observed for this transistor for different temperatures, which is characterized by a shift of the Ids − Vds curve when the gate tension varies in one way and then back (Fig. 3). This last figure shows that the kink effect is also present in Ids − Vds characteristic when we perform a go–return gate voltage. Kink effect is represented by the increase of drain–source current. This increasing is well observed if we draw the kink effect characteristics in the same spectrum with the ideal characteristics. The comparison of these characteristics shows a shift which is expressed by kink current Δ Id0 explained in Fig. 5. The variation of the kink current Δ Id0 as a function of temperature (Fig. 6) presents two peaks: the first one at 250 K and the second one at 150 K. In the same time, the area separating the two go–return Ids −Vds curves (Fig. 3), plotted as a function of temperature (Fig. 7) has shown, also, the presence of two peaks observed at 150 K and 250 K (Table 1). To study the origin of these two peaks, a detailed study of deep levels using Current Deep Levels Transient Spectroscopy (CDLTS) technique was performed. The investigation of our sample has revealed the presence of a defect located at Ec − 0.2 eV and which appears at a temperature ranging between 220 K and 270 K. The variation of the kink current ΔId0 (Fig. 6) and the area separating the two go–return Ids −Vds curves (Fig. 7), plotted as a function of temperature, show the presence of a peak which is observed at a temperature in the order of 250 K. We can then attribute the parasitic kink and hysteresis effects to the presence of defect observed in our transistor by CDLTS technique. This direct correlation was the aim of our previous work [14]. The variation of the kink current ΔId0 (Fig. 6) as a function of temperature shows the presence of a second peak at a bout 150 K temperature range. In the same time, the area separating the two go–return Ids − Vds curves (Fig. 7), plotted as a function of temperature, shows the presence of a second peak in the same range of temperature. We expect that a corresponding defect would be observed by CDLTS in the same range of temperature. CDLTS spectra (Fig. 4) does not show such a defect. It may be due to the non-activation of this defect in the chosen CDLTS conditions.

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6. Conclusion In summary, we have investigated static measurements and defects analysis on InAlAs/InGaAs/InP heterojunction HEMTs transistors grown by MOCVD. Drain–source current as a function of drain–source voltage characteristics shows the apparition of two anomalies: kink effect and hysteresis effect. The variation of the kink current Δ Id0 as a function of temperature shows the presence of two peaks observed one at 150 K and the second one at 250 K. The variation of the area comprised between the two go–return Ids − Vds characteristics plotted as a function of temperature make shower, also, the apparition of two peaks at the same temperature (150 K and 250 K). Defects analysis performed on this transistor by CDLTS technique prove the presence of a dominant trap with activation energy Ec − 0.20 eV. This defect has been observed at a temperature ranging at about 250 K, which is the same temperature of the apparition of the two parasitic effects. We can attribute this defect to parasitic kink and hysteresis effect observed on the output characteristics. References [1] D. Delagebeaudeuf, N.T. Linh, IEEE Trans. Electron Devices 29 (1982) 955. [2] D.F. Weslch, G.W. Wicks, L.F. Eastman, J. Appl. Phys. 55 (1984) 3176. [3] T. Sato, S. Uno, T. Hashizume, H. Hasegawa, Jpn. J. Appl. Phys. 36 (3B) (1997) 1811. [4] P.S. Whitney, W. Lee, C.G. Fonstad, J. Vac. Sci. Technol., B 5 (3) (1987) 796. [5] K.P. Korona, A. Wysmpołek, R. Bożek, M. Kamińska, J.M. Baranowski, Acta Phys. Pol. 82 (5) (1992) 825. [6] A. Kalboussi, G. Marrakchi, A. Tabata, G. Guillot, G. Halkias, K. Zekentes, A. Georgakilas, A. Cristou, Mater. Sci. Eng. B22 (1993) 93. [7] H. Maher, J. Décobert, G. Post, Nationales Micro-Optoélectron. Chantilly (France), 1997, p. 172. [8] A.A. Mooljii, S.R. Bahli, J.A. Del Alamo, IEEE Electron Device Lett. 15 (1994) 313. [9] Y. Hori, M. Kuzuhara, IEEE Trans. Electron Devices 41 (1994) 2262. [10] A. Souifi, B. Georgescu, G. Brémond, M.A. Py, J. Décobert, G. Guillot, IPRM, Suisse, Lausane, 1999. [11] A. Souifi, B. Georgescu, G. Brémond, M.A. Py, J. Décobert, G. Post, G. Guillot, Proceeding of the 11th International Conference on Idium Phosphide and Related Materials, 1999, p. 487. [12] B. Georgescu, M.A. Py, A. Souifi, G. Post, G. Guillot, IEEE Electron Device Lett. 19 (1998) 154. [13] N. Sghaier, S. Bouzgarrou, M.M. Ben Salem, A. Souifi, A. Kalboussi, G. Guillot, Mater. Sci. Eng., B 121 (2005) 178. [14] M.M. Ben Salem, S. Bouzgarrou, N. Sghaier, A. Kalboussi, A. Souifi, Mater. Sci. Eng., B 127 (2006) 134.