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Silicon-gate C-MOS chips gain immunity to SCR latchup
592
World Abstracts on Microelectronics and Reliability
electrically induced latch-up circuit paths in a variety of commercially available bulk CMOS devices. The method and results are compared to those reported by others using electron beam induced current and liquid crystal techniques.
cannot be clearly identified, and different technologies could favor different SOl approaches. VHSIC/VLS1 packaging update. RON ISCOFF. Semicomluctor Int. 52 (July 19'83). The greater complexity and faster operating speeds of today's integrated circuits are among the forces driving the semiconductor industry to review device packaging choices.
ComparisonofdifferentSOItechnologies:assetsandliabilities. L. JASTRZEBSKI. RCA Rev. 44, 250 (June 1983). Different methods used to obtain silicon-over-insulator (SOI) films are compared, based on the information available in the literature. All techniques are briefly outlined and their assets and liabilities are compared with special emphasis on application in different present and future processing technologies, It seems that at the present stage of development the "leader"
Techniques of wire bond testing. PETER H. SIN¢;ER. Semiconductor Int. 76 (July 1983). Destructive pull testing is still the most commonly used method of checking wire bond quality, but nondestructive pull tests and ball bond shear tests are increasing in popularity.
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S ,
SYSTEMS
AND
EQUIPMENTS
Scan-path logic integrated on chip tests gate array. KEV1N possible liability and direct responsibility relative to machine SMITH. Electronics 85 (28 July 1983). Cooperative design is operators and maintenance or service personnel. The based on an oxide-isolated, 3-/~m C-MOS process using environmentalimpact of any plasma installation must always multilevel metalization interconnection, be considered. We offer some "food for thought" for the plasma engineer and the equipment vendor about exercising Design of central processor units with custom VLSI and gate these responsibilities during the installation and operation of array circuits. C. FERNANDES.Acta Electron. 25 (1) 15 (1983) plasma systems. Examples of plasma etch processes with (In French). This paper points out experience in custom emphasis on safety and environmental considerations are processor and gate array design. 16 bit central processor presented. units were designed for P800 minicomputers. The architecture and main characteristics of those integrated central Fast RAM corrects errors on chip. AURAN~ZEn KHAN. units are outlined. Results and comments for experimented Electronics 126 (8 September 1983). Prototype randommethods about microprogram debugging and test pattern access memory ups soft-error immunity with little penalty in generation are given (software and/or hardware models, access time but with increased yield. simulation). A gate array (Signetics 8A 1200) has been used for the design of memory management. Different parameters IC houses are fruitful in multipliers. LARRY WALLER. for choice are detailed, as well as the encountered problems. Electronics 155 (14 July 1983). Digital multiplier market, for years exclusively bipolar, may open up with arrival of LS1 techniques applied to mini-computers. L. QUERE. Acta cheaper, less power-hungry MOS parts. Electron. 25 (1) 9 (1983). (In French). Key architectural elements of mini-computers need to be realized with specific HMOS 2: the first step toward VLS1. B. BAYLAC,J. M. BRIO.; LSI and VLSI components. Several design techniques are and M. MONTIER. Rev. Tech. Thomson-CSF 15 (2) 437 (June used: gate arrays, cell library, or full custom design of the 1983). (In French). The combined evolution of silicon techfunction on silicon. More and more users will have access to nologies and MOS integrated circuit simulation and design these techniques in the future. However, the increasing methods makes it possible to develop complex products of complexity of the designs will still be a challenge for selecting the memory or microprocessor type. appropriate design methodologies and CAD tools. As early as 1980, EFCIS selected and installed the facilities required to preserve its independence in the area of spearhead Silicon-gate C-MOS chips gain immunity to SCR latchup, technologies. In 1983, this effort took concrete form when LARRY WAKEMAN. Electronics 136 (11 August 1983). products based on HMOS 2 technology went into proImproved processing deprives parasitic silicon controlled duction. In this paper, the authors describe the performance rectifiers of the current that unleashes their destructive characteristics, the application targets, the resources used tendencies, and the essential technological options. IC gives ear radio highly accurate digital tuning. JOHN GOSCH. Electronics 11E (8 September 1983). Chip reduces number of parts in radio, sends microcomputer signal and multipath level data to aid in search tuning process, Plasma processing: some safety, health and engineering considerations. G. K. HERU, R. E. CAFEREY,E. T. ECKROTH, Q. T. JARRETT, C. L. FRAUST and J. A. FULTON. Solid St. Technol. 185 (August 1983). Incorporating plasma processes into VLSI production facilities has become a prime activity of the plasma technologist. It is important to be aware of
7. S E M I C O N D U C T O R
INTEGRATED
Lowering of the breakdown voltage of silicon dioxide by asperities and at spherical electrodes. N. KLEIN and O. NEVAYLINNA. Solid-St. Electron. 26 (9) 883 (1983). The paper
Single-chip speech synthesizers speak well of their algorithms. DAKSHESH PARIKH. SUSAN CHARBONNEAU and SUSAN BARBER.Electronics 135 (28 July 1983). Parametric methods like linear predictive and formant coding are used extensively in speech-synthesis devices. 256-K dynamic RAM is more than just an upgrade. MICHAEL C. SMAYL1NG and MIKE MAEKAWA. Electronics 135 (25 August 1983). Silicides, lightly doped drain structures are being tuned for mass production of a next-generation part that improves on the 64-K workhorse.
CIRCUITS,
DEVICES
AND
MATERIALS
examines the assumption that asperities and corners in electrodes can be preferential sites for electrical breakdown of silicon dioxide capacitors. It was assumed for this purpose
World Abstracts on Microelectronics and Reliability
electrically induced latch-up circuit paths in a variety of commercially available bulk CMOS devices. The method and results are compared to those reported by others using electron beam induced current and liquid crystal techniques.
cannot be clearly identified, and different technologies could favor different SOl approaches. VHSIC/VLS1 packaging update. RON ISCOFF. Semicomluctor Int. 52 (July 19'83). The greater complexity and faster operating speeds of today's integrated circuits are among the forces driving the semiconductor industry to review device packaging choices.
ComparisonofdifferentSOItechnologies:assetsandliabilities. L. JASTRZEBSKI. RCA Rev. 44, 250 (June 1983). Different methods used to obtain silicon-over-insulator (SOI) films are compared, based on the information available in the literature. All techniques are briefly outlined and their assets and liabilities are compared with special emphasis on application in different present and future processing technologies, It seems that at the present stage of development the "leader"
Techniques of wire bond testing. PETER H. SIN¢;ER. Semiconductor Int. 76 (July 1983). Destructive pull testing is still the most commonly used method of checking wire bond quality, but nondestructive pull tests and ball bond shear tests are increasing in popularity.
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S ,
SYSTEMS
AND
EQUIPMENTS
Scan-path logic integrated on chip tests gate array. KEV1N possible liability and direct responsibility relative to machine SMITH. Electronics 85 (28 July 1983). Cooperative design is operators and maintenance or service personnel. The based on an oxide-isolated, 3-/~m C-MOS process using environmentalimpact of any plasma installation must always multilevel metalization interconnection, be considered. We offer some "food for thought" for the plasma engineer and the equipment vendor about exercising Design of central processor units with custom VLSI and gate these responsibilities during the installation and operation of array circuits. C. FERNANDES.Acta Electron. 25 (1) 15 (1983) plasma systems. Examples of plasma etch processes with (In French). This paper points out experience in custom emphasis on safety and environmental considerations are processor and gate array design. 16 bit central processor presented. units were designed for P800 minicomputers. The architecture and main characteristics of those integrated central Fast RAM corrects errors on chip. AURAN~ZEn KHAN. units are outlined. Results and comments for experimented Electronics 126 (8 September 1983). Prototype randommethods about microprogram debugging and test pattern access memory ups soft-error immunity with little penalty in generation are given (software and/or hardware models, access time but with increased yield. simulation). A gate array (Signetics 8A 1200) has been used for the design of memory management. Different parameters IC houses are fruitful in multipliers. LARRY WALLER. for choice are detailed, as well as the encountered problems. Electronics 155 (14 July 1983). Digital multiplier market, for years exclusively bipolar, may open up with arrival of LS1 techniques applied to mini-computers. L. QUERE. Acta cheaper, less power-hungry MOS parts. Electron. 25 (1) 9 (1983). (In French). Key architectural elements of mini-computers need to be realized with specific HMOS 2: the first step toward VLS1. B. BAYLAC,J. M. BRIO.; LSI and VLSI components. Several design techniques are and M. MONTIER. Rev. Tech. Thomson-CSF 15 (2) 437 (June used: gate arrays, cell library, or full custom design of the 1983). (In French). The combined evolution of silicon techfunction on silicon. More and more users will have access to nologies and MOS integrated circuit simulation and design these techniques in the future. However, the increasing methods makes it possible to develop complex products of complexity of the designs will still be a challenge for selecting the memory or microprocessor type. appropriate design methodologies and CAD tools. As early as 1980, EFCIS selected and installed the facilities required to preserve its independence in the area of spearhead Silicon-gate C-MOS chips gain immunity to SCR latchup, technologies. In 1983, this effort took concrete form when LARRY WAKEMAN. Electronics 136 (11 August 1983). products based on HMOS 2 technology went into proImproved processing deprives parasitic silicon controlled duction. In this paper, the authors describe the performance rectifiers of the current that unleashes their destructive characteristics, the application targets, the resources used tendencies, and the essential technological options. IC gives ear radio highly accurate digital tuning. JOHN GOSCH. Electronics 11E (8 September 1983). Chip reduces number of parts in radio, sends microcomputer signal and multipath level data to aid in search tuning process, Plasma processing: some safety, health and engineering considerations. G. K. HERU, R. E. CAFEREY,E. T. ECKROTH, Q. T. JARRETT, C. L. FRAUST and J. A. FULTON. Solid St. Technol. 185 (August 1983). Incorporating plasma processes into VLSI production facilities has become a prime activity of the plasma technologist. It is important to be aware of
7. S E M I C O N D U C T O R
INTEGRATED
Lowering of the breakdown voltage of silicon dioxide by asperities and at spherical electrodes. N. KLEIN and O. NEVAYLINNA. Solid-St. Electron. 26 (9) 883 (1983). The paper
Single-chip speech synthesizers speak well of their algorithms. DAKSHESH PARIKH. SUSAN CHARBONNEAU and SUSAN BARBER.Electronics 135 (28 July 1983). Parametric methods like linear predictive and formant coding are used extensively in speech-synthesis devices. 256-K dynamic RAM is more than just an upgrade. MICHAEL C. SMAYL1NG and MIKE MAEKAWA. Electronics 135 (25 August 1983). Silicides, lightly doped drain structures are being tuned for mass production of a next-generation part that improves on the 64-K workhorse.
CIRCUITS,
DEVICES
AND
MATERIALS
examines the assumption that asperities and corners in electrodes can be preferential sites for electrical breakdown of silicon dioxide capacitors. It was assumed for this purpose