- Email: [email protected]
drain MOSFETs using a twin SONOS memory structure
Solid-State Electronics 50 (2006) 914–919 www.elsevier.com/locate/sse
25-nm programmable virtual source/drain MOSFETs using a twin SONOS memory structure Woo Young Choi a,*, Byung Yong Choi a, Dong-Won Kim b, Choong-Ho Lee b, Donggun Park b, Jong Duk Lee a, Byung-Gook Park a a
b
School of Electrical Engineering and Computer Science, Seoul National University, College of Engineering, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea Device Research Team, Semiconductor R&D Center, Samsung Electronics Co., Yongin-city, Gyeonggi-do 449-711, Republic of Korea Received 13 April 2006; received in revised form 2 May 2006; accepted 3 May 2006
The review of this paper was arranged by A.A. Iliadis and P.E. Thompson
Abstract 25-nm PVS MOSFETs using a twin SONOS memory structure have been successfully fabricated and characterized for the first time. Compared with our previous study, the gate length, the gate oxide thickness and the storage node length are scaled down to 25, 4, and 20 nm, respectively. When erased, they show a normal transistor operation with short channel effect suppressed. However, when programmed, they remain in OFF state regardless of the gate voltage. It is confirmed that PVS MOSFETs have a good feasibility for mobile applications which require both high performance and low-power consumption. 2006 Elsevier Ltd. All rights reserved. Keywords: PVS MOSFET; SONOS; High performance; Low-power consumption
1. Introduction With an emergence of increasing demand of mobile applications, much attention has been aroused in lowpower devices. Low-power operation requires small stand-by current and well-controlled short channel effect. On the other hand, recently, more and more mobile electronic devices are required to have a high performance since additional functions are converged into them. It means that high-performance device with low-power consumption is indispensable. However, in the case of a conventional MOSFET, it is difficult to meet both requirements at the same time as shown in Fig. 1. Thus, when low-power consumption is needed, MOSFETs tend to have a high threshold voltage in order to suppress the OFF *
Corresponding author. Tel.: +82 2 880 7279; fax: +82 2 882 4658. E-mail address: [email protected] (W.Y. Choi).
0038-1101/$ - see front matter 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2006.05.003
current (state 1). Conversely, high-performance applications need a low threshold voltage for maximum ON current (state 2). Generally, threshold voltage is modulated by changing the oxide thickness and the substrate doping concentration which become fixed after device fabrication. What is worse, the value of the subthreshold swing has a physical limit: 60 mV/dec at room temperature [1]. Therefore, only two options are available in conventional MOSFETs within given supply voltage range: high ON and OFF current (ION2, IOFF2) or low ON and OFF current (ION1, IOFF1). In this point of view, high-performance MOSFETs with low-power consumption may be controversial. As a way of overcoming the abovementioned problem, we have already proposed a programmable virtual source/drain (PVS) MOSFET using a twin silicon–oxide– nitride–oxide–silicon (SONOS) memory structure [2]. Since it adopts a non-volatile memory structure, whether storage nodes are programmed or erased determines the threshold
W.Y. Choi et al. / Solid-State Electronics 50 (2006) 914–919
-4
ION2 State 2
ION1
ID (A/μm)
10-5
State 1
10-6 10-7
IOFF2
10-8 10-9 10-10 0.0
IOFF1 0.4
0.8
1.2
VGS (V) Fig. 1. Two operation modes of MOSFETs. State 1 corresponds to lowpower consumption applications which require a high threshold voltage in order to suppress the OFF current. State 2 conforms to high-performance applications which demand a low threshold voltage in order to maximize the ON current.
voltage. When the storage nodes are programmed, n-channel PVS MOSFETs will have a high threshold voltage which corresponds to the state 1 in Fig. 1. If erased, they will show a low threshold voltage which conforms to the state 2. The underlying idea of PVS MOSFETs is as follows: the device remains in the state 1 when the system is idle to save the power but it turns into the state 2 when the system is in operation to extract maximum performance, which leads to high ON and low OFF current (ION2, IOFF1). Compared with substrate-bias control scheme [3], the PVS MOSFET shows better characteristics in terms of short-channel behavior and drain leakage current due to electrically induced source/drain extension. Since the devices in our previous works were designed for non-volatile memory applications rather than logic applications, their performance was lower than expected. In this paper, in order to enhance the performance of the device, we scaled the length of the gate and the thickness of the gate oxide down to 25 and 4 nm, respectively. Finally, it is demonstrated that PVS MOSFETs have a potential for the applications which needs both high performance and low-power consumption. 2. Device structure and fabrication The fabrication process flow is similar to that in Ref. [4]. However, some process parameters have been optimized for logic applications. Fig. 2 depicts the key process flow of n-channel version of PVS MOSFETs. Shallow trench isolation process was used for cell isolation. 125-nm thick silicon nitride and 150-nm thick plasma oxide layer as the etching mask of damascene gate process were deposited on the oxide/nitride/oxide (O/N/O) stack layer. Through these masking layers, the O/N/O region located at the channel center could be selectively removed to make two separate storage nodes. Then, main gate oxidation was fol-
915
lowed by poly-silicon deposition and chemical mechanical polishing (CMP) process. After wet removal of dummy silicon nitride mask, the outer sidewall spacer formation of N+ poly-silicon was performed to define O/N/O storage nodes around the main gate. Subsequently, low-energy implantation was done in order to form source/drain extension region which was followed by halo and highenergy implantation and annealing. Finally, cobalt silicide was used to merge the main gate and outer poly-Si sidewall spacer. The fabricated PVS MOSFET is shown in Fig. 3. The gate length (LG), the gate oxide thickness (Tox) and the storage node length (LS) are scaled down to 25, 4, and 20 nm, respectively. Additionally, the thickness of each O/N/O layer of storage node is measured to be 3.2/4.5/ 6.8 nm. On noteworthy thing is that the PVS MOSFET has a variable gate length. When erased, it has a gate length of 25 nm since the storage nodes induces source/ drain extension electrically. On the other hand, when programmed, its gate length is increased to 65 nm (LG + 2 · LS). Considering the total size it occupies, it is reasonable that total gate length amounts to 65 nm. 3. Results and discussion Table 1 summarizes program/erase bias conditions for PVS MOSFET operation. In erase mode, Fowler–Nordheim (FN) tunneling was adopted to inject holes into two storage nitrides. The PVS MOSFET has an electrically induced source/drain junction using hole-injected nitride in erase mode. On the other hand, three different schemes of channel hot electron injection (CHEI) were considered in program mode. Program 1 makes only the storage nitride near the source filled with electrons. The storage nitride near the drain becomes full of electrons in program 2. Program 3 is a sequence of the programs 1 and 2, which means that both of the storage nitrides are programmed by electrons. In the course of program 3, each operation does not influence each other [5]. In program mode, because the channel of the PVS MOSFET has a high potential barrier below storage nitrides, it is difficult for output current to flow between the source and the drain. To sum up, whether the PVS MOSFET is in erase or program mode can activate or deactivate it. Fig. 4 compares the transfer characteristics of the programs 1–3 mode in terms of threshold voltage shift and leakage current. Although the largest shift in threshold voltage is achieved in the program 3, significant leakage current is observed when drain voltage becomes 1.5 V, which prevents program mode from deactivating the device. To address the origin of the leakage current, drain and substrate current are monitored as shown in Fig. 5. It is found that most of leakage current comes from drain-tosubstrate current: gate induced drain leakage (GIDL) current. It is widely known that GIDL current increases as the channel doping concentration near the drain becomes higher [6]. In the programs 2 and 3 mode, high channel doping area is electrically induced near the drain region
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W.Y. Choi et al. / Solid-State Electronics 50 (2006) 914–919
Fig. 2. Key process flow of PVS MOSFETs. (a) Oxide/nitride dummy layer etch. (b) O/N/O storage node separation. (c) Main gate oxidation followed by poly-silicon deposition. (d) CMP process for main gate definition. (e) Dummy layer removal. (f) Outer sidewall spacer formation. (g) Low-energy implantation to form source/drain extension region. (h) High-energy implantation and annealing. (i) Silicidation to merge the main gate and outer poly-Si sidewall spacer.
due to electrons in the storage nitride. It makes drain junction more abrupt and leads to the GIDL current increase. Additionally, halo implantation process can be thought of as one of the reasons. Further process optimization may be necessary to suppress OFF current induced by GIDL. In this study, from now on, we will use only the program 1 to represent program modes where the threshold voltage is almost the highest and OFF current is the lowest. Fig. 6 shows the transfer curves of the fabricated PVS MOSFET in the initial, the erase, and the program 1 mode. Since the threshold voltage successfully shifts in each mode, the erase mode can activate the device for performance whereas the program 1 mode can deactivate the device for stand-by power saving. Table 2 summarizes some elec-
trical parameters in the case of each operation mode. In the case of the erase mode, 25-nm PVS MOSFETs have an ON and an OFF current of 716 lA/lm and 85 pA/lm, respectively. High ON/OFF current ratio in the erase mode is due to electrically induced source/drain junction using holeinjected nitride (activation state). On the contrary, the program 1 mode leads to high threshold voltage, which means output current hardly flows between the drain and the source (deactivation state). Moreover, the OFF current is reduced down to 2 pA/lm. If appropriate channel engineering is done, the OFF current resulting from GIDL current will be decreased further. Fig. 7 illustrates the change of threshold voltage with the variation of LG. In the erase mode, threshold voltage
W.Y. Choi et al. / Solid-State Electronics 50 (2006) 914–919
10-3
917
VD = 1.5V
Current (A/μm)
10-4 10-5 10-6 10-7
ID (Program1)
10
-8
IB (Program1)
10
-9
ID (Program2)
10
-10
IB (Program2)
10-11
ID (Program3)
10-12
IB (Program3)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VG (V) Fig. 5. Drain and substrate current with the variation of the gate voltage. Fig. 3. SEM image of the fabricated device.
Biasing condition VG (V)
ID (A/μm)
Erase (1 ms) Program 1 (10 ls) Program 2 (10 ls) Program 3 (10 ls + 10 ls)
VD (V)
VS (V)
VB (V)
5
5 5 6 0 4 6 4 0 Program 1 + Program 2
10-3 VD=0V, 1.5V 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 0.0 0.5 1.0 1.5
0 0 0
ID (A/μm)
Table 1 Erase and program biasing conditions for PVS MOSFET operation
10 -3 VD=0V, 1.5V 10 -4 10 -5 10 -6 10 -7 10 -8 10 -9 10 -10 10 -11 10 -12 10 -13 10 -14 0.0 0.5 1.0 1.5
Initial Erase Program1 2.0
2.5
3.0
VG (V) Fig. 6. Transfer characteristics of PVS MOSFETs in the initial, the erase, and the program 1 mode.
Program1 Program2 Program3 2.0
2.5
3.0
VG (V)
Table 2 Electrical characteristic summarization of PVS MOSFETs
DIBL (mV/V) SS (mV/dec) ION (lA/lm) IOFF (pA/lm)
Initial
Erase
Program 1
166 125 537 10
100 100 716 85
466 288 25 2
Fig. 4. Transfer characteristics of PVS MOSFETs in the programs 1–3 mode.
roll-off is suppressed down to 25 nm thanks to electrically induced shallow source/drain junction [7]. However, in the program 1 mode, threshold voltage exceeds 2 V and rolls up as the gate length decreases. It is easily understood considering the fact that LS is fixed at 20 nm. As LG decreases, the ratio of LG to LS becomes higher. In other words, the channel region which is not influenced by the storage nitride becomes smaller. Fig. 8 shows the ON and OFF current with LG varying from 25 to 75 nm. While the device acts as a normal transistor in the erase mode, it remains in OFF state regardless
of gate voltage in the program 1 mode. OFF current can be reduced further by optimizing process condition such as halo implantation. Thus, it is confirmed that the erase and the program 1 mode correspond to activation and deactivation state, respectively. Figs. 9 and 10 show the reliability characteristics in terms of endurance and retention. The endurance data of a fabricated PVS MOSFETs show reasonable threshold voltage variation up to 105 program/erase cycling due to its immunity to ‘hard-to-erase’ problem as shown in Fig. 9. The retention characteristics of Fig. 10 which were measured at 150 C also confirm the small charge loss characteristics of PVS MOSFETs. As the gate length of a cell transistor
918
W.Y. Choi et al. / Solid-State Electronics 50 (2006) 914–919
3.0
3.0
2.5
2.5
Initial Erase Program1
1.5
2.0
VTH (V)
VTH (V)
2.0
1.5
1.0
1.0
0.5
0.5
0.0
25
35
45
55
0.0
65
101 102 103 104 105 106 107 108 109
Time (sec)
LG (nm) Fig. 7. Threshold voltage variation as a function of LG. LS is fixed at 20 nm.
Fig. 10. Retention characteristics of PVS MOSFETs with program/erase state at 150 C baking condition.
charge loss though the tunnel oxide. In the measured devices, since the charges in the isolated nitride nodes are surrounded by the high energy barrier of oxide, its undesirable lateral charge diffusion is negligible and the threshold voltage decay can be small enough to show a stable non-volatile memory operation as shown in Fig. 10.
10-9 Initial Erase Program1
IOFF (A/μm)
Erase Program1
10-10
4. Conclusions 10-11
10-12 0
200
400
600
800
1000
ION (μA/μm) Fig. 8. ON and OFF current characteristics with LG varying from 25 to 75 nm.
3.5
Acknowledgments
3.0
This work was supported by the BK 21 program, by the Collaborative Project for Excellence in Basic System IC Technology and by the Nano-Systems Institute (NSINCRC) program sponsored by the Korea Science and Engineering Foundation (KOSEF).
2.5
V TH (V)
25-nm PVS MOSFETs were successfully fabricated and characterized. When erased, they show a normal transistor operation with short channel effect suppressed. However, when programmed, they remain in OFF state regardless of the gate voltage. The fabricated device has an ON current of 716 lA/lm in erase mode and an OFF current of 2 pA/lm in program mode. It is confirmed that PVS MOSFETs can be a promising candidate for mobile devices which require both high performance and low-power consumption.
2.0 Erase Program1
1.5 1.0
References
0.5
[1] Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong H-SP, et al. Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 2001;89(3):259–88. [2] Lee YK, Sung SK, Sim JS, Song KW, Lee JD, Park B-G, et al. Scalable 2-bit silicon–oxide–nitride–oxide–silicon (SONOS) memory with physically separated local nitrides under a merged gate. SolidState Electron 2004;48(10–11):1771–5. [3] Kuroda T, Suzuki K, Mita S, Fujita T, Yamane F, Sano F, Chiba A, Watanabe Y, Matsuda K, Maeda T, Sakurai T, Furuyama T, et al. Variable supply-voltage scheme for low-power high-speed CMOS digital design. IEEE J Solid-State Circ 1998;33(3):454–62.
0.0
10 0
10 1
10 2
10 3
10 4
10 5
Cycling numbers Fig. 9. Program/erase endurance characteristics of PVS MOSFETs.
is aggressively down-scaled, it is of importance that the lateral charge spreading has to be minimized together with
W.Y. Choi et al. / Solid-State Electronics 50 (2006) 914–919 [4] Choi BY, Park B-G, Lee YK, Sung SK, Kim TY, Cho ES, et al. Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50 nm NVM technology using outer sidewall spacer scheme with damascene gate process. Symposium on VLSI Technology 2005. p. 118–9. [5] Choi BY, Lee C-H, Lee YK, Shin H, Lee JD, Park B-G, et al. Investigation of lateral charge distribution of 2-bit SONOS memory
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devices using physically separated twin SONOS structure. ICMTS 2006:47–50. [6] Taur Y, Ning TH. Fundamentals of modern VLSI devices. Cambridge: Cambridge University Press; 1998. [7] Noda H, Murai F, Kimura S. Short channel characteristics of Si MOSFET with extremely shallow source and drain regions formed by inversion layers. IEEE Trans Electron Dev 1994;41(10):1831–6.
25-nm programmable virtual source/drain MOSFETs using a twin SONOS memory structure Woo Young Choi a,*, Byung Yong Choi a, Dong-Won Kim b, Choong-Ho Lee b, Donggun Park b, Jong Duk Lee a, Byung-Gook Park a a
b
School of Electrical Engineering and Computer Science, Seoul National University, College of Engineering, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea Device Research Team, Semiconductor R&D Center, Samsung Electronics Co., Yongin-city, Gyeonggi-do 449-711, Republic of Korea Received 13 April 2006; received in revised form 2 May 2006; accepted 3 May 2006
The review of this paper was arranged by A.A. Iliadis and P.E. Thompson
Abstract 25-nm PVS MOSFETs using a twin SONOS memory structure have been successfully fabricated and characterized for the first time. Compared with our previous study, the gate length, the gate oxide thickness and the storage node length are scaled down to 25, 4, and 20 nm, respectively. When erased, they show a normal transistor operation with short channel effect suppressed. However, when programmed, they remain in OFF state regardless of the gate voltage. It is confirmed that PVS MOSFETs have a good feasibility for mobile applications which require both high performance and low-power consumption. 2006 Elsevier Ltd. All rights reserved. Keywords: PVS MOSFET; SONOS; High performance; Low-power consumption
1. Introduction With an emergence of increasing demand of mobile applications, much attention has been aroused in lowpower devices. Low-power operation requires small stand-by current and well-controlled short channel effect. On the other hand, recently, more and more mobile electronic devices are required to have a high performance since additional functions are converged into them. It means that high-performance device with low-power consumption is indispensable. However, in the case of a conventional MOSFET, it is difficult to meet both requirements at the same time as shown in Fig. 1. Thus, when low-power consumption is needed, MOSFETs tend to have a high threshold voltage in order to suppress the OFF *
Corresponding author. Tel.: +82 2 880 7279; fax: +82 2 882 4658. E-mail address: [email protected] (W.Y. Choi).
0038-1101/$ - see front matter 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2006.05.003
current (state 1). Conversely, high-performance applications need a low threshold voltage for maximum ON current (state 2). Generally, threshold voltage is modulated by changing the oxide thickness and the substrate doping concentration which become fixed after device fabrication. What is worse, the value of the subthreshold swing has a physical limit: 60 mV/dec at room temperature [1]. Therefore, only two options are available in conventional MOSFETs within given supply voltage range: high ON and OFF current (ION2, IOFF2) or low ON and OFF current (ION1, IOFF1). In this point of view, high-performance MOSFETs with low-power consumption may be controversial. As a way of overcoming the abovementioned problem, we have already proposed a programmable virtual source/drain (PVS) MOSFET using a twin silicon–oxide– nitride–oxide–silicon (SONOS) memory structure [2]. Since it adopts a non-volatile memory structure, whether storage nodes are programmed or erased determines the threshold
W.Y. Choi et al. / Solid-State Electronics 50 (2006) 914–919
-4
ION2 State 2
ION1
ID (A/μm)
10-5
State 1
10-6 10-7
IOFF2
10-8 10-9 10-10 0.0
IOFF1 0.4
0.8
1.2
VGS (V) Fig. 1. Two operation modes of MOSFETs. State 1 corresponds to lowpower consumption applications which require a high threshold voltage in order to suppress the OFF current. State 2 conforms to high-performance applications which demand a low threshold voltage in order to maximize the ON current.
voltage. When the storage nodes are programmed, n-channel PVS MOSFETs will have a high threshold voltage which corresponds to the state 1 in Fig. 1. If erased, they will show a low threshold voltage which conforms to the state 2. The underlying idea of PVS MOSFETs is as follows: the device remains in the state 1 when the system is idle to save the power but it turns into the state 2 when the system is in operation to extract maximum performance, which leads to high ON and low OFF current (ION2, IOFF1). Compared with substrate-bias control scheme [3], the PVS MOSFET shows better characteristics in terms of short-channel behavior and drain leakage current due to electrically induced source/drain extension. Since the devices in our previous works were designed for non-volatile memory applications rather than logic applications, their performance was lower than expected. In this paper, in order to enhance the performance of the device, we scaled the length of the gate and the thickness of the gate oxide down to 25 and 4 nm, respectively. Finally, it is demonstrated that PVS MOSFETs have a potential for the applications which needs both high performance and low-power consumption. 2. Device structure and fabrication The fabrication process flow is similar to that in Ref. [4]. However, some process parameters have been optimized for logic applications. Fig. 2 depicts the key process flow of n-channel version of PVS MOSFETs. Shallow trench isolation process was used for cell isolation. 125-nm thick silicon nitride and 150-nm thick plasma oxide layer as the etching mask of damascene gate process were deposited on the oxide/nitride/oxide (O/N/O) stack layer. Through these masking layers, the O/N/O region located at the channel center could be selectively removed to make two separate storage nodes. Then, main gate oxidation was fol-
915
lowed by poly-silicon deposition and chemical mechanical polishing (CMP) process. After wet removal of dummy silicon nitride mask, the outer sidewall spacer formation of N+ poly-silicon was performed to define O/N/O storage nodes around the main gate. Subsequently, low-energy implantation was done in order to form source/drain extension region which was followed by halo and highenergy implantation and annealing. Finally, cobalt silicide was used to merge the main gate and outer poly-Si sidewall spacer. The fabricated PVS MOSFET is shown in Fig. 3. The gate length (LG), the gate oxide thickness (Tox) and the storage node length (LS) are scaled down to 25, 4, and 20 nm, respectively. Additionally, the thickness of each O/N/O layer of storage node is measured to be 3.2/4.5/ 6.8 nm. On noteworthy thing is that the PVS MOSFET has a variable gate length. When erased, it has a gate length of 25 nm since the storage nodes induces source/ drain extension electrically. On the other hand, when programmed, its gate length is increased to 65 nm (LG + 2 · LS). Considering the total size it occupies, it is reasonable that total gate length amounts to 65 nm. 3. Results and discussion Table 1 summarizes program/erase bias conditions for PVS MOSFET operation. In erase mode, Fowler–Nordheim (FN) tunneling was adopted to inject holes into two storage nitrides. The PVS MOSFET has an electrically induced source/drain junction using hole-injected nitride in erase mode. On the other hand, three different schemes of channel hot electron injection (CHEI) were considered in program mode. Program 1 makes only the storage nitride near the source filled with electrons. The storage nitride near the drain becomes full of electrons in program 2. Program 3 is a sequence of the programs 1 and 2, which means that both of the storage nitrides are programmed by electrons. In the course of program 3, each operation does not influence each other [5]. In program mode, because the channel of the PVS MOSFET has a high potential barrier below storage nitrides, it is difficult for output current to flow between the source and the drain. To sum up, whether the PVS MOSFET is in erase or program mode can activate or deactivate it. Fig. 4 compares the transfer characteristics of the programs 1–3 mode in terms of threshold voltage shift and leakage current. Although the largest shift in threshold voltage is achieved in the program 3, significant leakage current is observed when drain voltage becomes 1.5 V, which prevents program mode from deactivating the device. To address the origin of the leakage current, drain and substrate current are monitored as shown in Fig. 5. It is found that most of leakage current comes from drain-tosubstrate current: gate induced drain leakage (GIDL) current. It is widely known that GIDL current increases as the channel doping concentration near the drain becomes higher [6]. In the programs 2 and 3 mode, high channel doping area is electrically induced near the drain region
916
W.Y. Choi et al. / Solid-State Electronics 50 (2006) 914–919
Fig. 2. Key process flow of PVS MOSFETs. (a) Oxide/nitride dummy layer etch. (b) O/N/O storage node separation. (c) Main gate oxidation followed by poly-silicon deposition. (d) CMP process for main gate definition. (e) Dummy layer removal. (f) Outer sidewall spacer formation. (g) Low-energy implantation to form source/drain extension region. (h) High-energy implantation and annealing. (i) Silicidation to merge the main gate and outer poly-Si sidewall spacer.
due to electrons in the storage nitride. It makes drain junction more abrupt and leads to the GIDL current increase. Additionally, halo implantation process can be thought of as one of the reasons. Further process optimization may be necessary to suppress OFF current induced by GIDL. In this study, from now on, we will use only the program 1 to represent program modes where the threshold voltage is almost the highest and OFF current is the lowest. Fig. 6 shows the transfer curves of the fabricated PVS MOSFET in the initial, the erase, and the program 1 mode. Since the threshold voltage successfully shifts in each mode, the erase mode can activate the device for performance whereas the program 1 mode can deactivate the device for stand-by power saving. Table 2 summarizes some elec-
trical parameters in the case of each operation mode. In the case of the erase mode, 25-nm PVS MOSFETs have an ON and an OFF current of 716 lA/lm and 85 pA/lm, respectively. High ON/OFF current ratio in the erase mode is due to electrically induced source/drain junction using holeinjected nitride (activation state). On the contrary, the program 1 mode leads to high threshold voltage, which means output current hardly flows between the drain and the source (deactivation state). Moreover, the OFF current is reduced down to 2 pA/lm. If appropriate channel engineering is done, the OFF current resulting from GIDL current will be decreased further. Fig. 7 illustrates the change of threshold voltage with the variation of LG. In the erase mode, threshold voltage
W.Y. Choi et al. / Solid-State Electronics 50 (2006) 914–919
10-3
917
VD = 1.5V
Current (A/μm)
10-4 10-5 10-6 10-7
ID (Program1)
10
-8
IB (Program1)
10
-9
ID (Program2)
10
-10
IB (Program2)
10-11
ID (Program3)
10-12
IB (Program3)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VG (V) Fig. 5. Drain and substrate current with the variation of the gate voltage. Fig. 3. SEM image of the fabricated device.
Biasing condition VG (V)
ID (A/μm)
Erase (1 ms) Program 1 (10 ls) Program 2 (10 ls) Program 3 (10 ls + 10 ls)
VD (V)
VS (V)
VB (V)
5
5 5 6 0 4 6 4 0 Program 1 + Program 2
10-3 VD=0V, 1.5V 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 0.0 0.5 1.0 1.5
0 0 0
ID (A/μm)
Table 1 Erase and program biasing conditions for PVS MOSFET operation
10 -3 VD=0V, 1.5V 10 -4 10 -5 10 -6 10 -7 10 -8 10 -9 10 -10 10 -11 10 -12 10 -13 10 -14 0.0 0.5 1.0 1.5
Initial Erase Program1 2.0
2.5
3.0
VG (V) Fig. 6. Transfer characteristics of PVS MOSFETs in the initial, the erase, and the program 1 mode.
Program1 Program2 Program3 2.0
2.5
3.0
VG (V)
Table 2 Electrical characteristic summarization of PVS MOSFETs
DIBL (mV/V) SS (mV/dec) ION (lA/lm) IOFF (pA/lm)
Initial
Erase
Program 1
166 125 537 10
100 100 716 85
466 288 25 2
Fig. 4. Transfer characteristics of PVS MOSFETs in the programs 1–3 mode.
roll-off is suppressed down to 25 nm thanks to electrically induced shallow source/drain junction [7]. However, in the program 1 mode, threshold voltage exceeds 2 V and rolls up as the gate length decreases. It is easily understood considering the fact that LS is fixed at 20 nm. As LG decreases, the ratio of LG to LS becomes higher. In other words, the channel region which is not influenced by the storage nitride becomes smaller. Fig. 8 shows the ON and OFF current with LG varying from 25 to 75 nm. While the device acts as a normal transistor in the erase mode, it remains in OFF state regardless
of gate voltage in the program 1 mode. OFF current can be reduced further by optimizing process condition such as halo implantation. Thus, it is confirmed that the erase and the program 1 mode correspond to activation and deactivation state, respectively. Figs. 9 and 10 show the reliability characteristics in terms of endurance and retention. The endurance data of a fabricated PVS MOSFETs show reasonable threshold voltage variation up to 105 program/erase cycling due to its immunity to ‘hard-to-erase’ problem as shown in Fig. 9. The retention characteristics of Fig. 10 which were measured at 150 C also confirm the small charge loss characteristics of PVS MOSFETs. As the gate length of a cell transistor
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W.Y. Choi et al. / Solid-State Electronics 50 (2006) 914–919
3.0
3.0
2.5
2.5
Initial Erase Program1
1.5
2.0
VTH (V)
VTH (V)
2.0
1.5
1.0
1.0
0.5
0.5
0.0
25
35
45
55
0.0
65
101 102 103 104 105 106 107 108 109
Time (sec)
LG (nm) Fig. 7. Threshold voltage variation as a function of LG. LS is fixed at 20 nm.
Fig. 10. Retention characteristics of PVS MOSFETs with program/erase state at 150 C baking condition.
charge loss though the tunnel oxide. In the measured devices, since the charges in the isolated nitride nodes are surrounded by the high energy barrier of oxide, its undesirable lateral charge diffusion is negligible and the threshold voltage decay can be small enough to show a stable non-volatile memory operation as shown in Fig. 10.
10-9 Initial Erase Program1
IOFF (A/μm)
Erase Program1
10-10
4. Conclusions 10-11
10-12 0
200
400
600
800
1000
ION (μA/μm) Fig. 8. ON and OFF current characteristics with LG varying from 25 to 75 nm.
3.5
Acknowledgments
3.0
This work was supported by the BK 21 program, by the Collaborative Project for Excellence in Basic System IC Technology and by the Nano-Systems Institute (NSINCRC) program sponsored by the Korea Science and Engineering Foundation (KOSEF).
2.5
V TH (V)
25-nm PVS MOSFETs were successfully fabricated and characterized. When erased, they show a normal transistor operation with short channel effect suppressed. However, when programmed, they remain in OFF state regardless of the gate voltage. The fabricated device has an ON current of 716 lA/lm in erase mode and an OFF current of 2 pA/lm in program mode. It is confirmed that PVS MOSFETs can be a promising candidate for mobile devices which require both high performance and low-power consumption.
2.0 Erase Program1
1.5 1.0
References
0.5
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10 0
10 1
10 2
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10 5
Cycling numbers Fig. 9. Program/erase endurance characteristics of PVS MOSFETs.
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