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Drain breakdown voltage: A comparison between junctionless and inversion mode p-channel MOSFETs
Microelectronics Reliability 52 (2012) 1945–1948
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Drain breakdown voltage: A comparison between junctionless and inversion mode p-channel MOSFETs Seung Min Lee a, Chong Gun Yu a, Seung Min Jeong b, Won Ju Cho b, Jong Tae Park a,⇑ a b
Department of Electronics Engineering, University of Incheon, #119 Academi-Ro Yoonsu-Gu, Incheon 406–772, Republic of Korea Department of Electronic Materials Engineering, Kwangwoon University, #447-1 Wolgye-Dong Nowon-Gu, Seoul, Republic of Korea
a r t i c l e
i n f o
Article history: Received 25 May 2012 Received in revised form 12 June 2012 Accepted 13 June 2012 Available online 4 July 2012
a b s t r a c t A comparative study of the drain breakdown phenomena in junctionless (JL) and inversion mode (IM) pchannel MOSFETs has been investigated experimentally with different VGS, channel widths, and VSUB. In order to explain the dependence of drain breakdown voltages (BVDS) on VGS, 3-D device simulation has been also performed. When the device is turned ON, the BVDS is larger in JL than IM transistors. The BVDS is decreased with the increase of |VGS| in IM transistors but it is increased in JL transistors. When the device is turned OFF, the BVDS is larger in IM than JL transistors. The BVDS is decreased with the increase of channel width for JL and IM transistors. The BVDS is decreased in IM transistor when the back surface state of Si film is changed from the accumulation to the inversion but it is almost constant in JL transistors. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction Since the effective gate length in MOS transistor is now reaching less than ten nanometers, the diffusion of source and drain impurities into the channel region is a bottle neck in nanometer level CMOS devices. To overcome the significant problems occurred at the source and drain junctions, JL transistor, which the channel doping concentration and type are the same as in the source and drain region, has been drawing considerable attention in recent years [1]. It has been reported that the device characteristics are the same as IM or accumulation mode devices [2]. Besides that JL transistor avoids junction problems, it has many advantages such as reduced electric field perpendicular to current flow, low subthreshold slope, less NBTI and hot carrier induced device degradation [3,4]. However, a recent study indicated that JL transistors have reduced gate control and degraded short channel characteristics [5]. The device characterizations of JL transistors including the current voltage model, low temperature conductance oscillation, and noise properties have been reported [6,7]. Although the breakdown phenomenon determines the highest supply voltage and the device lifetime, the characterization of the source to drain breakdown in JL transistor has not been studied as far as we know. As the device dimensions of SOI MOSFETs are reduced to nanometer level, avalanche induced drain breakdown becomes a limiting factor in their operation. It is well known that the drain breakdown in SOI devices is less than bulk devices because the ⇑ Corresponding author. Tel.: +82 32 835 8445; fax: +82 32 835 0774. E-mail address: [email protected] (J.T. Park). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.06.018
hole/electron current generated via impact ionization near drain acts as base current for the parasitic bipolar junction transistor (PBT) [8]. The BVDS decreases as the decrease of silicon film thickness due to the increased lateral electric field. And the BVDS decreases as the channel width is increased due to enhanced impact ionization rate and lowered potential barrier between source and drain [9]. In this work, a comparative study on the BVDS between JL and IM p-channel MOSFET has been performed for different gate bias voltages, channel widths and VSUB. 2. Device fabrication and measurement The devices were fabricated on (100) standard Unibond SOI wafer with a 100 nm top silicon layer and a 200 nm buried oxide layer. The starting SOI film is p-type with a resistivity of 10– 20 Ocm. For the fabrication of JL transistor with a single gate, the whole silicon film was doped using ion shower with Boron source at 950 °C for 30 min. After defining the active channel region, the channel region was locally thinned down to 10 nm by Si etching using a 2.38% TMAH solution. To reduce the parasitic resistance of source and drain, the thinning of the channel region was carried out. The 10 nm thickness of gate oxide was deposited using sputtering. After performing of the activation, aluminum was deposited as a gate electrode material. The devices were subjected to post annealing in 2% mixed H2 and N2 gas for 30 min at 450 °C. No source and drain implantation was performed on the JL transistors. The doing concentration of the channel region and the source and drain was about 1 1019 cm 3. To compare the BVDS with JL
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S.M. Lee et al. / Microelectronics Reliability 52 (2012) 1945–1948
transistor, an IM p-channel MOSFET with a single gate was also fabricated as the same procedure as JL transistor without the doping concentration in the channel region. The doping concentration of source and drain was about 1 1020 cm 3. The channel region was not doped and thus the doping concentration could be assumed about 1 1015 cm 3. P+ poly silicon was deposited as a gate material. The devices fabricated here have a gate length of 2 lm. The channel widths are ranged from 2 lm to 20 lm. The electrical characteristics of devices have been simulated using the ATLAS 3-D numerical device simulator. A uniform doping concentration in the channel region and in the source/drain regions has been assumed as the fabricated devices. The gate length and channel width of the simulated devices are 1 lm and 100 nm, respectively. Physical models accounting for the impact ionization with electric field have been included in the simulation. 3. Results and discussion Fig. 1 shows IDS–VGS characteristics of JL transistors with the channel widths. The gate length (LG) is 2 lm and the channel widths (W) are 2 lm, 58 lm, and 10 lm. The extracted threshold voltage which was defined as a VGS to reach a constant drain current of 0.4 lA at VDS = 50 mV, was 1.45 V and the inverse subthreshold slope was 102 mV/dec. for W = 2 lm transistor. From the measured maximum transconductance, the calculated field effective hole mobility was 116 cm2/V s for W = 2 lm transistor. Fig. 2 shows the drain breakdown characteristics with different VGS for JL transistors. Based on the observation of the breakdown characteristics of a large number of measured devices, a method similar to that used to define threshold voltage was adopted here.
Since it is difficult to define the BVDS accurately and reproducibly, the peak of plotting d(log(ID))/dVDS as a function of the drain voltage was defined as a BVDS as in Ref.[9]. From Fig. 3, the measured BVDS is about 11.8 V at VGS–VTH = 0.5 V. Since the drain current in JL transistor is dominated by channel current, the BVDS increases as |VGS| increases. Fig. 3 shows the drain breakdown characteristics with different VGS for IM transistor. Since the PBT effect plays more prominent role in IM transistors, beyond BVDS the drain current of IM transistor increases more slowly with VDS than that of JL transistors. The measured BVDS is 10.2 V at VGS-VTH = 0.5 V. On the contrary to JL transistor, the BVDS of IM transistors is decreased as |VGS| increases. The dependence of BVDS on VGS is shown in Fig. 4 for JL and IM transistors. When the transistor is turned ON, the BVDS of JL transistor is larger than that of IM transistor although the BVDS of JL transistor is decreased with the decrease of |VGS|. However, the reverse phenomenon was observed when the transistor is turned OFF. The reduced BVDS with the increase of VGS-VTH in IM transistor has been attributed to PBT effect. Since there is a small potential barrier between the source (P+) and the channel region (P ) in IM transistor, the electron current generated via impact ionization acts as the base current for PBT. As |VGS| increase the base current is increased. The drain current is amplified by lateral PBT and hence the BVDS is decreased. However there is no potential barrier between the source and the channel region in JL transistor because the channel doping concentration and type are the same as in the source and drain region. As consequence, the electron generated via impact ionization flows into the source. In addition to no PBT effects, the decrease of the lateral electric field with increase of |VGS| in JL transistor could be a cause for the increase of the BVDS with increase |VGS|. For a short channel device, the more
Fig. 1. IDS–VGS charateristics of JL transistors with the channel widths. Fig. 3. Extraction of BVDS by the derivative method for IM transistor.
Fig. 2. Extraction of BVDS by the derivative method for JL transistor.
Fig. 4. BVDS as a function of VGS–VTH.
S.M. Lee et al. / Microelectronics Reliability 52 (2012) 1945–1948
significant decrease of BVDS is expected in IM transistor due to the enhanced PBT effects with the decrease of gate length. In order to understand why BVDS is larger in JL transistor than IM transistor at the turn ON bias condition, the devices have been simulated using the 3-dimensional ATLAS software [10] using the following parameters for JL transistors: channel width W = 100 nm, silicon film thickness, tSi = 10 nm, gate oxide thickness, TOX = 10 nm, and a gate length of 1 lm. The uniform p-type doping concentration of silicon film is NA = 1 1019 cm 3. Although the measured devices have a larger gate length (LG = 2 lm), both simulated and measured devices are long-channel devices and are expected to have the same electric field distribution at the drainchannel ‘‘junction’’. IM transistors were also simulated using the same parameters as the JL transistors, but with a n-type doping concentration of ND = 1 1015 cm 3 in the channel region and an p-type doping concentration of NA = 1 1020 cm 3 in the source and drain region. The physical models accounting for electric field-dependent carrier mobility, velocity saturation, SRH recombination and generation, band gap narrowing and impact ionization have been included in the simulation. Fig. 5 shows the lateral electric field and the impact ionization rate in JL and IM transistors at VGS-VTH = 1.0 V. It is clearly observed that the lateral electric field and the impact ionization rate are larger in IM transistor than JL transistor. The peak electric field and peak ionization rate are found at the drain junction in the IM transistor. However, the peak electric field is located in the drain for JL transistor, to the right of the gate edge. The drain potential drop spreads over a longer distance, and both the value of the peak electric field and ionization rate are lower than in the IM device. However, when the transistor is turned OFF, the increase of the lateral electric field and the integration of the impact ionization rate over the entire device in IM transistors, which yields a generation of drain current, are observed in Fig. 6. When the transistors are turned OFF, the bulk of the drain potential drop is found at the drain junction in IM transistor but it is found inside the drain electrode. Therefore, the entire channel region is pinched off in JL transistor and thus enhanced the integration of the impact ionization rate [3]. The dependence of BVDS on W is shown in Fig. 7 for JL and IM transistors. It is observed that the BVDS is larger in JL transistor than IM transistor and the BVDS is reduced with the increase of W for both devices. It is well known that the impact ionization rate at the channel edge is much lower than that at the channel center because it varies exponentially as a function of the electric field [9,11]. Since the back surface state of the Si film is dependent on the applying VSUB, the dependence of BVDS on VSUB is shown in Fig. 8 for JL and IM transistor. The BVDS of JL transistor is almost indepen-
Fig. 5. The lateral electric field and impact ionization rate in JL and IM transistor at VGS–VTH = 1.0 V.
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Fig. 6. The lateral electric field and impact ionization rate in JL and IM transistor at VGS–VTH = 0.5 V.
Fig. 7. Dependence of BVDS on W for JL and IM transistor.
Fig. 8. BVDS characteristics with different VSUB in JL (a) and IM transistor (b).
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S.M. Lee et al. / Microelectronics Reliability 52 (2012) 1945–1948
dent on VSUB. However, the BVDS of IM transistor is decreased when the back surfaces state is changed from the accumulation to the inversion state like the increase of the front gate |VGS|. 4. Conclusion When the transistor is turned ON, the drain breakdown voltage is smaller in IM transistor than JL transistor. The drain breakdown voltage of IM transistor is decreased as the gate voltage increases. However, the reverse phenomenon was observed in JL transistor. The larger drain breakdown voltage in IM transistor is due to the enhanced parasitic bipolar transistor effect and the larger lateral electric field. When the transistor is turned OFF, the drain breakdown voltage is smaller in JL transistor than IM transistor due to the larger electric field and integration of the impact ionization rate. The drain breakdown voltage is decreased with the increase of channel width for JL and IM transistors. The drain breakdown voltage is decreased in IM transistor when the back surface state of Si film is changed from the accumulation to the inversion but it is almost constant in JL transistor. Acknowledgements This work was supported by Basic Science Research Program through National Research Foundation of Korea funded by the Ministry of Education, Science and Technology (No. 2011-0021826).
References [1] Colinge JP, Lee CW, Afzalian A, Dehdashti N, Yan R, Ferain I, et al. Nanowire transistor without junctions. Nat Nanotechnol 2010;5:225–9. [2] Lee CW, Borne A, Ferain I, Afzalian A, Yan R, Dehdashti N, et al. High temperature performance of silicon junctionless MOSFET. IEEE Trans Electron Dev 2010;57:620–5. [3] Lee CW, Nazarov AN, Ferain I, Dehdashti N, Yan R, Razavi P, et al. Low subthreshold slope in junctionless multigate transistors. Appl Phys Lett 2010;96:102106. [4] Park JT, Kim JY, Colinge JP. Negative bias temperature instability and hot carrier effects in nanowire junctionless p-channel multiple gate transistors. Appl Phys Lett 2012;100:083504. [5] Rios R, Cappellani A, Armstrong M, Budrevich A, Gomez H, Pai R, et al. Comparison of junctionless and conventional trigate transistor with Lg down to 26 nm. IEEE Electron Dev Lett 2011;32:1170–2. [6] Duarte JP, Choi SJ, Choi YK. A full range drain current model for double gate junctionless transistors. IEEE Trans Electron Dev 2011;58:4219–25. [7] Park JT, Kim JY, Lee CW, Colinge JP. Low temperature conductance oscillation in junctionless nanowire transistors. Appl Phys Lett 2011;97:172101. [8] Young KK, Burns JA. Avalanche induced drain–source breakdown in silicon-oninsulator n-MOSFET’s. IEEE Trans Electron Dev 1988;35:426–31. [9] Lee CW, Afzalian A, Yan R, Akhavan ND, Xiong W, Colinge JP. Drain breakdown voltage in MuGFETs: influence of physical parameters. IEEE Trans Electron Dev 2008;55:3503–6. [10] http://www.silvaco.com/products/device_simulation/atlas.html. [11] Choi CH, Lee SH, Kim IK, Park YK, Kong JT. Analysis of channel width effects in 0.3 lm ultra thin SOI NMOSFETs. In: Proceeding of SISPAD; 1997. 37–40.
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Drain breakdown voltage: A comparison between junctionless and inversion mode p-channel MOSFETs Seung Min Lee a, Chong Gun Yu a, Seung Min Jeong b, Won Ju Cho b, Jong Tae Park a,⇑ a b
Department of Electronics Engineering, University of Incheon, #119 Academi-Ro Yoonsu-Gu, Incheon 406–772, Republic of Korea Department of Electronic Materials Engineering, Kwangwoon University, #447-1 Wolgye-Dong Nowon-Gu, Seoul, Republic of Korea
a r t i c l e
i n f o
Article history: Received 25 May 2012 Received in revised form 12 June 2012 Accepted 13 June 2012 Available online 4 July 2012
a b s t r a c t A comparative study of the drain breakdown phenomena in junctionless (JL) and inversion mode (IM) pchannel MOSFETs has been investigated experimentally with different VGS, channel widths, and VSUB. In order to explain the dependence of drain breakdown voltages (BVDS) on VGS, 3-D device simulation has been also performed. When the device is turned ON, the BVDS is larger in JL than IM transistors. The BVDS is decreased with the increase of |VGS| in IM transistors but it is increased in JL transistors. When the device is turned OFF, the BVDS is larger in IM than JL transistors. The BVDS is decreased with the increase of channel width for JL and IM transistors. The BVDS is decreased in IM transistor when the back surface state of Si film is changed from the accumulation to the inversion but it is almost constant in JL transistors. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction Since the effective gate length in MOS transistor is now reaching less than ten nanometers, the diffusion of source and drain impurities into the channel region is a bottle neck in nanometer level CMOS devices. To overcome the significant problems occurred at the source and drain junctions, JL transistor, which the channel doping concentration and type are the same as in the source and drain region, has been drawing considerable attention in recent years [1]. It has been reported that the device characteristics are the same as IM or accumulation mode devices [2]. Besides that JL transistor avoids junction problems, it has many advantages such as reduced electric field perpendicular to current flow, low subthreshold slope, less NBTI and hot carrier induced device degradation [3,4]. However, a recent study indicated that JL transistors have reduced gate control and degraded short channel characteristics [5]. The device characterizations of JL transistors including the current voltage model, low temperature conductance oscillation, and noise properties have been reported [6,7]. Although the breakdown phenomenon determines the highest supply voltage and the device lifetime, the characterization of the source to drain breakdown in JL transistor has not been studied as far as we know. As the device dimensions of SOI MOSFETs are reduced to nanometer level, avalanche induced drain breakdown becomes a limiting factor in their operation. It is well known that the drain breakdown in SOI devices is less than bulk devices because the ⇑ Corresponding author. Tel.: +82 32 835 8445; fax: +82 32 835 0774. E-mail address: [email protected] (J.T. Park). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.06.018
hole/electron current generated via impact ionization near drain acts as base current for the parasitic bipolar junction transistor (PBT) [8]. The BVDS decreases as the decrease of silicon film thickness due to the increased lateral electric field. And the BVDS decreases as the channel width is increased due to enhanced impact ionization rate and lowered potential barrier between source and drain [9]. In this work, a comparative study on the BVDS between JL and IM p-channel MOSFET has been performed for different gate bias voltages, channel widths and VSUB. 2. Device fabrication and measurement The devices were fabricated on (100) standard Unibond SOI wafer with a 100 nm top silicon layer and a 200 nm buried oxide layer. The starting SOI film is p-type with a resistivity of 10– 20 Ocm. For the fabrication of JL transistor with a single gate, the whole silicon film was doped using ion shower with Boron source at 950 °C for 30 min. After defining the active channel region, the channel region was locally thinned down to 10 nm by Si etching using a 2.38% TMAH solution. To reduce the parasitic resistance of source and drain, the thinning of the channel region was carried out. The 10 nm thickness of gate oxide was deposited using sputtering. After performing of the activation, aluminum was deposited as a gate electrode material. The devices were subjected to post annealing in 2% mixed H2 and N2 gas for 30 min at 450 °C. No source and drain implantation was performed on the JL transistors. The doing concentration of the channel region and the source and drain was about 1 1019 cm 3. To compare the BVDS with JL
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S.M. Lee et al. / Microelectronics Reliability 52 (2012) 1945–1948
transistor, an IM p-channel MOSFET with a single gate was also fabricated as the same procedure as JL transistor without the doping concentration in the channel region. The doping concentration of source and drain was about 1 1020 cm 3. The channel region was not doped and thus the doping concentration could be assumed about 1 1015 cm 3. P+ poly silicon was deposited as a gate material. The devices fabricated here have a gate length of 2 lm. The channel widths are ranged from 2 lm to 20 lm. The electrical characteristics of devices have been simulated using the ATLAS 3-D numerical device simulator. A uniform doping concentration in the channel region and in the source/drain regions has been assumed as the fabricated devices. The gate length and channel width of the simulated devices are 1 lm and 100 nm, respectively. Physical models accounting for the impact ionization with electric field have been included in the simulation. 3. Results and discussion Fig. 1 shows IDS–VGS characteristics of JL transistors with the channel widths. The gate length (LG) is 2 lm and the channel widths (W) are 2 lm, 58 lm, and 10 lm. The extracted threshold voltage which was defined as a VGS to reach a constant drain current of 0.4 lA at VDS = 50 mV, was 1.45 V and the inverse subthreshold slope was 102 mV/dec. for W = 2 lm transistor. From the measured maximum transconductance, the calculated field effective hole mobility was 116 cm2/V s for W = 2 lm transistor. Fig. 2 shows the drain breakdown characteristics with different VGS for JL transistors. Based on the observation of the breakdown characteristics of a large number of measured devices, a method similar to that used to define threshold voltage was adopted here.
Since it is difficult to define the BVDS accurately and reproducibly, the peak of plotting d(log(ID))/dVDS as a function of the drain voltage was defined as a BVDS as in Ref.[9]. From Fig. 3, the measured BVDS is about 11.8 V at VGS–VTH = 0.5 V. Since the drain current in JL transistor is dominated by channel current, the BVDS increases as |VGS| increases. Fig. 3 shows the drain breakdown characteristics with different VGS for IM transistor. Since the PBT effect plays more prominent role in IM transistors, beyond BVDS the drain current of IM transistor increases more slowly with VDS than that of JL transistors. The measured BVDS is 10.2 V at VGS-VTH = 0.5 V. On the contrary to JL transistor, the BVDS of IM transistors is decreased as |VGS| increases. The dependence of BVDS on VGS is shown in Fig. 4 for JL and IM transistors. When the transistor is turned ON, the BVDS of JL transistor is larger than that of IM transistor although the BVDS of JL transistor is decreased with the decrease of |VGS|. However, the reverse phenomenon was observed when the transistor is turned OFF. The reduced BVDS with the increase of VGS-VTH in IM transistor has been attributed to PBT effect. Since there is a small potential barrier between the source (P+) and the channel region (P ) in IM transistor, the electron current generated via impact ionization acts as the base current for PBT. As |VGS| increase the base current is increased. The drain current is amplified by lateral PBT and hence the BVDS is decreased. However there is no potential barrier between the source and the channel region in JL transistor because the channel doping concentration and type are the same as in the source and drain region. As consequence, the electron generated via impact ionization flows into the source. In addition to no PBT effects, the decrease of the lateral electric field with increase of |VGS| in JL transistor could be a cause for the increase of the BVDS with increase |VGS|. For a short channel device, the more
Fig. 1. IDS–VGS charateristics of JL transistors with the channel widths. Fig. 3. Extraction of BVDS by the derivative method for IM transistor.
Fig. 2. Extraction of BVDS by the derivative method for JL transistor.
Fig. 4. BVDS as a function of VGS–VTH.
S.M. Lee et al. / Microelectronics Reliability 52 (2012) 1945–1948
significant decrease of BVDS is expected in IM transistor due to the enhanced PBT effects with the decrease of gate length. In order to understand why BVDS is larger in JL transistor than IM transistor at the turn ON bias condition, the devices have been simulated using the 3-dimensional ATLAS software [10] using the following parameters for JL transistors: channel width W = 100 nm, silicon film thickness, tSi = 10 nm, gate oxide thickness, TOX = 10 nm, and a gate length of 1 lm. The uniform p-type doping concentration of silicon film is NA = 1 1019 cm 3. Although the measured devices have a larger gate length (LG = 2 lm), both simulated and measured devices are long-channel devices and are expected to have the same electric field distribution at the drainchannel ‘‘junction’’. IM transistors were also simulated using the same parameters as the JL transistors, but with a n-type doping concentration of ND = 1 1015 cm 3 in the channel region and an p-type doping concentration of NA = 1 1020 cm 3 in the source and drain region. The physical models accounting for electric field-dependent carrier mobility, velocity saturation, SRH recombination and generation, band gap narrowing and impact ionization have been included in the simulation. Fig. 5 shows the lateral electric field and the impact ionization rate in JL and IM transistors at VGS-VTH = 1.0 V. It is clearly observed that the lateral electric field and the impact ionization rate are larger in IM transistor than JL transistor. The peak electric field and peak ionization rate are found at the drain junction in the IM transistor. However, the peak electric field is located in the drain for JL transistor, to the right of the gate edge. The drain potential drop spreads over a longer distance, and both the value of the peak electric field and ionization rate are lower than in the IM device. However, when the transistor is turned OFF, the increase of the lateral electric field and the integration of the impact ionization rate over the entire device in IM transistors, which yields a generation of drain current, are observed in Fig. 6. When the transistors are turned OFF, the bulk of the drain potential drop is found at the drain junction in IM transistor but it is found inside the drain electrode. Therefore, the entire channel region is pinched off in JL transistor and thus enhanced the integration of the impact ionization rate [3]. The dependence of BVDS on W is shown in Fig. 7 for JL and IM transistors. It is observed that the BVDS is larger in JL transistor than IM transistor and the BVDS is reduced with the increase of W for both devices. It is well known that the impact ionization rate at the channel edge is much lower than that at the channel center because it varies exponentially as a function of the electric field [9,11]. Since the back surface state of the Si film is dependent on the applying VSUB, the dependence of BVDS on VSUB is shown in Fig. 8 for JL and IM transistor. The BVDS of JL transistor is almost indepen-
Fig. 5. The lateral electric field and impact ionization rate in JL and IM transistor at VGS–VTH = 1.0 V.
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Fig. 6. The lateral electric field and impact ionization rate in JL and IM transistor at VGS–VTH = 0.5 V.
Fig. 7. Dependence of BVDS on W for JL and IM transistor.
Fig. 8. BVDS characteristics with different VSUB in JL (a) and IM transistor (b).
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S.M. Lee et al. / Microelectronics Reliability 52 (2012) 1945–1948
dent on VSUB. However, the BVDS of IM transistor is decreased when the back surfaces state is changed from the accumulation to the inversion state like the increase of the front gate |VGS|. 4. Conclusion When the transistor is turned ON, the drain breakdown voltage is smaller in IM transistor than JL transistor. The drain breakdown voltage of IM transistor is decreased as the gate voltage increases. However, the reverse phenomenon was observed in JL transistor. The larger drain breakdown voltage in IM transistor is due to the enhanced parasitic bipolar transistor effect and the larger lateral electric field. When the transistor is turned OFF, the drain breakdown voltage is smaller in JL transistor than IM transistor due to the larger electric field and integration of the impact ionization rate. The drain breakdown voltage is decreased with the increase of channel width for JL and IM transistors. The drain breakdown voltage is decreased in IM transistor when the back surface state of Si film is changed from the accumulation to the inversion but it is almost constant in JL transistor. Acknowledgements This work was supported by Basic Science Research Program through National Research Foundation of Korea funded by the Ministry of Education, Science and Technology (No. 2011-0021826).
References [1] Colinge JP, Lee CW, Afzalian A, Dehdashti N, Yan R, Ferain I, et al. Nanowire transistor without junctions. Nat Nanotechnol 2010;5:225–9. [2] Lee CW, Borne A, Ferain I, Afzalian A, Yan R, Dehdashti N, et al. High temperature performance of silicon junctionless MOSFET. IEEE Trans Electron Dev 2010;57:620–5. [3] Lee CW, Nazarov AN, Ferain I, Dehdashti N, Yan R, Razavi P, et al. Low subthreshold slope in junctionless multigate transistors. Appl Phys Lett 2010;96:102106. [4] Park JT, Kim JY, Colinge JP. Negative bias temperature instability and hot carrier effects in nanowire junctionless p-channel multiple gate transistors. Appl Phys Lett 2012;100:083504. [5] Rios R, Cappellani A, Armstrong M, Budrevich A, Gomez H, Pai R, et al. Comparison of junctionless and conventional trigate transistor with Lg down to 26 nm. IEEE Electron Dev Lett 2011;32:1170–2. [6] Duarte JP, Choi SJ, Choi YK. A full range drain current model for double gate junctionless transistors. IEEE Trans Electron Dev 2011;58:4219–25. [7] Park JT, Kim JY, Lee CW, Colinge JP. Low temperature conductance oscillation in junctionless nanowire transistors. Appl Phys Lett 2011;97:172101. [8] Young KK, Burns JA. Avalanche induced drain–source breakdown in silicon-oninsulator n-MOSFET’s. IEEE Trans Electron Dev 1988;35:426–31. [9] Lee CW, Afzalian A, Yan R, Akhavan ND, Xiong W, Colinge JP. Drain breakdown voltage in MuGFETs: influence of physical parameters. IEEE Trans Electron Dev 2008;55:3503–6. [10] http://www.silvaco.com/products/device_simulation/atlas.html. [11] Choi CH, Lee SH, Kim IK, Park YK, Kong JT. Analysis of channel width effects in 0.3 lm ultra thin SOI NMOSFETs. In: Proceeding of SISPAD; 1997. 37–40.