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2DEG based on strained Si on SGOI substrate
ARTICLE IN PRESS
Physica E 40 (2008) 1611–1613 www.elsevier.com/locate/physe
2DEG based on strained Si on SGOI substrate L. Di Gasparea,, A. Notargiacomoa,b, E. Giovineb, M. De Setaa, G. Capellinia, M. Peaa, G. Ciascaa, F. Evangelistia,b a Dipartimento di Fisica, Universita` Roma Tre, Via Vasca Navale, 84-00146 Roma, Italy Istituto di Fotonica e Nanotecnologie, Consiglio Nazionale delle Ricerche, Via Cineto Romano 42, 00156 Roma, Italy
b
Available online 12 October 2007
Abstract We report on the realization of high-mobility two-dimensional electron gas based on modulation-doped Si/SiGe heterostructure grown directly on thin SiGe-On-Insulator (SGOI) substrate. The samples were grown by using low-pressure chemical vapor deposition. A pregrowth procedure for the cleaning of the SGOI surface that preserves the integrity and the composition of the substrate was developed. An electron mobility as high as 105 cm2 V1 s1 at T ¼ 0.4 K and 2000 cm2 V1 s1 at T ¼ 300 K was obtained. r 2007 Elsevier B.V. All rights reserved. PACS: 73.50.Dn; 81.15.Gh Keywords: SiGe heterostructure; SGOI; 2DEG
1. Introduction Semiconductor heterostructures, including tensilestrained Si, have been the subject of extensive studies since the attendant increase of the electron mobility improved the performances of very large-scale integrated circuits [1]. The conventional method for creating tensile strain in Si layers, which exploits the 4.2% lattice mismatch between Si and Ge, requires the growth of thick, high-quality, virtual substrates based on strain-relaxed compositionally graded SiGe layer [1,2]. However, the strain relaxation inevitably produces misfit dislocations and surface roughening that degrade the mobility [3]. For the next generation ultra large-scale integrated circuits, it will become essential the use of the SiGe-On-Insulator (SGOI) substrates with strained Si channel implemented directly on relaxed ultrathin SiGe device layer: the consequent performance benefits of Si/SiGe heterostructures will be combined with that of an insulating substrate, i.e. reduced short-channel effects, improved insulation and reduced parasitic capacitance [1,4]. However, the thermal processes necessary for implementing high quality growth on ultra-thin Corresponding author. Tel.: +39 06 55173315; fax: +39 06 55173431.
E-mail address: digaspare@fis.uniroma3.it (L. Di Gaspare). 1386-9477/$ - see front matter r 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.physe.2007.09.159
semiconductors on insulator substrates produces critical process limitations due to deterioration of the substrate integrity [5]. Enhanced electron mobility in strained Si has been previously reported in two-dimensional electron gases (2DEGs) based on modulation-doped heterostructures grown on Si substrate, with record values of the orders of 2900 cm2 V1 s1 at room temperature [6,7] and m44 105 cm2 V1 s1 at T=0.4 K [8]. 2DEGs deposited directly on SGOI substrate, avoiding the growth of the thick virtual substrate, should benefit from not only the thin-on-insulator substrate advantages but also the reduction of both leakage current and defect propagation toward the Si channel brought about by the thick defective SiGe layer [3,9]. 2. Experimental and discussion In this work, we report on the realization of 2DEG based on modulation-doped Si/SiGe heterostructures grown directly on SGOI substrate. The Si/SiGe heterostructures were grown by UHV low-pressure chemical vapor deposition technique. The morphological, structural and electrical properties of the grown samples were investigated by X-ray photoelectron spectroscopy (XPS), atomic force
ARTICLE IN PRESS 1612
L. Di Gaspare et al. / Physica E 40 (2008) 1611–1613
microscopy (AFM), Hall effect and conductivity measurements. The SGOI substrates, fabricated by smart-cut technique, were provided by SOITEC. Their structure consists of a 160-nm-thick BOX layer and 23-nm-thick GexSi1x device layer (x=0.2). The morphological AFM characterization of the SGOI wafer shows an rms roughness value of the order of 0.7 nm. A cleaning procedure of the SGOI surface suitable for the epitaxial growth was implemented. After a preliminary ultrasonic bath in isopropyl alcohol, the substrate was processed by an ex situ wet chemical cleaning in a H2O2:H2SO4=1:2 solution for 3 min, followed by a dip in 1% diluted hydrofluoric acid for 80 s. Finally, the substrate was immersed in H2O2:H2SO4=1:2 solution for 6 min. The pre-growth preparation of the SGOI surface was completed by an in situ thermal heating up to 900 1C in H2 atmosphere for desorbing the residual O and C present on the surface. XPS measurements on the substrate surface after each process step indicate that this cleaning procedure preserves the composition of SGOI layer. Before the growth of the 2DEG, a 100-nm-thick SiGe buffer layer was deposited on the clean SGOI substrate at T=850 1C. The 2DEG was obtained by growing at T=700 1C the following sequence of layers: (i) a tensile 11nm-thick Si channel layer, (ii) a 5-nm-thick Si0.80Ge0.20 spacer layer, and (iii) a 5-nm-thick n-doped Si0.80Ge0.20 layer. The structure was completed by a second 35-nmthick Si0.80Ge0.20 spacer layer followed by a final 15-nmthick Si cap layer. The morphology of the 2DEGs was characterized by AFM. The surfaces appeared homogenous with a low defect density (pits). The typical surface rms roughness was of the order of 3.6 nm, due to the presence of an irregular corrugation with maximum amplitude of 5.2 nm. This corrugation is significantly lower than that found on SiGe virtual substrates where the cross-hatch pattern dominates the surface morphology. No signature of cross-hatch pattern was found indicating that no misfit dislocations were present in the layers underneath the 2DEG. The transport properties of the 2DEGs were investigated in the 0.4–300 K temperature range by means of classical Hall effect and conductivity measurements in the Hall bar geometry. Fig. 1 shows typical measured electron mobility and carrier density as a function of the temperature. Upon decreasing the temperature, the electron mobility increases up to 99,800 cm2 V1 s1 at 0.4 K. This value is comparable with, or slightly lower than, that found in our 2DEG samples having the same layer sequence grown on Si substrates: the difference can be ascribed to residual defects at the SGOI substrate surface which, in principle, can be further controlled by optimization of the chemical and thermal processes. As for the carrier density, we found a small temperature dependence in the 15–300 K range. This temperature variation becomes smaller when the roomtemperature density n2D decreases below 1 1012 cm2 and disappears for samples with lowest n2D.
Fig. 1. Electron mobility (filled symbols) and carrier density (open symbols) of the 2DEG as a function of temperature. The dotted and dashed lines are a guide for eyes.
Fig. 2. Room-temperature electron mobility versus carrier density for several samples with nominally the same heterostructure sequence. The dotted line is a guide for eyes.
In Fig. 2, the room-temperature mobility of several samples with nominally the same heterostructure sequence is reported. We found a linear relationship between the measured mobility and carrier density. Both the n2D variations, as a function of temperature in Fig. 1 and the data reported in Fig. 2, can be explained by
ARTICLE IN PRESS L. Di Gaspare et al. / Physica E 40 (2008) 1611–1613
assuming a contribution to conduction from the parallel ndoped layer, which is relevant at high doping and at high temperature. Indeed, the conventional single conducting layer model, when used for data analysis in presence of a parallel parasitic layer, produces an overestimate of the actual 2DEG carrier density, compatible with the n2D variation observed in our samples and reported in Fig. 1 [10]. As a consequence, the mobility values reported in Fig. 2 underestimate the actual 2DEG mobility and the error is larger for larger values of carrier concentrations. Therefore, the actual mobility of our 2DEG on SGOI is at least the value found in the sample with the lowest carrier density. This mobility takes the value of 2000 cm2 V1 s1. 3. Conclusions We implemented a procedure for the cleaning of the SGOI surface that preserves the structural integrity and composition of the substrate on which it is then possible to grow 2DEGs with electron mobilities comparable with those usually found on similar samples grown on conventional Si substrate. An electron mobility as high as 105 cm2 V1 s1 at T ¼ 0.4 K and 2000 cm2 V1 s1 at T ¼ 300 K was obtained. Optimization of growth procedure will permit to benefit both the electrical performances
1613
of 2DEGs in SiGe heterostructure and the use of thin ‘‘on insulator’’ substrates. Acknowledgment This work was partially supported by the FIRB Project no. RBNE01FSWY ‘‘Nanoelettronica’’. References [1] M.L. Lee, E.A. Fitzgerald, M.T. Bulsara, M.T. Currie, A. Lochtefeld, J. Appl. Phys. 97 (2005) 011101. [2] Y. Shiraki, A. Sakai, Surf. Sci. Rep. 59 (2005) 153. [3] F. Scha¨ffler, Semicond. Sci. Technol. 12 (1997) 1515. [4] G.K. Celler, S. Cristoloveanu, J. Appl. Phys. 93 (2003) 4955. [5] D.T. Danielson, D.K. Sparacin, J. Michel, L.C. Kimerling, J. Appl. Phys. 100 (2006) 083507. [6] S.F. Nelson, K. Ismail, J.O. Chu, B.S. Meyerson, Appl. Phys. Lett. 63 (1993) 367. [7] L. Di Gaspare, K. Alfaramawi, F. Evangelisti, E. Palange, G. Barucca, G. Majni, Appl. Phys. Lett. 79 (2001) 2031. [8] K. Ismail, F.K. LeGoues, K.L. Saenger, M. Arafa, J.O. Chou, P.M. Mooney, V.B.S. Meyerson, Phys. Rev. Lett. 73 (1994) 3447. [9] L.J. Huang, J.O. Chu, D.F. Canaperi, C.P. D’Emic, R.M. Anderson, S.J. Koester, H.-S. Philip Wong, Appl. Phys. Lett. 78 (2001) 1267. [10] D.C. Look, C.E. Stutz, C.A. Bozada, J. Appl. Phys. 74 (1993) 311.
Physica E 40 (2008) 1611–1613 www.elsevier.com/locate/physe
2DEG based on strained Si on SGOI substrate L. Di Gasparea,, A. Notargiacomoa,b, E. Giovineb, M. De Setaa, G. Capellinia, M. Peaa, G. Ciascaa, F. Evangelistia,b a Dipartimento di Fisica, Universita` Roma Tre, Via Vasca Navale, 84-00146 Roma, Italy Istituto di Fotonica e Nanotecnologie, Consiglio Nazionale delle Ricerche, Via Cineto Romano 42, 00156 Roma, Italy
b
Available online 12 October 2007
Abstract We report on the realization of high-mobility two-dimensional electron gas based on modulation-doped Si/SiGe heterostructure grown directly on thin SiGe-On-Insulator (SGOI) substrate. The samples were grown by using low-pressure chemical vapor deposition. A pregrowth procedure for the cleaning of the SGOI surface that preserves the integrity and the composition of the substrate was developed. An electron mobility as high as 105 cm2 V1 s1 at T ¼ 0.4 K and 2000 cm2 V1 s1 at T ¼ 300 K was obtained. r 2007 Elsevier B.V. All rights reserved. PACS: 73.50.Dn; 81.15.Gh Keywords: SiGe heterostructure; SGOI; 2DEG
1. Introduction Semiconductor heterostructures, including tensilestrained Si, have been the subject of extensive studies since the attendant increase of the electron mobility improved the performances of very large-scale integrated circuits [1]. The conventional method for creating tensile strain in Si layers, which exploits the 4.2% lattice mismatch between Si and Ge, requires the growth of thick, high-quality, virtual substrates based on strain-relaxed compositionally graded SiGe layer [1,2]. However, the strain relaxation inevitably produces misfit dislocations and surface roughening that degrade the mobility [3]. For the next generation ultra large-scale integrated circuits, it will become essential the use of the SiGe-On-Insulator (SGOI) substrates with strained Si channel implemented directly on relaxed ultrathin SiGe device layer: the consequent performance benefits of Si/SiGe heterostructures will be combined with that of an insulating substrate, i.e. reduced short-channel effects, improved insulation and reduced parasitic capacitance [1,4]. However, the thermal processes necessary for implementing high quality growth on ultra-thin Corresponding author. Tel.: +39 06 55173315; fax: +39 06 55173431.
E-mail address: digaspare@fis.uniroma3.it (L. Di Gaspare). 1386-9477/$ - see front matter r 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.physe.2007.09.159
semiconductors on insulator substrates produces critical process limitations due to deterioration of the substrate integrity [5]. Enhanced electron mobility in strained Si has been previously reported in two-dimensional electron gases (2DEGs) based on modulation-doped heterostructures grown on Si substrate, with record values of the orders of 2900 cm2 V1 s1 at room temperature [6,7] and m44 105 cm2 V1 s1 at T=0.4 K [8]. 2DEGs deposited directly on SGOI substrate, avoiding the growth of the thick virtual substrate, should benefit from not only the thin-on-insulator substrate advantages but also the reduction of both leakage current and defect propagation toward the Si channel brought about by the thick defective SiGe layer [3,9]. 2. Experimental and discussion In this work, we report on the realization of 2DEG based on modulation-doped Si/SiGe heterostructures grown directly on SGOI substrate. The Si/SiGe heterostructures were grown by UHV low-pressure chemical vapor deposition technique. The morphological, structural and electrical properties of the grown samples were investigated by X-ray photoelectron spectroscopy (XPS), atomic force
ARTICLE IN PRESS 1612
L. Di Gaspare et al. / Physica E 40 (2008) 1611–1613
microscopy (AFM), Hall effect and conductivity measurements. The SGOI substrates, fabricated by smart-cut technique, were provided by SOITEC. Their structure consists of a 160-nm-thick BOX layer and 23-nm-thick GexSi1x device layer (x=0.2). The morphological AFM characterization of the SGOI wafer shows an rms roughness value of the order of 0.7 nm. A cleaning procedure of the SGOI surface suitable for the epitaxial growth was implemented. After a preliminary ultrasonic bath in isopropyl alcohol, the substrate was processed by an ex situ wet chemical cleaning in a H2O2:H2SO4=1:2 solution for 3 min, followed by a dip in 1% diluted hydrofluoric acid for 80 s. Finally, the substrate was immersed in H2O2:H2SO4=1:2 solution for 6 min. The pre-growth preparation of the SGOI surface was completed by an in situ thermal heating up to 900 1C in H2 atmosphere for desorbing the residual O and C present on the surface. XPS measurements on the substrate surface after each process step indicate that this cleaning procedure preserves the composition of SGOI layer. Before the growth of the 2DEG, a 100-nm-thick SiGe buffer layer was deposited on the clean SGOI substrate at T=850 1C. The 2DEG was obtained by growing at T=700 1C the following sequence of layers: (i) a tensile 11nm-thick Si channel layer, (ii) a 5-nm-thick Si0.80Ge0.20 spacer layer, and (iii) a 5-nm-thick n-doped Si0.80Ge0.20 layer. The structure was completed by a second 35-nmthick Si0.80Ge0.20 spacer layer followed by a final 15-nmthick Si cap layer. The morphology of the 2DEGs was characterized by AFM. The surfaces appeared homogenous with a low defect density (pits). The typical surface rms roughness was of the order of 3.6 nm, due to the presence of an irregular corrugation with maximum amplitude of 5.2 nm. This corrugation is significantly lower than that found on SiGe virtual substrates where the cross-hatch pattern dominates the surface morphology. No signature of cross-hatch pattern was found indicating that no misfit dislocations were present in the layers underneath the 2DEG. The transport properties of the 2DEGs were investigated in the 0.4–300 K temperature range by means of classical Hall effect and conductivity measurements in the Hall bar geometry. Fig. 1 shows typical measured electron mobility and carrier density as a function of the temperature. Upon decreasing the temperature, the electron mobility increases up to 99,800 cm2 V1 s1 at 0.4 K. This value is comparable with, or slightly lower than, that found in our 2DEG samples having the same layer sequence grown on Si substrates: the difference can be ascribed to residual defects at the SGOI substrate surface which, in principle, can be further controlled by optimization of the chemical and thermal processes. As for the carrier density, we found a small temperature dependence in the 15–300 K range. This temperature variation becomes smaller when the roomtemperature density n2D decreases below 1 1012 cm2 and disappears for samples with lowest n2D.
Fig. 1. Electron mobility (filled symbols) and carrier density (open symbols) of the 2DEG as a function of temperature. The dotted and dashed lines are a guide for eyes.
Fig. 2. Room-temperature electron mobility versus carrier density for several samples with nominally the same heterostructure sequence. The dotted line is a guide for eyes.
In Fig. 2, the room-temperature mobility of several samples with nominally the same heterostructure sequence is reported. We found a linear relationship between the measured mobility and carrier density. Both the n2D variations, as a function of temperature in Fig. 1 and the data reported in Fig. 2, can be explained by
ARTICLE IN PRESS L. Di Gaspare et al. / Physica E 40 (2008) 1611–1613
assuming a contribution to conduction from the parallel ndoped layer, which is relevant at high doping and at high temperature. Indeed, the conventional single conducting layer model, when used for data analysis in presence of a parallel parasitic layer, produces an overestimate of the actual 2DEG carrier density, compatible with the n2D variation observed in our samples and reported in Fig. 1 [10]. As a consequence, the mobility values reported in Fig. 2 underestimate the actual 2DEG mobility and the error is larger for larger values of carrier concentrations. Therefore, the actual mobility of our 2DEG on SGOI is at least the value found in the sample with the lowest carrier density. This mobility takes the value of 2000 cm2 V1 s1. 3. Conclusions We implemented a procedure for the cleaning of the SGOI surface that preserves the structural integrity and composition of the substrate on which it is then possible to grow 2DEGs with electron mobilities comparable with those usually found on similar samples grown on conventional Si substrate. An electron mobility as high as 105 cm2 V1 s1 at T ¼ 0.4 K and 2000 cm2 V1 s1 at T ¼ 300 K was obtained. Optimization of growth procedure will permit to benefit both the electrical performances
1613
of 2DEGs in SiGe heterostructure and the use of thin ‘‘on insulator’’ substrates. Acknowledgment This work was partially supported by the FIRB Project no. RBNE01FSWY ‘‘Nanoelettronica’’. References [1] M.L. Lee, E.A. Fitzgerald, M.T. Bulsara, M.T. Currie, A. Lochtefeld, J. Appl. Phys. 97 (2005) 011101. [2] Y. Shiraki, A. Sakai, Surf. Sci. Rep. 59 (2005) 153. [3] F. Scha¨ffler, Semicond. Sci. Technol. 12 (1997) 1515. [4] G.K. Celler, S. Cristoloveanu, J. Appl. Phys. 93 (2003) 4955. [5] D.T. Danielson, D.K. Sparacin, J. Michel, L.C. Kimerling, J. Appl. Phys. 100 (2006) 083507. [6] S.F. Nelson, K. Ismail, J.O. Chu, B.S. Meyerson, Appl. Phys. Lett. 63 (1993) 367. [7] L. Di Gaspare, K. Alfaramawi, F. Evangelisti, E. Palange, G. Barucca, G. Majni, Appl. Phys. Lett. 79 (2001) 2031. [8] K. Ismail, F.K. LeGoues, K.L. Saenger, M. Arafa, J.O. Chou, P.M. Mooney, V.B.S. Meyerson, Phys. Rev. Lett. 73 (1994) 3447. [9] L.J. Huang, J.O. Chu, D.F. Canaperi, C.P. D’Emic, R.M. Anderson, S.J. Koester, H.-S. Philip Wong, Appl. Phys. Lett. 78 (2001) 1267. [10] D.C. Look, C.E. Stutz, C.A. Bozada, J. Appl. Phys. 74 (1993) 311.