Performance and physics of sub-50 nm strained Si on Si1−xGex-on-insulator (SGOI) nMOSFETs

Solid-State Electronics 50 (2006) 566–572 www.elsevier.com/locate/sse

Performance and physics of sub-50 nm strained Si on Si1 xGex-on-insulator (SGOI) nMOSFETs F. Andrieu a,*, T. Ernst a, O. Faynot a, O. Rozeau a, Y. Bogumilowicz b, J.-M. Hartmann a, L. Bre´vard a, A. Toffoli a, D. Lafond a, B. Ghyselen c, F. Fournel a, G. Ghibaudo d, S. Deleonibus a a

CEA-LETI, Grenoble, 17 Avenue des Martyrs, 38054 Grenoble Cedex 9, France b STMicroelectronics, 850 Rue J. Monnet, 38926 Crolles Cedex, France c SOITEC, Parc Technologique des Fontaines, 38190 Bernin, France d IMEP, ENSERG, BP 257, 38016 Grenoble, France

Received 22 November 2005; received in revised form 8 March 2006; accepted 15 March 2006

The review of this paper was arranged by G. Ghibaudo and T. Skotnicki

Abstract Partially depleted floating body transistors on SGOI down to 30 nm gate length were fabricated and characterized. They demonstrate excellent static and RF performance. In particular, 40 nm gate length SGOI transistors exhibit a maximum oscillation frequency (fmax) estimated to be 150 GHz at VG = 0.4 V. The SGOI originality concerning the floating body effects, the RF characteristics and the short channel transport were in-depth studied in order to evaluate this architecture potentiality. Ó 2006 Elsevier Ltd. All rights reserved.

1. Introduction For the 45 nm technology node and below, the shortchannel effects control is a major issue. Unfortunately, many solutions which were proposed to solve this problem either tend to increase the source/drain resistance (use of thin low doped sources and drains and/or ultra-thin SOI) or degrade the short channel transistor mobility (through channel, pockets and halos over-doping). To relax the sub-30 nm gate length MOSFET process window and to improve the overall device performance, many researches have focused on carrier mobility enhancement. Strained Si on relaxed Si1 xGex on bulk Si(0 0 1) is a promising candidate. It demonstrated an up to 35% ON-state current improvement for 70 nm gate length nMOSFETs [1–4]. These results could be interesting for both CMOS high performance logic and for nMOS RF applications. However, *

Corresponding author. E-mail address: [email protected] (F. Andrieu).

0038-1101/$ - see front matter Ó 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2006.03.029

this architecture suffers from the usual strong parasitic capacitance of bulk substrates. There is thus a great interest for a buried oxide layer and consequently for strained silicon on relaxed Si1 xGex-on-insulator (SGOI) as an alternative to standard Si partially depleted (PD) MOSFETs. In the literature, short channel transistors on SGOI were fabricated and demonstrated ON-state current improvements [5–8]. Few studies about RF performance were performed on such devices, however. Another critical question is the challenging transport improvement scalability for sub-50 nm gate length SGOI [8] (as for substrate-induced strained-Si on bulk [9,10]). For this study, partially depleted transistors down to 30 nm gate length (LG) were fabricated and characterized to address these points. 2. Device description SGOI substrates were fabricated starting from relaxed Si0.2Ge0.8 epitaxial layers on bulk Si(0 0 1), transferred with the smart cutTM technology [11]. The tensile strain measured

F. Andrieu et al. / Solid-State Electronics 50 (2006) 566–572

567

Fig. 1. Atomic force microscopy surface image of a strained Si epitaxial layer on a Si0.8Ge0.2 on insulator substrate. RMS = 0.19 nm and Z range = 2.50 nm.

by Raman spectroscopy in the 15 nm thick Si channel epitaxially grown on top is equal to 1.3 GPa. After this process step, atomic force microscopy (AFM) revealed no crosshatch on the silicon surface (Fig. 1). Its roughness was as low as our SOI references (root mean square roughness = 0.19 nm and Z range = 2.5 nm). Then, 30 nm gate length devices featuring a 1.4 nm thick thermal SiO2 gate oxide, slim offset spacers, L-shaped spacers, a Ni-silicided gate and sources/drains were fabricated (see Fig. 2). Low doped drain (LDD) and pockets implants were carried out after the slim offset spacer formation. Transistors with and without pocket implants were fabricated to study the

short-channel electron transport limitations in SGOI. Note that no channel over-doping was introduced in the SGOI devices (process-matched with the SOI ones) in order to evaluate the intrinsic performances of this architecture. 3. Performance of floating body MOSFETs and floating body effect The ON-state (ION) vs. the OFF-state (IOFF) drain current is presented in Fig. 3. SOI devices demonstrated 630 lA/lm ION at 100 nA/lm IOFF and 1 V supply voltage (VDD = 1 V). The raw ION/IOFF trade-off is slightly better on SGOI than on SOI for short gate lengths. At a given gate length, we can see in Fig. 3 that ION and IOFF are higher for SGOI transistors than for SOI ones. To evaluate the influence of the floating body effects on the SOI and SGOI transistor ION–IOFF relationship, we

=30nm =35nm =40nm =45nm =90nm =500nm

-4

30nm -6

IOFF (A/µm)

sSi SiGe

-8 sGOI=open symb. SOI=full symb. -10

VDD=1V w/pockets Floating body

-12 0

Fig. 2. Cross sectional transmission electron microscopy image of a SGOI transistor. The physical gate length is 33 nm. Under the poly-Si/SiO2 gate stack, the measured strained Si and relaxed SiGe thicknesses are 12 nm and 41 nm, respectively.

500

1000

ION (µA/µm) Fig. 3. OFF-state vs. ON-state drain current at VDD = 1 V for SGOI (open symbols) and SOI (full symbols) floating body transistors.

F. Andrieu et al. / Solid-State Electronics 50 (2006) 566–572

studied the floating body effect on both architectures. We measured the drain current (ID) on floating and contacted body transistors (Fig. 4). The sub-threshold current at high drain voltages (VD) proves that the kink effect is slightly lower for SGOI devices. However, the maximum impact ionization (II) multiplication factor (defined as M = IB/ ID, where IB is the body current) is worse in SGOI than in SOI at 30 nm gate lengths (Fig. 5). But, for SGOI, the stronger II hole current recombines more easily with electrons of the source/drain regions, as proved by the diode characteristics (Fig. 6). This is due to a lower potential barrier for holes in Si1 xGex. Finally, the trade-off between the impact ionization and the recombining mechanisms leads to the same kink effects at 90 nm gate length and slightly lower ones at 30 nm (Fig. 4). This small floating body effect difference between SOI and SGOI cannot explain the ION– IOFF differences presented in Fig. 3. The VT mismatch is the main explanation. Indeed, the drain current characteristics of the 30 nmlong strained and unstrained floating body transistors are

10-3

LG=1µm WG=10µm VD=VS=VG=0V

10-5

Body Current (A)

568

SOI SGOI

10-7 10-9 10-11 10-13 10-15 -3

-2

-1

0

0.6

SOI CB

SOI FB

10-1 VD=1V

-3

Drain Current (A)

10

Threshold Voltage (V)

SGOI FB

Floating body

VD=50mV

10-5

2

Fig. 6. Diode characteristics of SGOI and SOI transistors.

VD = 50mV

0.4 SGOI CB

1

Body Voltage (V)

SOI 1V

0.2

200mV

50mV 0 SGOI

1V -0.2

10-7

w/pockets Floating Body -0.4 0.01

w/pockets LG=30nm WG=10µm

10-9 10-11 -1.5

-1

-0.5

0

0.5

1

0.1

1

10

Gate Length (µm) 1.5

Gate Voltage Overdrive (V)

Fig. 7. Linear (full symbols) and saturation (open symbols) threshold voltage vs. gate length for SGOI and SOI floating body transistors.

Fig. 4. Drain current vs. gate voltage overdrive at VD = 50 mV and 1 V for 30 nm gate length SGOI (full lines) and SOI (dashed lines) transistors. 0.6 VD=50mV

-6

4 10

0.4

Short Channel Effect (V)

II Multiplication Factor

Contacted body

3 10-6 SGOI

2 10-6 SOI 1 10-6 VD=1V LG=30nm WG=10µm 0 100 0

0.3

0.6

0.9

1.2

SOI 0.2

With pockets

0

-0.4 -0.6 0.01

1.5

Gate Voltage Overdrive (V) Fig. 5. Ionization by Impact coefficient vs. gate voltage overdrive for SOI and SGOI transistors.

Without pockets

SGOI -0.2

0.1

1

10

Gate Length (µm) Fig. 8. Threshold voltage variation (compared to the long channel VT) vs. gate length with (full symbols) and without (open symbols) BF2 pockets implants for SGOI and SOI floating body transistors.

F. Andrieu et al. / Solid-State Electronics 50 (2006) 566–572 500

Electron Mobility (cm2/ Vs)

similar when they are plotted vs. VG–VT (Fig. 4). So, the threshold voltage lowering in SGOI (see Fig. 7) is the reason why there is an IOFF increase in such devices. The VT shift is equal to 200 mV for long channel devices. It is due to the conduction band lowering in the strained Si layer. In devices without pocket implants, this VT-shift is kept even for short channel transistors (Fig. 8), suggesting that the tensile strain is kept. On the other hand, in devices with pocket implants, the reverse short channel effect is slightly lower in SGOI (Figs. 7 and 8). It is attributed to a lowered B diffusion in Si1 xGex. In this part, we have mainly discussed the threshold and sub-threshold SGOI characteristics, demonstrating that the VT-lowering in SGOI is responsible for its higher IOFF. In the following part, above-threshold parameters (gate transconductance, mobility) will be extracted to discuss the ION and transport difference between SOI and SGOI.

569

400 +43%

SGOI

300

SOI

200

LG=1µm

100

WG=10µm Contacted Body 0 0

13

2 10

1 10

Inversion Charge Density

13

(cm-2)

Fig. 10. Electron mobility vs. inversion charge density for body contacted SGOI and SOI transistors.

4. Mobility and transconductance 100

1000

4 10-4

Drain Current (A)

3 10-4

LG=1µm WG=10µm VD=50mV

SGOI

SOI 2 10-4

1 10-4

0 10

FB SOI FB SGOI CB SOI CB SGOI

0

-1

0

1

2

Gate Voltage Overdrive (V) Fig. 9. Drain current vs. gate voltage at VD = 50 mV for SGOI and SOI transistors in the floating or contacted body mode.

Gm max (µS/µm)

SOI w/ pockets SGOI w/pockets SOI w/o pockets SGOI w/o pockets

80 60

100

40

20

10 Gain w/pockets Gain w/o pockets 1 0.01

0.1

1

0

Gm max enhancement (%)

The gate induced floating body effect (GIFBE) [12], evidenced in Fig. 9, is the consequence of the body voltage enhancement by the hole gate current for ultra-thin gate oxide thicknesses at high gate voltages. It does not impact the high-VD ION (in particular for short channel lengths) but disturbs any mobility measurement at low VD. The latter must thus be carried out on contacted body transistors. When done, a 43% mobility enhancement is then highlighted for long channel SGOI (Fig. 10). However, this transport improvement is not maintained with the gate length scaling-down as suggested by the gm maximum (Fig. 11). Several assumptions were made in the literature to clarify such a phenomenon observed on different substrateinduced strained transistors. First, the pocket implant was proved to degrade both the mobility and the strain-induced mobility enhancement in many short strained MOSFETs [13,14]. In our case,

Contacted Body; VD=50mV

-20 10

Gate Length (µm) Fig. 11. Maximum of transconductance (and gm,max gain) of the contacted body transistor at VD = 50 mV for SGOI (full lines) and SOI (dashed lines) devices.

the SGOI-relative gm enhancement degrades both with and without pockets (Fig. 11). This is confirmed by the mobility extraction (Fig. 12). Thus, pocket implant is not the technological process step which limits the electron transport in these devices. Secondly, recent studies [14,15] evidenced that the series resistance (Rseries) and any neutral scattering are the main phenomena responsible for strained Si on Si1 xGex performance degradation when LG is reduced. HRTEM pictures revealed a zone of numerous lattice defects in strained Si under the offset spacers, i.e. at the edges of the electron conduction channel (Fig. 13). They might induce extra scatterings between the electrons and neutral defects and consequently change the main limiting transport mechanism for short channel lengths. Such crystalline defects could result either from the offset spacers etching or from the As implantation (1015 cm 2 at 3 keV). Note that a one hour 600 °C anneal was carried out on these samples after implantation. In standard SOI technology, it is

570

F. Andrieu et al. / Solid-State Electronics 50 (2006) 566–572 1200

2 10

600

SOI w/ pockets SGOI w/pockets SOI w/o pockets SGOI w/o pockets 0 0.01

11

SGOI SOI

0.1

Cut-Off Frequency (Hz)

Low field Mobility (cm2/Vs)

Contacted Body

LG

1 10

VD=1V LG=110; 60; 40nm WG=30*3µm 0

1

10

Gate Offset spacer

Fig. 13. HRTEM image of the tensily strained Si layer under the offset spacer regions showing crystalline defects in the S/D (LDD) implanted regions.

supposed to heal defects and to allow the lattice re-crystallization. It could be inefficient for SGOI devices, however. Finally, both the source/drain resistance and neutral defects in the source/drain region near the channel (rather than pockets induced Coulomb scattering) reduces the electron mobility for SGOI, limiting the transistor performance for short gate lengths. 5. RF and analog performance

0.7

Fig. 14. Cut-off frequency of SGOI (full lines) and SOI transistors (dashed lines) vs. gate voltage for different gate lengths.

resistances Rseries reduce the gm or fT gains. However, the gm/gd ratio proves the intrinsic SGOI potentialities for analog applications (Fig. 15). Finally, the SGOI power gain was measured vs. the frequency (Fig. 16). fmax was estimated to be 150 GHz at VD = 1 V and VG = 0.4 V. SGOI thus demonstrates quite well-balanced fT and fmax values thanks to a good short channel effects control down to 40 nm gate lengths. Consequently, this architecture is a promising candidate for RF applications. To evaluate the intrinsic and parasitic parameters of SGOI nMOSFETs, an equivalent circuit was used (Fig. 17). A specific extraction method was used with very good fitting results (see Fig. 18(a), for example). The parasitic elements (i.e. the parasitic drain and source resistances – Rd and Rs and capacitances – Cgde and Cgse) are similar between SOI and SGOI 40 nm transistors (W = 60 lm): Rd = Rs = 230 X lm and Cgs,e = Cgd,e = 25 fF (the overlap and fringe capacitances are evaluated to be Cov = 0.26 fF/ lm) for SGOI vs. Rd = Rs = 200 X lm and Cgs,e = Cgd,e = 24.7 fF for SOI. As for the extracted intrinsic parameters of 12 VD=1V VGT=0.4V f=2GHz 10

gm / gd factor

Fig. 12. Low field mobility extracted for SOI (dashed line) and SGOI (full line) with and without pockets.

0

Gate Voltage Overdrive (V)

Gate Length (µm)

5nm

11

SGOI 8

6

RF results confirm the conclusions obtained from static measurements. Long channel SGOI transistors present some interesting RF performance improvements. The enhancement of the cut-off frequency (fT) maximum is higher for longer gate lengths: 6%, 10% and 18%, at respectively, 40, 60 and 110 nm gate length and 30 fingers of 3 lm gate width at VD = 1 V (Fig. 14). Note that the parasitic

SOI

4 0

60

120

Gate Length (nm) Fig. 15. Ratio between the gate and the drain transconductances (gm/gd) vs. gate voltage for SGOI (full lines) and SOI (dashed lines) transistors.

F. Andrieu et al. / Solid-State Electronics 50 (2006) 566–572 50 LG=40nm

Power Gain (dB)

40

WG=60*1µm VD=1V ; VG=0.4V

SGOI

30

20

150 GHz

10

0

109

1010

1011

Frequency (Hz) Fig. 16. Power gain vs. frequency for 40 nm gate length transistors. fmax is evaluated to 150 GHz.

Rd

Cgs

Rgs

Cds

gm

Cgde

opposed to the long channel behavior). However, SGOI devices are still interesting because they exhibit better conductance (gds, see Fig. 18(b)). This is due to a lower DIBL in SGOI devices probably caused by the lower boron diffusion in SGOI (evocated in the previous part). Our RF model demonstrates that the parasitic components of our devices are quite high. If the parasitic components would be reduced to Rs = Rd = 100 X lm and Cov = 0.16 fF/lm, that is to say closer to the ITRS specification for the 65 nm technology node (i.e. Rs = Rd = 80 X lm and Cov = 0.08 fF/lm), our model predict that we would reach even more interesting RF performance: fmax = 290 Ghz and fT = 250 GHz. The intrinsic part of SGOI nMOSFETs are thus enough to reach the ITRS specifications. The limiting part is the parasitic one. 6. Conclusion A lot of challenges remain to get the best out of SGOI short channel devices. In particular, the parasitic series resistances must be lowered. It could be achieved thanks to Si raised source/drains and/or any improvement of the salicidation process. Moreover, the access must be defectfree for the carrier mobility in the channel not to be limited by parasitic scattering. This would allow to improve even more the SGOI performance. Nevertheless, we proved the large potentialities of strained Si on SGOI for logic or RF applications. In particular, a 45% long channel electron mobility enhancement, a promising ION–IOFF compromise and a 150 GHz fmax at 40 nm gate length were obtained.

Cgse Rg

571

gds

Rs

Fig. 17. Equivalent circuit used for the extraction of the RF model.

Acknowledgments Measurement Equivalent circuit

SGOI

SOI

Cgsi

15.0 fF

15.7 fF

gm

54.9 mS

53.2 mS

gds

7.78 mS

10.9 mS

Cds

20.0 fF

15.9 fF

S21 10xS12

S22

References

S11

(a)

This work was partially supported by the French Government under the ‘‘SMARTSTRAIN’’ RMNT Project and by the LETI-Alliance (STMicroelectronics, Philips, Freescale) joint program. The authors would like to thank Dr. Carron, P. Besson, Dr. Le Gouil, Dr. Chevolleau, C. Vizioz, C. Arvet, Dr. Aulnette for process engineering, H. Dansas for TEM sample preparation, Dr. Barraud, Dr. Guegan, Dr. Gwoziecki, Dr. Fenouillet-Berranger, Dr. Barbe´, Dr. Weber, Dr. Moriceau, Dr. Bensahel, Dr. Deguet, Dr. Boeuf, Dr. Cayrefourcq, Y. Campidelli and Dr. Raynaud for stimulating discussions and support.

(b)

Fig. 18. (a) Comparison of the RF model with the experimental measurements on SGOI transistors (WG = 60*1 lm; LG = 40 nm; 10 MHz < f < 40 GHz). (b) Extraction of the intrinsic elements of the RF model for SOI and SGOI transistors at VG = 0.4 V and VD = 1 V (WG = 60*1 lm; LG = 40 nm).

40 nm SGOI devices, they are summarized in Fig. 18(b). As demonstrated in the last part of this paper, the transconductance is similar for 40 nm SGOI and SOI devices (as

[1] Hoyt JL, Nayfeh HM, Eguchi S, Aberg I, Xia G, Drake T, et al. Strained silicon MOSFET technology. In: IEDM Tech Dig; 2002. p. 23–6. [2] Rim K, Koester S, Hargrove M, Chu J, Mooney PM, Ott J, et al. Strained Si nMOSFETs for high performance CMOS technology. In: Symp on VLSI Tech Dig; 2001. p. 59–60. [3] Hwang JR, Ho JH, Ting SM, Chen TP, Hsieh YS, Huang CC, et al. Performance of 70 nm strained-silicon CMOS devices. In: Symp VLSI Tech Dig; 2003. p. 103–4. [4] Bœuf F, Payet F, Casanova N, Campidelli Y, Villani N, Kermarrec O, et al. Strained-Si for CMOS 65 nm node: Si0.8Ge0.2 SRB or ‘‘Low Cost’’ approach. In: Proc SSDM, Tokyo, 2004. p. 16–17.

572

F. Andrieu et al. / Solid-State Electronics 50 (2006) 566–572

[5] Huang L-J, Chu JO, Goma S, D’Emic CP, Koester SJ, Canaperi DF, et al. Carrier mobility enhancement in strained Si-On-Insulator fabricated by wafer bonding. In Symp VLSI Tech Dig; 2001. p. 57–8. [6] Takagi S, Mizuno T, Tezuka T, Sugiyama N, Numata T, Usuda K, et al. Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-On-Insulator (Strained-SOI) MOSFETs. In: Proc IEDM Tech Dig; 2003. p. 57–60. [7] Sadaka M, Thean AV-Y, Barr A, Tekleab D, Kalpat S, White T, et al. Fabrication and operation of sub-50 nm strained-Si on Si1 xGex on Insulator (SGOI) CMOSFETs. In: Proc IEEE Int SOI Conf; 2004. p. 209–11. [8] Cai J, Rim K, Bryant A, Jenkins K, Ouyang C, Singh D, et al. Performance comparison and channel length scaling of strained Si FETs on SiGe-on-Insulator (SGOI). In: Proc IEDM Tech Dig; 2004. p. 165–8. [9] Goo J-S, Xiang Q, Takamura T, Wang H, Pan J, Arasnia F, et al. Scalability of strained-Si nMOSFETs down to 25 nm gate length. IEEE Electron Dev Lett 2003;24(5):351–3. [10] Sanuki T, Oishi A, Morimasa Y, Aota S, Kinoshita T, Hasumi R, et al. Scalability of strained silicon CMOSFET and high drive current in the 40 nm gate length technology. In: IEDM Tech Dig; 2003. p. 65–8.

[11] Ghyselen B, Ernst T, Hartmann J-M, Aulnette C, Osternaud B, Bogumilowicz Y, et al. Engineering strained silicon on insulator wafers with the Smart CutTM technology. Solid-State Electron 2004;48:1288–96. [12] Pretet J, Matsumoto T, Poiroux T, Cristoloveanu S, Gwoziecki R, Raynaud C, et al. New mechanism of body charging in partially depleted SOI-MOSFETs with ultra-thin gate oxides. In: Proc ESSDERC; 2002. p. 515–8. [13] Lusakowski J, Knap W, Meziani Y, Cesso J-P, El Fatimy A, Tauk R, et al. Ballistic and pocket limitations of mobility in nanometer Si metal-oxide semiconductor field-effect transistor. Appl Phys Lett 2005;87:053507. [14] Andrieu F, Ernst T, Lime F, Rochette F, Romanjek K, Barraud S, et al. Experimental and comparative investigation of low and high field transport in substrate-and process-induced strained nanoscaled MOSFETs. In: Symp VLSI Tech Dig, Kyoto, 2005. p.176–7. [15] Romanjek K, Andrieu F, Ernst T, Ghibaudo G. Characterization of the effective mobility by split C(V) technique in sub 0.1 lm Si and SiGe PMOSFETs. Solid-State Electron 2005;49:721–6.