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Buried channel silicon-on-insulator MOSFETs for hot-electron spectroscopy
Physica B 314 (2002) 354–357
Buried channel silicon-on-insulator MOSFETs for hot-electron spectroscopy Jinman Yanga, Trevor J. Thorntona,*, Stephen M. Goodnicka, Michael Kozickia, Joseph Lydingb a
Department of Electrical Engineering, Center for Solid State Electronics Research, Arizona State University, P.O. Box 875706, Tempe, AZ 85287-5706, USA b Beckman Institute, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA
Abstract Hot-carrier degradation in deep sub-micron MOSFETs can lead to shifts in the threshold voltage, reduction in effective mobility and transconductance, and reduced device reliability. Voltage and current stress measurements are often used to determine the hot-carrier degradation mechanisms. However, direct measurements of the hot-carrier distribution are difficult to make because the inversion layer in a conventional MOSFET is buried beneath the MOS gate material. In this paper, we describe a novel buried-channel silicon-on-insulator MOSFET that is suitable for hotelectron spectroscopy using a scanning-probe microscope. r 2002 Elsevier Science B.V. All rights reserved. Keywords: SOI MOSFETs; Electron transport; Device modeling
Hot-carrier transport is a well-known phenomenon in deep sub-micron MOSFETs [1]. It can lead to threshold voltage shifts, lower effective mobility and transconductance, and reduced device reliability. As CMOS scaling approaches its physical limit, these effects become more and more critical. Hot-carrier degradation depends on electron energy [1,2] and to better understand the mechanisms involved, it is important to know the energy distribution of the carriers as a function of the device bias. Measurements of hot luminescence from CMOS circuits have shown effective electron temperatures >2500 K [3]. However, in general, direct measurements of carrier energies in MOS*Corresponding author. Tel.: +1-480-965-3803; fax: +1480-965-3808. E-mail address: [email protected] (T.J. Thornton).
FETs are difficult, and the carrier-induced degradation mechanisms are usually inferred from indirect measurements such as voltage and current stressing. One of the main problems in directly extracting the carrier energy is the fact that the electron (or hole) inversion layer in a conventional MOSFET is buried beneath poly Si/SiO2 MOS layers. In this paper, we present experimental data and simulations from a novel, buried-channel, silicon-on-insulator (SOI) MOSFET. The electron inversion layer is formed at the interface between the SOI layer and the buried oxide (BOX) by applying a positive bias to the substrate. The SOI layer itself is only 40 nm thick and the inversion layer is close to the top surface, which is covered only by a thin native oxide. For this reason, hot electrons within the inversion layer are now accessible from the top surface by, for example,
0921-4526/02/$ - see front matter r 2002 Elsevier Science B.V. All rights reserved. PII: S 0 9 2 1 - 4 5 2 6 ( 0 1 ) 0 1 4 0 4 - 1
J. Yang et al. / Physica B 314 (2002) 354–357
scanning-probe measurements. Before discussing the possible STM-based measurements of the electron-energy distribution, we shall first describe the fabrication and characterization of the device. A cross-section through the SOI MOSFET is shown schematically in Fig. 1. The starting wafer is an SOI SIMOX (separation by implanted oxygen) substrate, doped p-type to a concentration of B1015 cm3. Device isolation is achieved by mesa-etching down to the BOX layer. An oxide layer is then deposited by plasma-enhanced chemical vapor deposition (PECVD) and windows down to the SOI layer are opened in the source and drain areas by wet etching with a HF buffered-oxide etch (BOE). Heavily doped n-type source and drain contacts are formed using spinon-glasses followed by rapid thermal annealing. The PECVD oxide acts as a diffusion barrier so that only the exposed regions of the SOI layer are doped. Another etch step is used to open via holes down to the silicon substrate below the BOX layer, to allow substrate connection. Finally, aluminum metal is deposited by lift-off and sintered to make electrical connection to the source, drain and substrate. The conducting channel is formed by applying, first, a positive bias to the substrate to create an electron-inversion layer at the interface
355
between the SOI layer and the BOX. A pair of split poly Si surface gates is patterned on the top surface as indicated in the plan view micrograph shown in Fig. 2. By applying a negative bias to the split top gate, we can reduce the charge in the underlying inversion layer. The current from the source to drain is then forced to flow through a narrow constriction formed in the gap between the split gate electrodes. Fig. 3 shows the drain current as a function of top gate voltage, VTG ; for different substrate voltages. We have fabricated a number of devices with various split gate length-to-width ratios. The turn-on characteristics of a device with a 2 mm long and 2 mm wide gap are shown in Fig. 3. The data show the characteristic step-like pinchoff expected for the split-gate geometry. For VTG o 2 V, the sheet density under the top gates is dramatically reduced and the drain current drops rapidly as it is forced to flow through the resulting constriction. We have performed simulations of the 3D electron concentration in the device using the Atlas simulator from Silvaco [4]. The electron concentration in the channel along a cut-line through the axis of the split gate is shown in Fig. 4 for different top gate and substrate biases. The three bias configurations represent the
V ds
STM tip
V Sub
SiO 2
inversion layer Fig. 1. Cross-section through the SOI MOSFET showing the bias arrangement. We propose a novel hot-electron spectroscopy technique that uses an STM tip to extract electrons from the buried-channel inversion layer.
Fig. 2. Optical micrograph showing a plan view of the completed device.
J. Yang et al. / Physica B 314 (2002) 354–357
356
10
-6
(a)
V Sub (V)
Current (A)
10
10
-7
(b)
5 4 3 2
-8
1 10
(c)
0
-9
-1 -2
10
-10
-8
-6
-4
-2
0
2
4
6
8
Split-Gate Voltage (V) Fig. 3. Turn-on characteristics of the device showing the drain current as a function of the split-gate voltage for different substrate biases. The solid circles marked (a), (b) and (c) indicate the bias conditions used to model the 3D carrier concentration shown in Fig. 4. For each case, Vds ¼ 0:1 V.
different operating regimes of the device, as shown by the solid circles in Fig. 3. For the case, Vsub ¼ 5 V and VTG ¼ 6 V, the density of inversion charge at both the lower and upper Si:SiO2 interfaces is high, and the flow of current is not constricted (Fig. 4a). However, by reducing the split gate voltage, the electron concentration directly under the poly Si gate is reduced as shown in Fig. 4b for the case Vsub ¼ 5 V and VTG ¼ 4 V. The electron concentration that remains under the split gate in Fig. 4b can be removed almost completely by reducing the substrate voltage, as shown in Fig. 4c for the case Vsub ¼ 0 V and VTG ¼ 4 V. The data in Fig. 4c indicates that the charge in the constriction falls abruptly at the edges, with very little lateral depletion from the edges of the split gate. It appears that the charge density at the upper surface is controlled mostly by the fixed positive interface charge that we have used in the simulations. The interface charge and trap density have been used as fitting parameters to obtain reasonable agreement between the measured and simulated data. The best fit is obtained by using a
Fig. 4. Electron-concentration profiles along the axis of the split gate. The bias conditions are: (a) Vsub ¼ 5 V, VTG ¼ 6 V, (b) Vsub ¼ 5 V, VTG ¼ 4 V and (c) Vsub ¼ 0 V, VTG ¼ 4 V. In each case, Vds ¼ 0:1 V. The modeling parameters are as follows: BOX thickness, 400 nm; native oxide thickness, 2 nm; gateoxide thickness, 25 nm; channel thickness 40 nm; fixed oxide charge (lower interface), 1 1011 cm2; fixed oxide charge (upper interface), 9 1011 cm2; and interface trap density (acceptor like), 8 1011 cm2.
fixed charge density of 9 1011 cm2 at the top surface, which is not unreasonably high for a silicon surface terminated by a native oxide. The abrupt nature of the electron-density profile suggests that much smaller constrictions could be achieved if the gap between the split gates was reduced. Achieving a gap of 0.1 mm is quite realistic by, for example, electron beam lithography and reactive ion etching. We have simulated the electron velocity in a 0:1 mm 0:1 mm constriction similar to the larger devices we have measured. Fig. 5 shows the electron velocity as a function of length along the center of the channel.
J. Yang et al. / Physica B 314 (2002) 354–357 7
-1
Electron Velocity (cm.s )
2 10
1 10
7
0 0
0 .0 4
0 .08
0 .12
Distance Along Channel (µ m) Fig. 5. The simulated electron velocity along the channel of a 0:1 mm 0:1 mm constriction. Vds=0.1 to 5.1 V in 1 V steps.
The velocity distribution is for electrons in a plane 3 nm below the native oxide. The electron velocity shows a clear peak at the drain end of the device where we expect the electric field to be a maximum. To validate the simulations, we propose using a scanning probe to measure the electron-energy distribution within narrow constrictions. The method is illustrated in Fig. 1. Prior to scanning probe measurements, the native oxide will be desorbed by a 9001C flash annealing in the UHV chamber of a scanning-probe microscope. All
357
contacts to the device will be silicide-based to withstand the annealing temperature. After the native oxide is removed, a scanning tunneling microscope will be used to map the electric field distribution along the constriction formed between the split gates. In addition, by applying a positive bias to the STM tip, electrons can be extracted from the channel and spectroscopic measurements made of their energy distribution. We expect that the STM measurements will be most sensitive to electrons near the surface of the SOI layer and it is for this reason that the data in Fig. 4 is for electrons in a plane 3 nm below the surface. The electron concentration in the narrow constriction is clearly different from that in a conventional short channel MOSFET. However, there is enough similarity, in that the direct measurements of electron energy that we are proposing will provide additional insight into the hot-electron transport in ultra-short channel MOSFETs. This work is supported by the Office of Naval Research.
References [1] Eiji Takeda, Cary Y. Yang, Akemi Miura-Hamada, Hotcarrier Effects in MOS Devices, Academic Press, San Diego, 1995. [2] D. Arnold, E. Cartier, D.J. Dimaria, Phys. Rev. B 49 (1994) 10278. [3] J.A. Kash, J.C. Tsang, Phys. Stat. Sol. B 204 (1997) 507. [4] Atlas, Silvaco International, Santa Clara, CA, 2000.
Buried channel silicon-on-insulator MOSFETs for hot-electron spectroscopy Jinman Yanga, Trevor J. Thorntona,*, Stephen M. Goodnicka, Michael Kozickia, Joseph Lydingb a
Department of Electrical Engineering, Center for Solid State Electronics Research, Arizona State University, P.O. Box 875706, Tempe, AZ 85287-5706, USA b Beckman Institute, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA
Abstract Hot-carrier degradation in deep sub-micron MOSFETs can lead to shifts in the threshold voltage, reduction in effective mobility and transconductance, and reduced device reliability. Voltage and current stress measurements are often used to determine the hot-carrier degradation mechanisms. However, direct measurements of the hot-carrier distribution are difficult to make because the inversion layer in a conventional MOSFET is buried beneath the MOS gate material. In this paper, we describe a novel buried-channel silicon-on-insulator MOSFET that is suitable for hotelectron spectroscopy using a scanning-probe microscope. r 2002 Elsevier Science B.V. All rights reserved. Keywords: SOI MOSFETs; Electron transport; Device modeling
Hot-carrier transport is a well-known phenomenon in deep sub-micron MOSFETs [1]. It can lead to threshold voltage shifts, lower effective mobility and transconductance, and reduced device reliability. As CMOS scaling approaches its physical limit, these effects become more and more critical. Hot-carrier degradation depends on electron energy [1,2] and to better understand the mechanisms involved, it is important to know the energy distribution of the carriers as a function of the device bias. Measurements of hot luminescence from CMOS circuits have shown effective electron temperatures >2500 K [3]. However, in general, direct measurements of carrier energies in MOS*Corresponding author. Tel.: +1-480-965-3803; fax: +1480-965-3808. E-mail address: [email protected] (T.J. Thornton).
FETs are difficult, and the carrier-induced degradation mechanisms are usually inferred from indirect measurements such as voltage and current stressing. One of the main problems in directly extracting the carrier energy is the fact that the electron (or hole) inversion layer in a conventional MOSFET is buried beneath poly Si/SiO2 MOS layers. In this paper, we present experimental data and simulations from a novel, buried-channel, silicon-on-insulator (SOI) MOSFET. The electron inversion layer is formed at the interface between the SOI layer and the buried oxide (BOX) by applying a positive bias to the substrate. The SOI layer itself is only 40 nm thick and the inversion layer is close to the top surface, which is covered only by a thin native oxide. For this reason, hot electrons within the inversion layer are now accessible from the top surface by, for example,
0921-4526/02/$ - see front matter r 2002 Elsevier Science B.V. All rights reserved. PII: S 0 9 2 1 - 4 5 2 6 ( 0 1 ) 0 1 4 0 4 - 1
J. Yang et al. / Physica B 314 (2002) 354–357
scanning-probe measurements. Before discussing the possible STM-based measurements of the electron-energy distribution, we shall first describe the fabrication and characterization of the device. A cross-section through the SOI MOSFET is shown schematically in Fig. 1. The starting wafer is an SOI SIMOX (separation by implanted oxygen) substrate, doped p-type to a concentration of B1015 cm3. Device isolation is achieved by mesa-etching down to the BOX layer. An oxide layer is then deposited by plasma-enhanced chemical vapor deposition (PECVD) and windows down to the SOI layer are opened in the source and drain areas by wet etching with a HF buffered-oxide etch (BOE). Heavily doped n-type source and drain contacts are formed using spinon-glasses followed by rapid thermal annealing. The PECVD oxide acts as a diffusion barrier so that only the exposed regions of the SOI layer are doped. Another etch step is used to open via holes down to the silicon substrate below the BOX layer, to allow substrate connection. Finally, aluminum metal is deposited by lift-off and sintered to make electrical connection to the source, drain and substrate. The conducting channel is formed by applying, first, a positive bias to the substrate to create an electron-inversion layer at the interface
355
between the SOI layer and the BOX. A pair of split poly Si surface gates is patterned on the top surface as indicated in the plan view micrograph shown in Fig. 2. By applying a negative bias to the split top gate, we can reduce the charge in the underlying inversion layer. The current from the source to drain is then forced to flow through a narrow constriction formed in the gap between the split gate electrodes. Fig. 3 shows the drain current as a function of top gate voltage, VTG ; for different substrate voltages. We have fabricated a number of devices with various split gate length-to-width ratios. The turn-on characteristics of a device with a 2 mm long and 2 mm wide gap are shown in Fig. 3. The data show the characteristic step-like pinchoff expected for the split-gate geometry. For VTG o 2 V, the sheet density under the top gates is dramatically reduced and the drain current drops rapidly as it is forced to flow through the resulting constriction. We have performed simulations of the 3D electron concentration in the device using the Atlas simulator from Silvaco [4]. The electron concentration in the channel along a cut-line through the axis of the split gate is shown in Fig. 4 for different top gate and substrate biases. The three bias configurations represent the
V ds
STM tip
V Sub
SiO 2
inversion layer Fig. 1. Cross-section through the SOI MOSFET showing the bias arrangement. We propose a novel hot-electron spectroscopy technique that uses an STM tip to extract electrons from the buried-channel inversion layer.
Fig. 2. Optical micrograph showing a plan view of the completed device.
J. Yang et al. / Physica B 314 (2002) 354–357
356
10
-6
(a)
V Sub (V)
Current (A)
10
10
-7
(b)
5 4 3 2
-8
1 10
(c)
0
-9
-1 -2
10
-10
-8
-6
-4
-2
0
2
4
6
8
Split-Gate Voltage (V) Fig. 3. Turn-on characteristics of the device showing the drain current as a function of the split-gate voltage for different substrate biases. The solid circles marked (a), (b) and (c) indicate the bias conditions used to model the 3D carrier concentration shown in Fig. 4. For each case, Vds ¼ 0:1 V.
different operating regimes of the device, as shown by the solid circles in Fig. 3. For the case, Vsub ¼ 5 V and VTG ¼ 6 V, the density of inversion charge at both the lower and upper Si:SiO2 interfaces is high, and the flow of current is not constricted (Fig. 4a). However, by reducing the split gate voltage, the electron concentration directly under the poly Si gate is reduced as shown in Fig. 4b for the case Vsub ¼ 5 V and VTG ¼ 4 V. The electron concentration that remains under the split gate in Fig. 4b can be removed almost completely by reducing the substrate voltage, as shown in Fig. 4c for the case Vsub ¼ 0 V and VTG ¼ 4 V. The data in Fig. 4c indicates that the charge in the constriction falls abruptly at the edges, with very little lateral depletion from the edges of the split gate. It appears that the charge density at the upper surface is controlled mostly by the fixed positive interface charge that we have used in the simulations. The interface charge and trap density have been used as fitting parameters to obtain reasonable agreement between the measured and simulated data. The best fit is obtained by using a
Fig. 4. Electron-concentration profiles along the axis of the split gate. The bias conditions are: (a) Vsub ¼ 5 V, VTG ¼ 6 V, (b) Vsub ¼ 5 V, VTG ¼ 4 V and (c) Vsub ¼ 0 V, VTG ¼ 4 V. In each case, Vds ¼ 0:1 V. The modeling parameters are as follows: BOX thickness, 400 nm; native oxide thickness, 2 nm; gateoxide thickness, 25 nm; channel thickness 40 nm; fixed oxide charge (lower interface), 1 1011 cm2; fixed oxide charge (upper interface), 9 1011 cm2; and interface trap density (acceptor like), 8 1011 cm2.
fixed charge density of 9 1011 cm2 at the top surface, which is not unreasonably high for a silicon surface terminated by a native oxide. The abrupt nature of the electron-density profile suggests that much smaller constrictions could be achieved if the gap between the split gates was reduced. Achieving a gap of 0.1 mm is quite realistic by, for example, electron beam lithography and reactive ion etching. We have simulated the electron velocity in a 0:1 mm 0:1 mm constriction similar to the larger devices we have measured. Fig. 5 shows the electron velocity as a function of length along the center of the channel.
J. Yang et al. / Physica B 314 (2002) 354–357 7
-1
Electron Velocity (cm.s )
2 10
1 10
7
0 0
0 .0 4
0 .08
0 .12
Distance Along Channel (µ m) Fig. 5. The simulated electron velocity along the channel of a 0:1 mm 0:1 mm constriction. Vds=0.1 to 5.1 V in 1 V steps.
The velocity distribution is for electrons in a plane 3 nm below the native oxide. The electron velocity shows a clear peak at the drain end of the device where we expect the electric field to be a maximum. To validate the simulations, we propose using a scanning probe to measure the electron-energy distribution within narrow constrictions. The method is illustrated in Fig. 1. Prior to scanning probe measurements, the native oxide will be desorbed by a 9001C flash annealing in the UHV chamber of a scanning-probe microscope. All
357
contacts to the device will be silicide-based to withstand the annealing temperature. After the native oxide is removed, a scanning tunneling microscope will be used to map the electric field distribution along the constriction formed between the split gates. In addition, by applying a positive bias to the STM tip, electrons can be extracted from the channel and spectroscopic measurements made of their energy distribution. We expect that the STM measurements will be most sensitive to electrons near the surface of the SOI layer and it is for this reason that the data in Fig. 4 is for electrons in a plane 3 nm below the surface. The electron concentration in the narrow constriction is clearly different from that in a conventional short channel MOSFET. However, there is enough similarity, in that the direct measurements of electron energy that we are proposing will provide additional insight into the hot-electron transport in ultra-short channel MOSFETs. This work is supported by the Office of Naval Research.
References [1] Eiji Takeda, Cary Y. Yang, Akemi Miura-Hamada, Hotcarrier Effects in MOS Devices, Academic Press, San Diego, 1995. [2] D. Arnold, E. Cartier, D.J. Dimaria, Phys. Rev. B 49 (1994) 10278. [3] J.A. Kash, J.C. Tsang, Phys. Stat. Sol. B 204 (1997) 507. [4] Atlas, Silvaco International, Santa Clara, CA, 2000.